Unit 4: Asynchronous Sequential Systems

Dr.Nijisha Shajil
Assistant Professor
Dept. of Biomedical Engineering, CET, SRMIST Ktr
Ph: 7299696765, email: [email protected]

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Unit 4: Asynchronous Sequential Systems

Topics
• Stable and Unstable states
• Fundamental and Pulse mode sequential circuits
• Output specifications
• Cycles and races, State reduction, race free assignments
• Hazards, Essential Hazards
• Design of Hazard free circuits.

Syllabus

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Unit 4: Asynchronous Sequential Systems

Asynchronous sequential circuits

• Sequential Circuits consists of a combinational circuit to which storage elements are
connected to form a feedback path. The storage elements are devices capable of
storing binary information. The binary information stored in these elements at any
given time defines the state of the sequential circuit at that time. The sequential circuit
receives binary information from external inputs that, together with the present state
of the storage elements, determine the binary value of the outputs.
• The next state of the storage elements is also a function of external inputs and the
present state. Thus, a sequential circuit is specified by a time sequence of inputs,
outputs, and internal states.

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Asynchronous sequential circuits

• The difference between Synchronous and Asynchronous Circuits is in
how the circuit goes for one Internal State to the Next Internal State.
• In a Synchronous Sequential Circuit all the State Variables representing
the internal state of the circuit change their state simultaneously with
a given input clock signal to achieve the next state.
• On the other hand in case of an Asynchronous Circuit all the State
Variables may not change their state simultaneously to achieve the
next steady internal state. In other words, the state variables are not
synchronized with any universal clock signal.

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Asynchronous sequential circuits

• Asynchronous sequential circuits, also known as self-timed or ripple-clock
circuits, are digital circuits that do not use a clock signal to determine the
timing of their operations. Instead, the state of the circuit changes in
response to changes in the inputs.
• In an asynchronous sequential circuit, each flip-flop has a different set of
inputs and outputs, and the state of the circuit is determined by the outputs
of the flip-flops.
• Asynchronous sequential circuits are used in digital systems to implement
state machines, which are digital circuits that change their output based on
the current state and the inputs. They are commonly used in applications
that require low power consumption or where a clock signal is not available
or practical to use.
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Asynchronous sequential circuits

Advantages
• No clock signal, hence no waiting for a clock pulse to begin processing
inputs, therefore fast.
• The absence of clock drivers reduces power consumption.
• Less sensitive to timing errors.
• Do not require the synchronization logic that is required in synchronous
sequential circuits, making their design simpler.
• Can be designed to change their state in response to changes in the inputs,
which makes them more flexible and adaptable to changing conditions.

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Asynchronous sequential circuits

Disadvantages
• More difficult to design and subject to problems like sensitivity to the
relative arrival times of inputs at gates. If transitions on two inputs
arrive at almost the same time, the circuit can go into the wrong state
depending on slight differences in the propagation delays of the gates
which are known as race condition.
• The lack of a clock signal makes the behavior of asynchronous
sequential circuits unpredictable, which can make them harder to
design and debug.
• Design of asynchronous sequential circuits can be complex, especially
for large systems with many state transitions.
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Asynchronous sequential circuits

• The storage elements commonly used in asynchronous sequential circuits
are time-delay devices. The storage capability of a time-delay device varies
with the time it takes for the signal to propagate through the device. In
practice, the internal propagation delay of logic gates is of sufficient
duration to produce the needed delay, so that actual delay units may not be
necessary.
• In gate-type asynchronous systems, the storage elements consist of logic
gates whose propagation delay provides the required storage. Thus, an
asynchronous sequential circuit may be regarded as a combinational circuit
with feedback. Because of the feedback among logic gates, an
asynchronous sequential circuit may become unstable at times. The
instability problem imposes many difficulties on the designer.

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Unit 4: Asynchronous Sequential Systems

Asynchronous sequential circuits

• Block diagram of Asynchronous sequential
circuits that consists of Combinational
circuits and delay elements connected to
form feedback.
• n-input variable, m-output variable, k
internal states
• Present state variables are called secondary
variables, and the next state variables are
called excitation variables.
• Propagation: Input x -> Combinational
circuit -> Y (excitation variable) -> Delay -> y
(Secondary variable)

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Asynchronous sequential circuits

• For a given value of input
variables, the system is stable if
the circuit reaches a steady state
condition with yi=Yi for i=1,2,…,k.
Otherwise, the circuit is in a
continuous transition and is said to
be unstable.
• Transition from one stable state to
another occurs only in response to
a change in an input variable.

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Asynchronous sequential circuits

• To ensure proper operation, the
circuit must be allowed to attain a
stable state before the input is
changed to a new value.
• Impossible to change two or more
inputs at the same time since there
will be delay in wires and the gate
circuits. Hence, only one input
variable can be changed at a time or
time between two input changes
must be longer than the time to
reach stable state. Such operation is
defined as fundamental mode.

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Modes of Asynchronous Sequential Machines

• Depending on the type of input variables, the way they are allowed to change etc. the
asynchronous sequential circuits are classified into:
• Fundamental mode circuits
• Pulsed mode circuits

Fundamental Mode Asynchronous Circuits:

• The fundamental mode asynchronous circuit design is based on the following
assumptions :
• The inputs to the synchronous circuits change only when the circuit is stable, that
means when the state variables are not in their transition state.
• Inputs are levels and not pulses.
• The state variables in these circuits are characterized as delay elements. Delay may be
introduced by a latch or by logic gates.

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Modes of Asynchronous Sequential Machines

Pulse Mode Asynchronous Circuits
• In the pulsed mode, the input variables are allowed to be applied in the form of pulses, rather
than in the form of levels.
• But the width of input pulses is a critical parameter. There are two restrictions on the width of the
input pulses.
• The first requirement is that the pulses should be long enough so that the circuit can respond
to them.
• The second requirement is that the pulses should not be too long so that they are still present
after the new secondary state is reached.
• The base of calculating the minimum pulse width is the propagation delay of the excitation logic.
• The maximum pulse width is calculated based on the total propagation delay through the
excitation logic and the memory.

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Analysis Procedure
• Obtain table or diagram that describes the
sequence of internal states and outputs as a
function of changes in input variables.
Transition table
• One input variable x and two internal states
(secondary variables y1 and y2, excitation variable
Y1 and Y2)
• Delay associated with feedback– propagation delay
between each y input to its corresponding Y output
• Logic gate delay: 2 to 10 ns, wires delay: 1 ns

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Analysis Procedure
• Derive Boolean expression for excitation variable as
function of input and secondary variable:

• Plot Y1 and Y2 in a K-map. (input x states)

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Analysis Procedure
• Transition table is obtained by combining the • Circle the values where Y=y -> indicates
binary values. stable condition.
• Circuit repeats the sequence of states – 00,
01, 11, 10 when input alternates between 0
and 1.
• The internal state changes immediately after
a change in input.
• Total state = internal state + input = y1y2x
• Stable total states for circuit -
000,011,110,101
• For a state to be stable, secondary variable
must match excitation variable (Y must be
same as y=y1y2).

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Analysis Procedure
Transition table
• Secondary variable – present states, Excitation variable – next states

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Analysis Procedure
Flow table
• Representing the states by letter symbols without referring their binary values

a=00,
This table is called a
b=01, Primitive flow table because
c=11, it has only one stable state in
each row.
d=10

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Race condition
• A race condition is said to exist in an asynchronous sequential circuit when two or more binary
state variables change value in response to a change in an input variable.
• When unequal delays are encountered, a race condition may cause the state variable to change
in an unpredictable manner. A race condition can cause the sequential circuit to enter an invalid
state.
• Example: Change of state variable from 00 to 11. Race condition: 00->01->11 or 00->10->11
• Noncritical race: When the stable state the circuit reaches does not depend on the order in
which the state variable changes
• Critical race: Reaching a different stable state based on the order in which the state variable
changes. Must be avoided.
• Races can be avoided by directing the circuit through intermediate unstable states with a unique
state variable change.

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Race condition
Changing input x from 0 to 1

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Cycle
• Races can be avoided by directing the circuit through intermediate unstable states with a unique
state-variable change.
• When a circuit goes through a unique sequence of unstable states, it is said to have a cycle.

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Unstable circuit
For input = 11, no stable state

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State reduction
• The state-reduction procedure for completely specified
state tables is based on an algorithm that combines two
states in a state table into one, as long as they can be
shown to be equivalent.
• Two states are equivalent if, for each possible input, they
give exactly the same output and go to the same next
states or to equivalent next states.

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Unit 4: Asynchronous Sequential Systems

• When this relationship exists, we say

that (a, b) imply (c, d) in the sense that
if a and b are equivalent then c and d
have to be equivalent.
• Similarly, from the last two rows of
Table 9.3, we find that the pair of
states (c, d) implies the pair of states
(a, b).
• The present states a and b have the same output
• The characteristic of equivalent states
for the same input.
is that if (a, b) imply (c, d) and (c, d)
• Their next states are c and d for x = 0 and b and a imply (a , b), then both pairs of states
for x = 1. are equivalent: that is, a and b are
• If we can show that the pair of states (c, d) are equivalent, and so are c and d.
equivalent, then the pair of states (a, b) will also
be equivalent, because they will have the same
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Race free state assignment

• Critical races can be avoided by making a binary state assignment
in such a way that only one variable changes at any given time
when a state transition occurs in the flow table.
• To accomplish this objective, it is necessary that states between
which transitions occur be given adjacent assignments.
• Two binary values are said to be adjacent if they differ in only one
variable. For example: 010 and 011 are adjacent because they
differ only in the third bit.

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Three row flow table

• The assignment of a single binary variable to a flow table with two rows
does not impose critical race problems. A flow table with three rows
requires an assignment of two binary variables

Inspection of the row reveals

that there is a transition from
state a to state b in column 01
and from state a to state c in
column 11. This information is
transferred into a transition
diagram.

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Unit 4: Asynchronous Sequential Systems

Three row flow table

• To avoid critical races, we must find a binary state assignment such that only one binary
variable changes during each state transition.
• An attempt to find such an assignment is shown in the transition diagram.
• State a is assigned binary 00, and state c is assigned binary 11. This assignment will cause
a critical race during the transition from a to c because there are two changes in the
binary state variables and the transition from a to c may occur directly or pass through b.
• A race-free assignment can be obtained if we add an extra row to the flow table.

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• The transition from a to c must now go through d, with the result that the binary variables
change from a = 00 to d = 10, to c = 11, thus avoiding a critical race.
• This is accomplished by changing row a, column 11 to d and row d, column 11, to c.
• Similarly, the transition from c to a is shown to go through unstable state d even though
column 00 represents a noncritical race .
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Hazard
• In designing asynchronous sequential circuits, care must be taken to conform with
certain restrictions and precautions to ensure that the circuits operate properly.
• The circuit must be operated in fundamental mode with only one input changing at any
time and must be free of critical races.
• In addition, there is one more phenomenon, called a hazard, that may cause the circuit
to malfunction.
• Hazards are unwanted switching transients that may appear at the output of a
circuit because different paths exhibit different propagation delays.
• Hazards occur in combinational circuits, where they may cause a temporary false output
value.
• When they occur in asynchronous sequential circuits, hazards may result in a transition
to a wrong stable state.
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Hazard • Assume that all three inputs are

• A hazard is a condition in which a change in a single initially equal to 1. This causes
variable produces a momentary change in output when the output of gate 1 to be 1,
no change in output should occur. that of gate 2 to be 0, and that
of the circuit to be 1.
• Now consider a change in x2
from 1 to 0.
• Then the output of gate 1
changes to 0 and that of gate 2
changes to 1, leaving the output
at 1.
• However, the output may
momentarily go to 0 if the
propagation delay through the
inverter is taken into
consideration.
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Hazard in combinational circuit

• The two circuits implement the Boolean
function in sum-of-products form :
Y = x1x2+x2’x3
• This type of implementation may cause the
output to go to 0 when it should remain at
1.
• If, however, the circuit is implemented instead in product-of-sums form namely,
Y = (x1+x2)’(x2+x3’)
then the output may momentarily go to 1 when it should remain 0.
• The first case is referred to as static 1-hazard and the second case as static 0-hazard.
• A third type of hazard, known as dynamic hazard, causes the output to change three or more
times when it should change from 1 to 0 or from 0 to 1.
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Hazard in combinational circuit

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Designing Hazard-free circuit

Y = x1x2+x2’x3

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Designing Hazard-free circuit

• The change in x2 from 1 to 0 moves the circuit
from minterm 111 to minterm 101.
• The hazard exists because the change in input
results in a different product term covering the
two minterms.
• The extra gate in the circuit generates the
product term x1x3 .
• In general, hazards in combinational circuits can
be removed by covering any two minterms that
may produce a hazard with a product term
common to both.
• The removal of hazards requires the addition of
redundant gates to the circuit.
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Hazard in sequential circuit

• If the circuit is in total stable state yx1x2 = 111 and input x2 changes from 1 to 0, the next total
stable state should be 110.
• However because of the hazard, output Y may go to 0 momentarily.
• If this false signal is fed back into gate 2 before the output of the inverter goes to 1, the output of
gate 2 will remain at 0 and the circuit will switch to the incorrect total stable state 010.

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Hazard in sequential circuit

To overcome this hazard:
• Adding extra gate
• Add SR latch – momentary 0
applied to an SR (NOR) latch or
momentary 1 applied to SR
(NAND) latch – no effect

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Essential Hazard
• This type of hazard is caused by unequal delays along two or more paths that originate from the
same input.
• An excessive delay through an inverter circuit in comparison to the delay associated with the
feedback path may cause such a hazard.
• Essential hazards cannot be corrected by adding redundant gates as in static hazards. The
problem that they impose can be corrected by adjusting the amount of delay in the affected
path.
• To avoid essential hazards, each feedback loop must be handled with individual care to ensure
that the delay in the feedback path is long enough compared with delays of other signals that
originate from the input terminals.
• This problem tends to be specialized, as it depends on the particular circuit used and the size of
the delays that are encountered in its various paths.

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