Unit 5: Programmable Logic Devices

Dr.Nijisha Shajil
Assistant Professor
Dept. of Biomedical Engineering, CET, SRMIST Ktr
Ph: 7299696765, email: [email protected]

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Unit 5: Programmable Logic Devices

Topics
• Logic families
• Propagation Delay, Fan – In and Fan – Out, Noise Margin
• RTL, TTL, ECL, CMOS
• Comparison of Logic families
• Implementation of combinational logic/sequential logic design using standard ICs
• PROM, PLA and PAL
• Basic memory, static ROM, PROM, EPROM, EEPROM, EAPROM

Syllabus

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Unit 5: Programmable Logic Devices

Integrated Circuits
• Integrated Circuits (IC) is a silicon semiconductor crystal, called a chip, containing the electronics
components for constructing digital gates. The various gates are interconnected inside the chip
to form the required circuit. The chip is mounted in a ceramic or plastic container and
connections are welded to external pins to form the integrated circuit.
• Digital ICs are often categorized according to the complexity of their circuits, as measured by the
number of logic gates in a single package.

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Digital logic families

• Digital integrated circuits are also classified by the specific circuit technology to which they belong to. The
circuit technology is referred to as digital logic families.
• Each logic family has its own basic electronic circuit upon which more complex digital circuits and
components are developed. The basic circuit in each technology is a NAND, NOR or inverter gate. The
electronic components employed in the construction of the basic circuit are usually used to name the
technology.
• Following are the most popular logic families of digital ICs:
RTL: Resistor-transistor logic
DTL - Diode-transistor logic
TTL: Transistor-transistor logic
ECL: Emitter coupled logic
MOS - Metal -oxide semiconductor
CMOS: Complementary metal-oxide semiconductor
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Digital logic families

• TTL is a logic family that has been in use for a long time and is considered to be standard.
• ECL has an advantage in systems requiring high-speed operation.
• MOS is suitable for circuits that need high component density, and CMOS is preferable in systems requiring low
power consumption, such as digital cameras and other handheld portable devices.
The most important parameters that are evaluated and compared are
• Fan-out specifies the number of standard loads that the output of a typical gate can drive without impairing its
normal operation. A standard load is usually defined as the amount of current needed by an input of another
similar gate in the same family.
• Fan-in is the number of inputs available in a gate.
• Power dissipation is the power consumed by the gate that must be availa ble from the power supply.
• Propagation delay is the average transition delay time for a signal to propagate from input to output.
• The operating speed is inversely proportional to the propagation delay.
• Noise margin is the maximum external noise voltage added to an input signal that does not cause an undesirable
change in the circuit output.

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Unit 5: Programmable Logic Devices

Digital logic gate

• Analyse a gate as electronic circuits – necessary to
investigate their input output relationship in terms
of two voltage levels: high level (H) and low level
(L)
• Assignment of binary 1 to H – positive logic system
• Assignment of binary 1 to L – negative logic system
• NAND gate
• If any input of a NAND gate is low, the output is high.
• If all inputs of a NAND gate are high, the output is
low.
• NOR gate
• If any input of a NOR gate is high, the output is low.
• If all inputs of a NOR gate are low, the output is high.

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Fan-out
• The fan-out of a gate specifies the number of standard loads that can be connected to the output
of the gate without degrading its normal operation. A standard load is usually defined as the
amount of current needed by an input of another gate in the same logic family.
• The output of a gate is usually connected to the inputs of other gates. Each input requires a
certain amount of current from the gate output, so that each additional connection adds to the
load of the gate.
• Loading rules are sometimes specified for a family of digital circuits. These rules give the
maximum amount of loading allowed for each output of each circuit in the family. Exceeding the
specified maximum load may cause a malfunction because the circuit cannot supply the power
demanded of it by its loads.
• The fan-out is the maximum number of inputs that can be connected to the output of a gate
and is expressed by a number. The fan-out is calculated from the amount of current available in
the output of a gate and the amount of current needed in each input of a gate.

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Unit 5: Programmable Logic Devices

Fan-out
• Consider the TTL gates which have the
values:

O- Output
I-Input
L-Low
H-High

• Therefore, the fan-out is 10. This means that

• The fan-out of the gate is calculated from the output of a TTL gate can be connected
the ratio IOH/IIH or IOL/IIL, whichever is to no more than 10 inputs of other gates in
smaller. the same logic family.

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Unit 5: Programmable Logic Devices

Power dissipation
• The power dissipation is a parameter expressed in milliwatts (mW) and represents the amount
of power needed by the gate from the power supply.
• An IC with four gates will require from its power supply, four times the power dissipated in
each gate.
Calculation
• Supply voltage = Vcc
• Current drawn by circuit = Icc
• Power = Voltage x Current = Vcc x Icc
• The current drawn from the power supply when the output of the gate is in the high-voltage
level is termed ICCH and when the output is in the low-voltage level, the current is ICCL.

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Unit 5: Programmable Logic Devices

Power dissipation
• The average current is

• The average power dissipated is

• Example: TTL NAND gate with Vcc=5v, ICCH=1mA, ICCL=3mA. 4 NAND gates. Power dissipation?
• Ans: 40mW

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Unit 5: Programmable Logic Devices

Propagation Delay
• The propagation delay of a gate is the average transition-delay time for the
signal to propagate from input to output when the binary input signal
changes.
• Signals through a gate take a certain amount of time to propagate from
input to output – Propagation delay of the gate
• Propagation delay is in nanoseconds (ns).
• The sum of propagation delays through the gates is the total delay of the
circuit.
• If speed of operation is important
• Each gate must have short Propagation delay
• Digital circuit must have minimum number of gates between i/p and o/p
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Unit 5: Programmable Logic Devices

Propagation Delay
• The signal-delay time between the input
and the output when the output changes
from high to low level is referred to as tPHL
• Similarly, when the output goes from low to
high level, the delay is tPLH
• It is customary to measure the time
between the 50 percent point on the input
and output transitions.
• Average of the above two terms is the
average propagation delay.
Example: Delays for a standard TTL gate are tPHL= 7 ns and tPLH = 11 ns. The average propagation
delay is?
Ans: 9 ns
Standard NAND gate tPHL= 15 ns and tPLH = 22 ns
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Noise margin
• Noise: Spurious electrical signals from industrial and other sources can
induce undesirable voltages on the connecting wires between logic circuits.
• Two types of noise:
• DC noise is caused by drift in the voltage level of a signal
• AC noise is a random pulse that maybe created by other switching signals

• Noise margin is the maximum noise voltage added to an input signal of a

digital circuit that does not cause an undesirable change in the circuit’s
output.
• It is expressed in volts.

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Unit 5: Programmable Logic Devices

Noise margin
• It is calculated from the knowledge of
the voltage signal available in the output
of the gate and the voltage signal
required in the input of the gate.
• Any voltage between Vcc and VOH is high
level state, and between VOL and 0 is low
level state.
• In order to compensate for noise signal,
the circuit must be designed so that VIL is
greater than V0L and VIH is less than V0H.

Noise margin is V0H - VIH or VIL - V0L

whichever is smaller
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Unit 5: Programmable Logic Devices

Bipolar junction transistor

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RTL and DTL circuit

RTL – Resistor transistor logic
• Each output is associated with one resistor and one transistor.
• The collectors of the transistors are tied together at the output
• The voltage level for the circuit are 0.2V for low level and 3.6V for high level

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Unit 5: Programmable Logic Devices

RTL circuit
• The analysis of the RTL gate is simple.
• If any input of the RTL gate is high, the corresponding transistor is driven
into saturation and the output goes low, regardless of the states of the
other transistors.
• If all inputs are low at 0.2 V, all transistors are cut off because VBE < 0.6 V and
the output of the circuit goes high approaching the value of the supply
voltage Vcc
• This confirms the conditions of a NOR gate
• Note that the noise margin for low signal input is 0.6 - 0.2 = 0.4V.

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DTL gate
• Each input is associated with one diode
• Diodes and 5 k ohm resistor form an AND gate
• Transistor serves as current amplifier and inverts the signal
• Low level – 0.2 V
• High level – 4 and 5 V

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• If any input of the gate is low at 0.2 V, the corresponding

input diode conducts current through Vcc and the 5 k ohm
resistor into the input node.
• The voltage at point P is equal to the input voltage of 0.2 V
plus a diode drop of 0.7 V, for a total of 0.9 V.
• In order for the transistor to start conducting, the voltage
at point P must overcome (i.e., be at least as high as) VBE
drop in Q1 plus two diode drops across DI and D2, or 3 X
0.6 = 1.8 V.
• Since the voltage at P is maintained at 0.9 V by the input
conducting diode, the transistor is cut off with no drop • The power dissipation of a DTL
across the 2k ohm resistor and the output voltage is high gate is about 12 mW and the
at 5 V. propagation delay averages 30
ns. The noise margin is about 1 V
• If all inputs are high, transistor is driven into saturation – and a fan-out as high as 8 is
output drops to 0.2V possible.
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Unit 5: Programmable Logic Devices

Transistor Transistor Logic (TTL)

• It is an improvement over DTL.
• Widely used in the design of digital systems
• Commercial TTL series starts with 74
• Speed-power product: The product of the propagation delay and power dissipation, and is
measured in picojoules (pJ). A low value for this parameter is desirable because it indicates that a
given propagation delay can be achieved without excessive power dissipation.

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Unit 5: Programmable Logic Devices

TTL
• The standard TTL gate was the first version in the TTL family. This basic gate
was then designed with different resistor values to produce gates with lower
power dissipation or with higher speed.
• The propagation delay of a transistor circuit that goes into saturation
depends mostly on two factors: storage time and RC time constants.
• Reducing the storage time decreases the propagation delay.
• Reducing resistor values in the circuit reduces the RC time constants and
decreases the propagation delay. But, the trade-off is higher power
dissipation because lower resistances draw more current from the power
supply.
• The speed of the gate is inversely proportional to the propagation delay.

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TTL
• In the low-power TTL gate, the resistor values are higher than in the standard gate in order to
reduce the power dissipation, but the propagation delay is increased.
• In the high-speed TTL gate, resistor values are lowered to reduce the propagation delay but the
power dissipation is increased.
• The Schottky TTL gate was the next improvement in the technology. The effect of the Schottky
transistor is to remove the storage time delay by preventing the transistor from going into
saturation. This series increases the speed of operation of the circuit without an excessive
increase in power dissipation.
• The low-power Schottky TTL sacrifices some speed for reduced power dissipation
• The advanced low-power Schottky has the lowest speed- power product and is the most efficient
series. The fast TTL family is the best choice for high-speed designs.

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TTL
• TTL gates come in three different types of output configuration
• Open collector output
• Totem pole output
• Three-state output

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Open collector TTL NAND gate

• The multiple emitters in transistor Q1
are connected to the inputs
• Emitters behave like the input diodes in
the DTL gate – base emitter junction –
pn diode
• Base collector junction of Q1 acts as pn
junction diode corresponding to D1
• Transistor Q2 replaces the second diode
D2
• The output of the TTL gate is taken
from the open collector of Q3
• The two voltage levels of TTL gate are
0.2 for low level and 2.4 to 5 V for high
level.
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Unit 5: Programmable Logic Devices

Open collector Output Gate

• If all inputs are high – base voltage of Q1 is
equal to the voltage across its base collector
pn junction plus VBE drops in Q2 and Q3 or
about 0.7x3=2.1 V
• Q2 and Q3 conduct and saturate
• Since all inputs are high and greater than 2.4 V,
the base-emitter junctions of Q1 are all reverse
biased.
• When output transistor Q3 saturates (provided
that it has a current path), the output voltage
goes low to 0.2 V.
• This confirms the conditions of a NAND
operation.
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Unit 5: Programmable Logic Devices

Totem Pole
• The output impedance of a gate is normally a resistive plus a capacitive
load.
• The capacitive load consists of the capacitance of the output transistor, the
capacitance of the fan-out gates and any stray wiring capacitance.
• When the output changes from the low to the high state, the output
transistor of the gate goes from saturation to cutoff and the total load
capacitance C charges exponentially from the low to the high voltage level
with a time constant equal to RC
• The TTL gate with the totem-pole output is the same as the open-collector
gate, except for the output transistor Q4 and the diode D1.

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Unit 5: Programmable Logic Devices

Totem pole
• For a typical operating value of C=15 pF
and RL = 4 k ohms, the propagation
delay is 35 ns for TTL open collector.
• By replacing the passive resistor RL,
the propagation delay is reduced to 10
ns.
• This configuration is Totem pole.

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Unit 5: Programmable Logic Devices

Emitter Coupled Logic (ECL)

• This logic family has the lowest
propagation delay - 1 to 2 ns
• Used in very high speed operations
• Noise immunity and power dissipation
are the worst
• Each input is connected to the base of
a transistor. The two voltage levels are
about 0.8 V for the high state and
about 1.8V for the low state.
• The circuit consists of a differential
amplifier, a temperature- and voltage-
compensated bias network, and an
emitter-follower output.
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Unit 5: Programmable Logic Devices

Metal oxide semiconductor

• The field-effect transistor (FET) is a unipolar transistor, since its operation depends on the flow of
only one type of carrier.
• There are two types of FETs: the junction field-effect transistor (JFET) and the metal-oxide
semiconductor (MOS).
• The former is used in linear circuits and the latter in digital circuits. MOS transistors can be
fabricated in less area than bipolar transistors.

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MOS
• The p-channel MOS consists of a lightly doped substrate of n-type silicon material.
• Two regions are heavily doped by diffusion with p-type impurities to form the source and drain.
• The region between the two p-type sections serves as the channel.
• The gate is a metal plate separated from the channel by an insulated dielectric of silicon dioxide.
• A negative voltage (with respect to the substrate) at the gate terminal causes an induced electric
field in the channel that attracts p-type carriers (holes) from the substrate.
• As the magnitude of the negative voltage on the gate increases, the region below the gate
accumulates more positive carriers, the conductivity increases and current can flow from source
to drain, provided that a voltage difference is maintained between these two terminals.

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Unit 5: Programmable Logic Devices

MOS
• MOS can be p-type or n-type (depending on the majority carriers).
• They can operated in enhancement mode or depletion mode depending on the state of the
channel region at zero gate voltage
• The source is the terminal through which the majority carriers enter the device. The drain is the
terminal through which the majority carriers leave the device.
• In a n-channel MOS, the source terminal is connected to the substrate and a positive voltage is
applied to the drain terminal.
• When the gate voltage is below a threshold voltage VT (about 2 V), no current flows in the
channel and the drain-to-source path is like an open circuit.
• When the gate voltage is sufficiently positive above VT, a channel is formed and n-type carriers
flow from source to drain.
• n-type carriers are negative and correspond to a positive current flow from drain to source.
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Unit 5: Programmable Logic Devices

• One advantage of the MOS device is that it can be used not only as a transistor but as a resistor
as well.
• A resistor is obtained from the MOS by permanently biasing the gate terminal for conduction.
The ratio of the source-drain voltage to the channel current then determines the value of the
resistance.
• Different resistor values may be constructed during manufacturing by fixing the channel length
and width of the MOS device.
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Unit 5: Programmable Logic Devices

• For an n-channel MOS, the supply voltage VDD is positive (about 5

V), to allow positive current flow from drain to source. The two
voltage levels are a function of the threshold voltage VT. The low
level is anywhere from zero to VT, and the high level ranges from
VT to VDD. The n-channel gates usually employ positive logic.
• The inverter circuit uses two MOS devices. Q1 acts as the load
resistor and Q2 as the active device. When the input voltage is low
(below VT ), Q2 turns off. Since Q1 is always on, the output voltage
is about VDD. When the input voltage is high (above VT), Q2 turns
on. Current flows from VDD through the load resistor Q1 and into
Q2.
• The NAND gate uses transistors in series. Inputs A and B must
both be high for all transistors to conduct and cause the output to
go low. If either input is low, the corresponding transistor is turned
off and the output is high.
• The NOR gate uses transistors in parallel. If either input is high,
the corresponding transistor conducts and the output is low. If all
inputs are low, all active transistors are off and the output is high.
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Unit 5: Programmable Logic Devices

Complementary MOS
• Complementary MOS (CMOS) circuits take
advantage of the fact that both n-channel and
p-channel devices can be fabricated on the
same substrate.
• CMOS circuits consist of both types of MOS
devices interconnected to form logic
functions.

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Unit 5: Programmable Logic Devices

Complementary MOS
• The basic circuit is the inverter, which consists of one p-channel transistor and one n-
channel transistor. The source terminal of the p-channel device is at VDD and the source
terminal of the n-channel device is at ground.
• The behavior of the MOS transistor:
1. The n-channel MOS conducts when its gate-to-source voltage is positive.
2. The p-channel MOS conducts when its gate-to-source voltage is negative.
3. Either type of device is turned off if its gate-to-source voltage is zero.
• Operation of the inverter: When the input is low, both gates are at zero potential. The input is at - VDD
relative to the source of the p-channel device and at 0 V relative to the source of the a-channel device. The
result is that the p-channel device is turned on and the n-channel device is turned off. Under these
conditions, there is a low-impedance path from VDD to the output and a very high-impedance path from
output to ground. Therefore. the output voltage approaches the high-level VDD under normal loading
conditions.
• When the input is high, both gates are at VDD and the situation is reversed: The p-channel device is off and
the n-channel device is on. The result is that the output approaches the low level of 0 V.

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Unit 5: Programmable Logic Devices

Complementary MOS
• A two-input NAND gate consists of two p-type units
in parallel and two n-type units in series.
• If all inputs are high, both p-channel transistors turn
off and both n-channel transistors turn on. The
output has a low impedance to ground and produces
a low state.
• If any input is low, the associated n -channel
transistor is turned off and the associated p-channel
transistor is turned on. The output is coupled to VDD
and goes to the high state.

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Unit 5: Programmable Logic Devices

Complementary MOS
• A two-input NOR gate consists of two n-type units
in parallel and two p-type units in series.
• When all inputs are low, both n-channel units are on
and both p-channel units are off. The output is
coupled to VDD and goes to the high state.
• If any input is high, the associated p-channel
transistor is turned off and the associated n-channel
transistor turns on, connecting the output to ground
and causing a low-level output.

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Unit 5: Programmable Logic Devices

Complementary MOS
• MOS transistors can be considered to be electronic switches that either conduct or are
open.
• Operating CMOS at a larger power-supply voltage reduces the propagation delay time
and improves the noise margin, but the power dissipation is increased.
• The propagation delay time with VDD = 5 V ranges from 5 to 20 ns depending on the type
of CMOS used. The noise margin is usually about 40 percent of the power supply voltage.
The fan-out of CMOS gates is about 30 when they are operated at a frequency of I MHz.
The fan-out decreases with an increase in the frequency of operation of the gates.
• The CMOS fabrication process is simpler than that of TTL and provides a greater packing
density. Thus more circuits can be placed on a given area of silicon at a reduced cost per
function. This property together with the low power dissipation of CMOS circuits, good
noise immunity, and reasonable propagation delay, makes CMOS the most popular
standard as a digital logic family.
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Unit 5: Programmable Logic Devices

Comparison of Logic families

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Unit 5: Programmable Logic Devices

Comparison of Logic families

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Unit 5: Programmable Logic Devices

Comparison of Logic families

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Unit 5: Programmable Logic Devices

Comparison of Logic families

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Unit 5: Programmable Logic Devices

Combinational PLDs
• Combinational programmable
logic device (PLD) are
integrated circuits with
programmable gates divided
into an AND array and an OR
array to provide an AND–OR
sum‐of‐product
implementation.
• There are three major types of
combinational PLDs, differing in
the placement of the
programmable connections in
the AND–OR array.

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Unit 5: Programmable Logic Devices

Combinational PLDs
• The PROM has a fixed AND array constructed as a decoder and a
programmable OR array.
• The programmable OR gates implement the Boolean functions in
sum‐of‐minterms form.
• The PAL has a programmable AND array and a fixed OR array.
• The AND gates are programmed to provide the product terms for the
Boolean functions, which are logically summed in each OR gate.
• The most flexible PLD is the PLA, in which both the AND and OR arrays can
be programmed. The product terms in the AND array may be shared by any
OR gate to provide the required sum‐of‐products implementation.
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Unit 5: Programmable Logic Devices

Programmable Logic Array (PLA)

• The PLA is similar in concept to the X – Connected line

PROM, except that the PLA does not

provide full decoding of the variables and
does not generate all the minterms.
• The decoder is replaced by an array of
AND gates that can be programmed to
generate any product term of the input
variables. The product terms are then
1 - Complement
connected to OR gates to provide the sum
of products for the required Boolean
functions.
• The internal logic of a PLA with three
inputs and two outputs is shown here.
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Programmable Logic Array (PLA)

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Programmable Logic Array (PLA)

• The fuse map of a PLA can be specified in a tabular form.
• The PLA programming table consists of three sections.
• The first section lists the product terms numerically. The second section specifies the required
paths between inputs and AND gates. The third section specifies the paths between the AND and
OR gates. For each output variable, we may have a T (for true) or C (for complement) for
programming the XOR gate.

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Unit 5: Programmable Logic Devices

Programmable Logic Array (PLA)

• For each product term, the inputs are marked with 1, 0, or — (dash). If a variable in the product
term appears in the form in which it is true, the corresponding input variable is marked with a 1. If
it appears complemented, the corresponding input variable is marked with a 0. If the variable is
absent from the product term, it is marked with a dash.
• The paths between the AND and OR gates are specified under the column head “Outputs.” The
output variables are marked with 1’s for those product terms which are included in the function.
Each product term that has a 1 in the output column requires a path from the output of the AND
gate to the input of the OR gate.
• Finally, a T (true) output dictates that the other input of the corresponding XOR gate be
connected to 0, and a C (complement) specifies a connection to 1.

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Programmable Logic Array (PLA)

• The size of a PLA is specified by the number of inputs, the number of product
terms, and the number of outputs.
• For n inputs, k product terms, and m outputs, the internal logic of the PLA consists
of n buffer–inverter gates, k AND gates, m OR gates, and m XOR gates.
• In designing a digital system with a PLA, all that is needed is the PLA
programming table from which the PLA can be programmed to supply the
required logic.
• In implementing a combinational circuit with a PLA, careful investigation must be
undertaken in order to reduce the number of distinct product terms, since a PLA
has a finite number of AND gates. This can be done by simplifying each Boolean
function to a minimum number of terms.
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Problem: A combinational circuit is defined by the functions: F1=σ 𝑚(3,5,7) and F2=
σ 𝑚(4,5,7). Implement the circuit with a PLA having 3 inputs, 3 product terms and two
outputs.

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Unit 5: Programmable Logic Devices Combination of variables

Programmable Array Logic (PAL)

• The PAL is a programmable
logic device with a
programmable AND array
and a fixed OR array. Output –
Input- Boolean
• Because only the AND gates Variables functions
are programmable, the PAL
is easier to program than,
but is not as flexible as, the
PLA.
• Logic configuration of a Output –
typical PAL with four inputs SOP
and four outputs=>
Three product terms

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Unit 5: Programmable Logic Devices

Programmable Array Logic (PAL)

• Each input has a buffer–inverter gate, and each
output is generated by a fixed OR gate.
• There are four sections in the unit, each
composed of an AND–OR array that is three
wide, the term used to indicate that there are
three programmable AND gates in each section
and one fixed OR gate.
• Each AND gate has 10 programmable input
connections, shown in the diagram by 10 vertical
lines intersecting each horizontal line.
• The horizontal line symbolizes the
multiple‐input configuration of the AND gate.
One of the outputs is connected to a buffer–
inverter gate and then fed back into two inputs
of the AND gates.
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Unit 5: Programmable Logic Devices

Programmable Array Logic (PAL)

• A typical PAL integrated circuit may have eight inputs, eight outputs, and
eight sections, each consisting of an eight‐wide AND–OR array. The output
terminals are sometimes driven by three‐state buffers or inverters.
• In designing with a PAL, the Boolean functions must be simplified to fit into
each section.
• The number of product terms in each section is fixed, and if the number of
terms in the function is too large, it may be necessary to use two sections to
implement one Boolean function.

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Unit 5: Programmable Logic Devices

Programmable Array Logic (PAL)

• As an example of using a PAL in the design of a combinational circuit, consider the following
Boolean functions, given in sum‐of‐minterms form:

• Simplifying the four functions to a minimum number of terms results in the following Boolean
functions:

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Unit 5: Programmable Logic Devices

Programmable Array Logic (PAL)

Each output – max 3 products

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Unit 5: Programmable Logic Devices

Programmable Array Logic (PAL)

• The table is divided into four sections with three product terms in each, to conform with the PAL.
The first two sections need only two product terms to implement the Boolean function. The last
section, for output z, needs four product terms. Using the output from w, we can reduce the
function to three terms.
• The fuse map for the PAL as specified in the programming table.
• For each 1 or 0 in the table, we mark the corresponding intersection in the diagram with the
symbol for an intact fuse. For each dash, we mark the diagram with blown fuses in both the true
and complement inputs. If the AND gate is not used, we leave all its input fuses intact. Since the
corresponding input receives both the true value and the complement of each input variable, we
have AA = 0 and the output of the AND gate is always 0.
• As with all PLDs, the design with PALs is facilitated by using CAD techniques. The blowing of
internal fuses is a hardware procedure done with the help of special electronic instruments.

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Unit 5: Programmable Logic Devices

ROM
• A read‐only memory (ROM) is
essentially a memory device in which
permanent binary information is
stored.
• The binary information must be
specified by the designer and is then
embedded in the unit to form the
required interconnection pattern.
• Once the pattern is established, it stays
within the unit even when power is
turned off and on again.

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Unit 5: Programmable Logic Devices

Types of ROM
• The required paths in a ROM may be programmed in four different ways.
The first is called mask programming and is done by the semiconductor
company during the last fabrication process of the unit.
• The procedure for fabricating a ROM requires that the customer fill out the
truth table he or she wishes the ROM to satisfy.
• The manufacturer makes the corresponding mask for the paths to produce
the 1’s and 0’s according to the customer’s truth table.
• This procedure is costly because the vendor charges the customer a special
fee for custom masking the particular ROM. For this reason, mask
programming is economical only if a large quantity of the same ROM
configuration is to be ordered.

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Unit 5: Programmable Logic Devices

PROM
• For small quantities, it is more economical to use a second type of ROM called programmable
read‐only memory, or PROM.
• When ordered, PROM units contain all the fuses intact, giving all 1’s in the bits of the stored
words.
• The fuses in the PROM are blown by the application of a high‐voltage pulse to the device
through a special pin.
• A blown fuse defines a binary 0 state and an intact fuse gives a binary 1 state
• Special instruments called PROM programmers are available commercially to facilitate the
procedure
• The hardware procedure for programming ROMs or PROMs is irreversible, and once
programmed, the fixed pattern is permanent and cannot be altered.

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Unit 5: Programmable Logic Devices

EPROM (Erasable PROM)

• A third type of ROM is the erasable PROM, or EPROM,
which can be restructured to the initial state even though it
has been programmed previously.
• When the EPROM is placed under a special ultraviolet light
for a given length of time, the short wavelength radiation
discharges the internal floating gates that serve as the
programmed connections.
• After erasure, the EPROM returns to its initial state and can
be reprogrammed to a new set of values.
• EPROMs are generally employed for programs designed for
repeated use but that can be upgraded with a later version
of a program.

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Unit 5: Programmable Logic Devices

EEPROM – Electrically erasable PROM

• The fourth type of ROM is the electrically erasable PROM (EEPROM or
E2PROM ).
• This device is like the EPROM, except that the previously programmed
connections can be erased with an electrical signal instead of ultraviolet
light.
• The advantage is that the device can be erased without removing it from its
socket.

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Unit 5: Programmable Logic Devices

EAPROM
• Electronically Alterable Programmable Read-Only Memory (EAPROM) is
a non-volatile storage device where bytes or words can be erased and
reprogrammed individually during system operation.
• A form of PROM in which the contents of selected memory locations can be
changed by applying suitable electric signals.

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Unit 5: Programmable Logic Devices

Flash memory
• Flash memory devices are similar to EEPROMs, but have additional built‐in
circuitry to selectively program and erase the device in‐circuit, without the
need for a special programmer.
• They have widespread application in modern technology in cell phones,
digital cameras, set‐top boxes, digital TV, telecommunications, nonvolatile
data storage, and microcontrollers.
• Their low consumption of power makes them an attractive storage medium
for laptop and notebook computers.
• It has about 105 block-erase cycles

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Unit 5: Programmable Logic Devices

Implementation of combinational logic/sequential

logic design using standard IC
• Self study
• 4 bit adder and subtractor
• Adder implementation using Decoder

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