A

Laboratory Manual for

VLSI Design
(3151105)

B. E. Electronics and Communication

Semester 5

Directorate of Technical Education, Gandhinagar,

Gujarat
 VGEC, Chandkheda, Ahmedabad
Department of Electronics & Communication Engineering

Certificate

This is to certify that Mr. Patel Fevil Satishkumar

Enrollment No. 210170111046 of B. E. Semester-V Electronics and Communication
Engineering of this Institute (GTU Code: 11) has satisfactorily completed the
Practical / Tutorial work for the subject VLSI Design (3151105) for the academic
year 2023-24.

Place:
Date:

Name and Sign of Faculty member

Head of the Department

VLSI Design (3151105)

Practical – Course Outcome Matrix

Course Outcomes (COs):

1. To understand fabrication and operation of MOSFET device.
2. To obtain and verify the mathematical model of MOSFET device.
3. Analyze and design Static and Dynamic CMOS Circuits.
4. To understand techniques of DFT.
5. To write programs in Verilog/VHDL for combinational and sequential
circuits and realize them on FPGA.
Sr. CO C CO CO CO
Objective(s) of Experiment
No. 1 O2 3 4 5
1. Introduction to FPGA and CPLD. √
Introduction to Hardware Description Languages
2. √
(HDLs).
3. Introduction to Xilinx / Altera (Intel) Tools. √
Implement all the basic Logic Gates and Boolean
functions using different modeling styles in Verilog/
4. VHDL: √ √
a. Structural modeling
b. Dataflow modeling
c. Behavioural modeling
Design Adder & Subtractor using Verilog / VHDL.
a. Half Adder (structural and dataflow modeling)
5. b. Full Adder using Half Adder (structural modeling) √ √
c. Full Adder (dataflow and behavioural modeling)
d. Half Subtractor
e. Full Subtractor
Design Binary-to-Gray & Gray-to-Binary encoder using
6. √ √
Verilog/VHDL
Design Multiplexer and Demultiplexer using Verilog/
VHDL.
a. 2:1 Mux (dataflow and behavioural modeling)
7. b. 4:1 Mux (structural and dataflow modeling) √ √
c. 8:1 Mux (using 4:1 and 2:1 Mux: structural modeling)
d. 16:1 Mux (using behavioural modeling & 4:1 Mux:
structural modeling)
e. 1:8 Demux
8. Design 2:4, 3:8, 4:16 Decoders using Verilog/VHDL √ √
9. Design 4*2, 8*3 Priority Encoder using Verilog / VHDL. √ √
10. Design 4-bit Comparator using Verilog / VHDL. √ √
Design BCD and Ripple Carry Adder using Verilog /
11. √ √
VHDL.
Design of S-R and D latches using structural / behavioral
12. √ √
modeling usingVerilog/VHDL.
Design positive edge triggered D-FF with asynchronous
13. √ √
/synchronous active high reset using Verilog / VHDL.
VLSI Design (3151105)

Design serial in serial out and serial in parallel out shift

14. √ √
registers using Verilog/VHDL.
Design Counter using Verilog/VHDL.
15. a. BCD Counter. √ √
b. Up-Down Counter
16. Introduction to Microwind tool. √ √
Implementation of Resistive load and CMOS inverters
17.
using Microwind. √ √

Implementation of CMOS NAND and NOR gate using

18. √ √
Microwind.
VLSI Design (3151105)

Index
(Progressive Assessment Sheet)

Date of Date of Assessme Sign. of

Sr. Page Remar
No.
Title of Experiment perform submiss nt Teacher
No. ks
ance ion Marks with date
1 Introduction to FPGA and CPLD.

2 Introduction to Hardware Description

Languages (HDLs).
3 Introduction to Xilinx / Altera (Intel) Tools.
4 Implement all the basic Logic Gates and
Boolean functions using different modeling
styles in Verilog/ VHDL:
a. Structural modeling
b. Dataflow modeling
c. Behavioural modeling
5 Design Adder & Subtractor using Verilog /
VHDL.
a. Half Adder (structural and dataflow
modeling)
b. Full Adder using Half Adder (structural
modeling)
c. Full Adder (dataflow and behavioural
modeling)
d. Half Subtractor
e. Full Subtractor
6 Design Binary-to-Gray & Gray-to-Binary
encoder using Verilog/VHDL
7 Design Multiplexer and Demultiplexer using
Verilog/ VHDL.
f. 2:1 Mux (dataflow and behavioural
modeling)
g. 4:1 Mux (structural and dataflow modeling)
h. 8:1 Mux (using 4:1 and 2:1 Mux: structural
modeling)
i. 16:1 Mux (using behavioural modeling &
4:1 Mux: structural modeling)
1:8 Demux
8 Design 2:4, 3:8, 4:16 Decoders using
Verilog/VHDL
9 Design 4*2, 8*3 Priority Encoder using Verilog
/ VHDL.
10 Design 4-bit Comparator using Verilog /
VHDL.
11 Design BCD and Ripple Carry Adder using
Verilog / VHDL.
12 Design of S-R and D latches using structural /
behavioral modeling usingVerilog/VHDL.
VLSI Design (3151105)

13 Design positive edge triggered D-FF with

asynchronous /synchronous active high reset
using Verilog / VHDL.
14 Design serial in serial out and serial in parallel
out shift registers using Verilog/VHDL.
15 Design Counter using Verilog/VHDL.
a. BCD Counter.
b. Up-Down Counter
16 Introduction to Microwind tool.
17 Implementation of Resistive load and CMOS
inverters using Microwind.
18 Implementation of CMOS NAND and NOR
gate using Microwind.
Total
 Experiment No: 1

Date:

Aim: Introduction to FPGA & CPLD.

Competency and Practical Skills:

Relevant CO:

Objectives:

Equipment / Instruments: Laptop or Computer with Xilinx / Altera (Intel) Tools.

Basic Theory:

What is an FPGA?

Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based around a
matrix of configurable logic blocks (CLBs) connected via programmable interconnects. FPGAs can
be reprogrammed to desired application or functionality requirements after manufacturing. This
feature distinguishes FPGAs from Application Specific Integrated Circuits (ASICs), which are
custom manufactured for specific design tasks. Although one-time programmable (OTP) FPGAs
are available, the dominant types are SRAM based which can be reprogrammed as the design
evolves.

What are the differences between an ASIC and an FPGA?

FPGA Architecture:

A basic FPGA architecture shown below consists of thousands of fundamental elements called
configurable logic blocks (CLBs) surrounded by a system of programmable interconnects, called a
fabric, that routes signals between CLBs. Input/output (I/O) blocks interface between the FPGA
and external devices. Depending on the manufacturer, the CLB may also be referred to as a logic
block (LB), a logic element (LE) or a logic cell (LC).
 Fig 1.1 General Architecture of FPGA

Explain the structure of Switch matrix:

Fig 1.2 Simplified Block Diagram of XC4000-Families CLB

The XC4000 families achieve high speed through advanced semiconductor technology and through
improved architecture, and supports system clock rates of up to 50 MHz. Compared to older Xilinx
FPGA families, the XC4000 families are more powerful, offering on-chip RAM and wide-input
decoders. They are more versatile in their applications, and design cycles are faster due to a
combination of increased routing resources and more sophisticated software. And last, but not least,
they more than double the available complexity, up to the 20,000-gate level. The XC4000 families
have 16 members, ranging in complexity from 2,000 to 25,000 gates.

The CLBs provide the functional elements for constructing the user’s logic. The most important
one is a more powerful and flexible CLB surrounded by a versatile set of routing resources, resulting
in more “effective gates per CLB.” The principal CLB elements are shown in Figure 1.2. Each new
CLB also packs a pair of flip-flops and two independent 4-input function generators. The two
function generators offer designers plenty of flexibility because most combinatorial logic functions
need less than four inputs. Consequently, the design-software tools can deal with each function
generator independently, thus improving cell usage.

FPGA Applications:
• Aerospace & Defense - Radiation-tolerant FPGAs along with intellectual property for
image processing, waveform generation, and partial reconfiguration for SDRs.
• ASIC Prototyping - ASIC prototyping with FPGAs enables fast and accurate SoC system
modeling and verification of embedded software
• Automotive - Automotive silicon and IP solutions for gateway and driver assistance
systems, comfort, convenience, and in-vehicle infotainment. - Learn how AMD FPGA's
enable Automotive Systems
• Broadcast & Pro AV - Adapt to changing requirements faster and lengthen product life
cycles with Broadcast Targeted Design Platforms and solutions for high-end professional
broadcast systems.
• Consumer Electronics - Cost-effective solutions enabling next generation, full-featured
consumer applications, such as converged handsets, digital flat panel displays, information
appliances, home networking, and residential set top boxes.
• Data Center - Designed for high-bandwidth, low-latency servers, networking, and storage
applications to bring higher value into cloud deployments.
• High Performance Computing and Data Storage - Solutions for Network Attached
Storage (NAS), Storage Area Network (SAN), servers, and storage appliances.
• Industrial - AMD FPGAs and targeted design platforms for Industrial, Scientific and
Medical (ISM) enable higher degrees of flexibility, faster time-to-market, and lower overall
non-recurring engineering costs (NRE) for a wide range of applications such as industrial
imaging and surveillance, industrial automation, and medical imaging equipment.
• Medical - For diagnostic, monitoring, and therapy applications, the Virtex FPGA and
Spartan™ FPGA families can be used to meet a range of processing, display, and I/O
interface requirements.
• Video & Image Processing - FPGAs and targeted design platforms enable higher degrees
of flexibility, faster time-to-market, and lower overall non-recurring engineering costs
(NRE) for a wide range of video and imaging applications.
• Wired Communications - End-to-end solutions for the Reprogrammable Networking
Linecard Packet Processing, Framer/MAC, serial backplanes, and more
• Wireless Communications - RF, base band, connectivity, transport and networking
solutions for wireless equipment, addressing standards such as WCDMA, HSDPA, WiMAX
and others.

CPLD

A Complex Programmable Logic Device (CPLD) is a combination of a fully programmable

AND/OR array and a bank of microcells. The AND/OR array is reprogrammable and can perform
a multitude of logic functions. Microcells are functional blocks that perform combinatorial or
sequential logic, and also have the added flexibility for true or complement, along with varied
feedback paths.

Traditionally, CPLDs have used analog sense amplifiers to boost the performance of their
architectures. This performance boost came at the cost of very high current requirements.
Advantages of CPLD:
CPLDs perform a variety of useful functions in systems design due to their unique
capabilities and as the market leader in programmable logic solutions, AMD provides a total
solution to a designer's CPLD needs. Understanding the features and benefits of using CPLDs can
help enable ease of design, lower development costs, and speed products to market.

Comparison of CPLD and FPGA

Sr.
FPGA CPLD
No

Conclusion:
Suggested Reference:

https: www.xilinx.com/products/silicon-devices/fpga/what-is-an-fpga.html
https://www.xilinx.com/products/silicon-devices/cpld/cpld.html
https://media.digikey.com/pdf/data%20sheets/xilinx%20pdfs/xc4000,a,h.pdf

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 Experiment No: 2

Date:

Aim: Introduction to Hardware Description Languages (HDLs).

Competency and Practical Skills:

Relevant CO:

Objectives:

Equipment / Instruments: Laptop or Computer with Xilinx / Altera (Intel) Tools.

Basic Theory:

What Are Hardware Description Languages (HDLs)?

HDLs are indeed similar to programming languages but not exactly the same. We utilize a
programming language to build or create software, whereas we use a hardware description language
to describe or express the behavioral characteristics of digital logic circuits.

We utilize HDLs for designing processors, motherboards, CPUs (i.e., computer chips), as well as
various other digital circuitry.

What Is VHDL?

Very High-Speed Integrated Circuit Hardware Description Language (VHDL) is a description

language used to describe hardware. It is utilized in electronic design automation to express mixed-
signal and digital systems, such as ICs (integrated circuits) and FPGA (field-programmable gate
arrays). We can also use VHDL as a general-purpose parallel programming language.
We utilize VHDL to write text models that describe or express logic circuits. If the text model is
part of the logic design, the model is processed by a synthesis program. The next step in the process
incorporates a simulation program to test the logic design. During this step, we utilize the simulation
models to characterize the logic circuits that interface to the design. We refer to this collection of
simulation models as a testbench.
Typically, a VHDL simulator is an event-driven simulator which means that we add each
transaction to an event queue for a particular scheduled time. For example, if a signal assignment
occurs after one nanosecond, we add the event to the queue as time + 1 ns. Although a zero delay
is allowed, it still must be scheduled, and for these scenarios we utilize a Delta delay.

VHDL Functionality

These simulations alternate between two modes:

• Statement Execution: In this mode, the triggered statements are evaluated.

• Event Processing: During this mode, the events in the queue are processed.

Though there is an inherent similarity in hardware designs, VHDL has processes that can make the
necessary accommodations. However, these processes differ in syntax from the parallel processes
in tasks (Ada).
Similarly to Ada, VHDL is a predefined part of the programming language, plus, it is not case
sensitive. However, VHDL provides various features that are unavailable in Ada, e.g., an extensive
set of Boolean operators which include nor and nand. These additional features enable VHDL to
precisely represent operations that are customary in hardware.

Another feature of VHDL is it has file output and input capabilities that you can utilize as a general-
purpose language for text processing. Although, we typically see them in use by a simulation
testbench for data verification or stimulus. Specific VHDL compilers build executable binaries,
which afford the option to use VHDL to write a testbench for functionality verification designs
utilizing files on the host computer to compare expected results, user interaction, and define stimuli.

Note: Ada is a statically typed, structured, object-oriented, and imperative high-level programming
language; it is an extension that derives from Pascal and other programming languages.

What Is Verilog?

As I am sure you are aware, Verilog is also a Hardware Description Language. It employs a textual
format to describe electronic systems and circuits. In the area of electronic design, we apply Verilog
for verification via simulation for testability analysis, fault grading, logic synthesis, and timing
analysis.

Verilog is also more compact since the language is more of an actual hardware modeling language.
As a result, you typically write fewer lines of code, and it elicits a comparison to the C language.
However, Verilog has a superior grasp on hardware modeling as well as a lower level of
programming constructs. Verilog is not as wordy as VHDL, which accounts for its compact nature.
Although VHDL and Verilog are similar, their differences tend to outweigh their similarities.

Verilog HDL is an IEEE standard (IEEE 1364). It received its first publication in 1995, with a
subsequent revision in 2001. SystemVerilog, which is the 2005 revision of Verilog, is the latest
publication of the standard. We call the IEEE Verilog standard document the LRM (Language
Reference Manual). Currently, the IEEE 1364 standard defines the PLI (Programming Language
Interface).

Note: The PLI is a collective of software routines that allows a bidirectional interface between other
languages such as C and Verilog.

VHDL vs Verilog

Sr.
VHDL Verilog
No.
1 Strongly typed Weakly typed
2 Easier to understand Less code to write
3 More natural in use More of a hardware modeling language
4 Non-C-like syntax Similarities to the C language
Variables must be described by data A lower level of programming
5
type constructs
6 Widely used for FPGAs and military A better grasp on hardware modeling
7 More difficult to learn Simpler to learn
The most important thing to remember when you are writing HDL code is that you are describing
real hardware, not writing a computer program. The most common beginner’s mistake is to write
HDL code without thinking about the hardware you intend to produce. If you don’t know what
hardware you are implying, you are almost certain not going to get what you want. Instead, begin
by sketching a block diagram of your system, identifying which portions are combinational logic,
which portions are sequential circuits or finite state machines, and so forth. Then, write HDL code
for each portion, using the correct idioms to imply the kind of hardware you need.

Conclusion:

Suggested Reference:

https://resources.pcb.cadence.com/blog/2020-hardware-description-languages-vhdl-vs-verilog-
and-their-functional-uses
https://www.sciencedirect.com/topics/computer-science/hardware-description-languages

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 Experiment No: 3

Date:

Aim: Introduction to Xilinx / Altera (Intel) Tools.

Competency and Practical Skills:

Relevant CO:

Objectives:

Equipment / Instruments: Laptop or Computer with Xilinx / Altera (Intel) Tools.

Basic:

The Xilinx ISE software controls all aspects of the design flow. Through the Project Navigator
interface, one can access all of the design entry and design implementation tools. One can also
access the files and documents associated with their project.

Fig. 2.1 Project Navigator

The Project Navigator interface is divided into four panel sub-windows, as seen in Figure 2.1.

• On the top left are the Start, Design, Files, and Libraries panels, which include display and
access to the source files in the project as well as access to running processes for the
currently selected source. The Start panel provides quick access to opening projects as well
as frequently access reference material, documentation and tutorials.

• At the bottom of the Project Navigator are the Console, Errors, and Warnings panels, which
display status messages, errors, and warnings.
• To the right is a multi-document interface (MDI) window referred to as the Workspace. The
Workspace enables person to view design reports, text files, schematics, and simulation
waveforms.

• Each window can be resized, undocked from Project Navigator, moved to a new location
within the main Project Navigator window, tiled, layered, or closed.

• One can use the View > Panels menu commands to open or close panels. You can use the
Layout > Load Default Layout to restore the default window layout.

• The Design panel provides access to the View, Hierarchy, and Processes panes.

• The View pane radio buttons enable you to view the source modules associated with the
Implementation or Simulation Design View in the Hierarchy pane. If you select Simulation,
you must select a simulation phase from the drop-down list.

• The Hierarchy pane displays the project name, the target device, user documents, and design
source files associated with the selected Design View.

• The View pane at the top of the Design panel allows you to view only those source files
associated with the selected Design View, such as Implementation or Simulation.

• Each file in the Hierarchy pane has an associated icon. The icon indicates the file type (HDL
file, schematic, core, or text file, for example).

• For a complete list of possible source types and their associated icons, see the “Source File
Types” topic in the ISE Help.

• From Project Navigator, select Help > Help Topics to view the ISE Help. If a file contains
lower levels of hierarchy, the icon has a plus symbol (+) to the left of the name. One can
expand the hierarchy by clicking the plus symbol (+). One can open a file for editing by
double-clicking on the filename.

• The Console provides all standard output from processes run from Project Navigator. It
displays errors, warnings, and information messages.

• The Workspace is where design editors, viewers, and analysis tools open. These include ISE
Text Editor, Schematic Editor, Constraint Editor, Design Summary/Report Viewer, RTL
and Technology Viewers, and Timing Analyzer.

• Other tools such as the PlanAhead™ software for I/O planning and floorplanning, ISim,
third-party text editors, XPower Analyzer, and iMPACT open in separate windows outside
the main Project Navigator environment when invoked.

• The Design Summary provides a summary of key design data as well as access to all of the
messages and detailed reports from the synthesis and implementation tools.

• The summary lists high-level information about your project, including overview
information, a device utilization summary, performance data gathered from the Place and
Route (PAR) report, constraints information, and summary information from all reports with
links to the individual reports.
Students need to simulate one sample program code on Xilinx/Altera (Intel) Tools and write
all the steps with snapshot for simulation.

• Students can use below reference for understanding step by step simulation flow.

• https://www.xilinx.com/htmldocs/xilinx13_3/ise_tutorial_ug695.pdf

Conclusion:

Suggested Reference:

https://www.xilinx.com/htmldocs/xilinx13_3/ise_tutorial_ug695.pdf

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 Experiment No: 4

Date: __________________

Aim: Implement all the basic Logic Gates and Boolean functions using different modeling
styles in Verilog/ VHDL:
(a) Structural modeling
(b) Dataflow modeling
(c) Behavioural modeling

Competency and Practical Skills: Basic Digital Design

Relevant CO: CO5

Objectives: Understanding of different modeling styles in Verilog HDL.

Equipment / Instruments: Laptop or Computer with Xilinx / Altera (Intel) Tools.

Basic Theory:

Part – 1 Logic Gate Implementation

Logic Gate Truth Table

Inverter
A X
A X 0 1
1 0

OR Gate
A B Y
0 0 0
A 0 1 1
Y
B 1 0 1
1 1 1

AND Gate (Student Exercise)

NAND Gate

NOR Gate
XOR Gate

XNOR Gate

RTL Codes:

(a) Structural Modeling

module gate_demo(A, B, X, Y);
input A, B;
output X,Y;
not N1(X, A); // NOT gate
or OR1(Y, A, B); // OR gate
endmodule
(b) Dataflow Modeling
module gate_demo(A, B, X, Y);
input A, B;
output X,Y;
assign #5 X = ~A; // NOT gate
assign #2 Y = A | B; // OR gate
endmodule
(c) Behavioural Modeling
module gate_demo(A, B, X, Y);
input A, B;
output reg X,Y;

always @(A,B)
begin
X = ~A; // NOT gate
Y = A | B; // OR gate
end
endmodule
 Test Bench:

module gate_tb;
reg A, B; // Inputs
wire X,Y; // Outputs

// Instantiate the Unit Under Test (UUT)

gate_demo uut (.A(A), .B(B), .X(X), .Y(Y));
initial
begin
A = 0; B = 0; // Initialize Inputs
// Now add stimulus
#10; //add delay of 10 units of timescale
A = 0; B = 1; //change the inputs
#10 A = 1; B = 0;
#10 A = 1; B = 1;
#10 A = 0; B = 0;
#10 $finish;
end
endmodule

Simulation waveforms:

(a) Structural Modeling and (c) Behavioural Modeling

(b) Dataflow Modeling

 AND GATE

• STRUCTURAL MODELLING
module and_gate(A, B, X, Y);
input A, B;
output X,Y;
and a1(Y, A, B);
endmodule

• DATAFLOW MODELLING
module and_gate(A, B, Y);
input A, B;
output Y;
assign Y = A&B;
endmodule

• BEHAVIOURAL MODELLING
module and_gate(A, B, Y);
input A, B;
output reg Y;
always @(A,B)
begin
Y = A & B;
end
endmodule

• TESTBENCH
module gate_tb;
reg A, B;
wire Y;
and_gate uut (.A(A), .B(B), .Y(Y));
initial
begin
A = 0; B = 0;
#10;
A = 0; B = 1;
#10 A = 1; B = 0;
#10 A = 1; B = 1;
#10 A = 0; B = 0;
#10 $finish;
end
endmodule
 NAND GATE

• Structure modeling
module NAND(A,B,C);
input A,B;
output C;
nand X1(C,A,B);
endmodule

• Dataflow modeling
module NAND1(a,b,d);
input a,b;
output d;
wire c;
assign c=a&b;
assign d=~c;
endmodule

• Behavioural modeling
module nandX1(A, B, Y);
input A, B;
output reg Y;
always @(A,B)
begin
Y=~(A&B);
end
endmodule

• TESTBENCH
module gate_tb;
reg A, B;
wire Y;
OR_NOT_gate uut (.A(A), .B(B), .Y(Y));
initial
begin
A = 0; B = 0;
#10;
A = 0; B = 1;
#10 A = 1; B = 0;
#10 A = 1; B = 1;
#10 A = 0; B = 0;
#10 $finish;
end
endmodule
 NOR GATE

• Structural modeling
module NOR(A,B,C);
input A,B;
output C;
nor X1(C,A,B);
endmodule

• Dataflow modeling
module NOR1(a,b,d);
input a,b;
output d;
wire c;
assign c=a|b;
assign d=~c;
endmodule

nor behavioural
module norX1(A, B, Y);
input A, B;
output reg Y;

always @(A,B)
begin
Y=~(A|B);
end
endmodule

• TESTBENCH
module gate_tb;
reg A, B;
wire Y;
OR_NOT_gate uut (.A(A), .B(B), .Y(Y));
initial
begin
A = 0; B = 0;
#10;
A = 0; B = 1;
#10 A = 1; B = 0;
#10 A = 1; B = 1;
#10 A = 0; B = 0;
#10 $finish;
end
endmodule
 XOR GATE

• Structural modelling
module xorX1(A,B,C);
input A,B;
output C;
xor X1(C,A,B);
endmodule

• Dataflow modelling
module xorX1(c,a,b);
input a,b;
output c;
assign c=(a^b);
endmodule

• behavioural modelling
module xorX1(A, B, Y);
input A, B;
output reg Y;
always @(A,B)
begin
Y = A ^ B;
end
endmodule

• TESTBENCH
module gate_tb;
reg A, B;
wire Y;
xorX1_gate uut (.A(A), .B(B), .Y(Y));
initial
begin
A = 0; B = 0;
#10;
A = 0; B = 1;
#10 A = 1; B = 0;
#10 A = 1; B = 1;
#10 A = 0; B = 0;
#10 $finish;
end
endmodule
 XNOR GATE

• Structural modeling
module XNOR(A,B,C);
input A,B;
output C;
xnor X1(C,A,B);
endmodule

• Dataflow modeling
module XNOR(c,a,b);
input a,b;
output c;
assign c=(a~^b);
endmodule

• Behavioural modeling
module xnorX1(A, B, Y);
input A, B;
output reg Y;
always @(A,B)
begin
Y = A~^ B;
end
endmodule

• TESTBENCH
module gate_tb;
reg A, B;
wire Y;
OR_NOT_gate uut (.A(A), .B(B), .Y(Y));
initial
begin
A = 0; B = 0;
#10;
A = 0; B = 1;
#10 A = 1; B = 0;
#10 A = 1; B = 1;
#10 A = 0; B = 0;
#10 $finish;
end
endmodule
 Part – 2 Boolean Function Implementation

1. 𝒇 = 𝒙′ 𝒚′ + 𝒙𝒚
2. 𝒈 = 𝒙′ 𝒚𝒛 + 𝒙𝒚𝒛′ + 𝒙′ 𝒚′ 𝒛′ + 𝒙𝒚𝒛

RTL Code:
(a) Structural Modeling
module boolean_fun(x, y, z, f, g);
input x, y, z;
output f, g;
wire a,b,c,d,e; //internal signal definitions
wire p,q,r,s; //internal signal definitions

not (a, x); // 𝑎 = 𝑥 ′

not (b, y); // 𝑏 = 𝑦 ′
not (c, z); // 𝑐 = 𝑧 ′

and (d, a, b); // 𝑑 = 𝑥 ′ 𝑦′

and (e, x, y); // 𝑒 = 𝑥𝑦
or (f, d, e); // 𝑓 = 𝑥 ′ 𝑦 ′ + 𝑥𝑦

and (p, a, y, z); // 𝑝 = 𝑥 ′ 𝑦𝑧

and (q, x, y, c); // 𝑞 = 𝑥𝑦𝑧′
and (r, a, b, c); // 𝑟 = 𝑥 ′ 𝑦′𝑧′
and (s, x, y, z); // 𝑠 = 𝑥𝑦𝑧
or (g,p,q,r,s); //𝑔 = 𝑥 ′ 𝑦𝑧 + 𝑥𝑦𝑧 ′ + 𝑥 ′ 𝑦 ′ 𝑧 ′ + 𝑥𝑦𝑧

endmodule
(b) Dataflow Modeling
module boolean_fun(x, y, z, f, g);
input x, y, z;
output f, g;
assign f = (~x & ~y) | (x & y); // 𝑓 = 𝑥 ′ 𝑦 ′ + 𝑥𝑦
assign g = (~x & y & z) | (x & y & ~z) | (~x & ~y & ~z) | (x & y & z);
//𝑔 = 𝑥 ′ 𝑦𝑧 + 𝑥𝑦𝑧 ′ + 𝑥 ′ 𝑦 ′ 𝑧 ′ + 𝑥𝑦𝑧
endmodule
(c) Behavioural Modeling
module boolean_fun(x, y, z, f, g);
input x, y, z;
output f, g;

always @(x, y, z)
begin
f = (~x & ~y) | (x & y); // 𝑓 = 𝑥 ′ 𝑦 ′ + 𝑥𝑦
g = (~x & y & z) | (x & y & ~z) | (~x & ~y & ~z) | (x & y & z);
//𝑔 = 𝑥 ′ 𝑦𝑧 + 𝑥𝑦𝑧 ′ + 𝑥 ′ 𝑦 ′ 𝑧 ′ + 𝑥𝑦𝑧
end
endmodule
Simulation waveforms:

(a) Structural Modeling (b) Dataflow Modeling (c) Behavioural Modeling

Conclusion:

Suggested Reference: ---

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 Experiment No: 5
Date: __________________

Aim: Design Adder & Subtractor using Verilog / VHDL.

(a) Half Adder (Using structural and dataflow modeling)
(b) Full Adder using Half Adder (Structure Method).
(c) Full Adder (Using dataflow and behavioural modeling)
(d) Half Subtractor
(e) Full Subtractor

Competency and Practical Skills: Basic Digital Design

Relevant CO: CO5

Objectives: Designing of adders and subtractor using different modeling styles in Verilog HDL.

Equipment / Instruments: Laptop or Computer with Xilinx / Altera (Intel) Tools.

Basic Theory:

Logic Gate Truth Table

Half Adder A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Full Adder
A A B Cin Sum Cout
B Sum 0 0 0 0 0
Cin 0 0 1 1 0
0 1 0 1 0
T1 0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
T2
Cout 1 1 0 0 1
1 1 1 1 1

T3

Half Subtractor (Student Exercise) A B D Br

0 0
0 1
1 0
1 1
Full Subtractor
A B Cin Diff Bout
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

RTL Code:

(a) Half Adder (Structural modeling): S=A⊕B

C = AB

module HA (A, B, S, C); // HA - Half Adder

input A, B;
output S, C; // S- Sum , C - Carry
xor x1(S, A, B); // sum = A xor B
and n1(C, A, B); // carry = A and B
endmodule

Half Adder (Dataflow modeling):

module HA (A, B, S, C); // HA - Half Adder
input A, B;
output S, C; // S- Sum , C - Carry
assign S = A ^ B; // sum = A xor B
assign C =A & B; // carry = A and B
endmodule

(b) 1-bit Full Adder Implementation using Half Adders (structural modeling):

S1
A A S A S Sum
HA1 HA2
B B C B C

Cin
C2
Cout
C1

//Half Adder Module

module HA (A, B, S, C); // HA - Half Adder
input A, B;
output S, C; // S- Sum , C - Carry
xor x1(S, A, B); // sum = A xor B
and n1(C, A, B); // carry = A and B
endmodule
 //Full Adder Module
module FA_1Bit( A, B, Cin, Sum, Cout);
input A, B, Cin;
output Sum, Cout;
wire S1, C1, C2;
// Module instantiation
HA HA1 (A, B, S1, C1);
HA HA2 (S1, Cin, Sum, C2);
OR OR1 (Cout, C1, C2);
endmodule

RTL Schematic of 1-bit FA Implementation:

(c) 1-bit Full Adder (Dataflow and behavioural modeling):

Sum = A ⊕ B ⊕ Cin
Cout = AB + BCin + ACin

Full Adder (Dataflow modeling):

module FA_1_Bit_DF(A,B,Cin,Sum,Cout);
input A,B,Cin;
output Sum,Cout;
assign {Cout,Sum} = A + B + Cin;
endmodule

Full Adder (Behavioural modeling):

module FA_1_Bit_BH(A,B,Cin,Sum,Cout);
input A,B,Cin;
output reg Sum,Cout;
always @( A,B,Cin)
begin
{Cout,Sum} = A + B + Cin;
end
endmodule
Simulation waveforms:

1-Bit Full adder

(d) Half Subtractor (Exercise for Students):

(e) Full Subtractor (Exercise for Students):

Conclusion:

Suggested Reference:

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 Half Subtractor
• Dataflow modeling
module half_subtractor(a,b,difference,borrow);
input a,b;
output difference,borrow;
assign difference = a^b;
assign borrow = ~a&b;
endmodule

• Test Bench:
module tb_half_subtractor();
reg t_a, t_b;
wire difference, borrow;
half_subtractor dut(.a(t_a), .b(t_b), .difference(difference),
.borrow(borrow));

initial
begin
$monitor("A=%b | B=%b | Difference=%b |
Borrow=%b",t_a,t_b,difference,borrow);

t_a=0; t_b=0;
#10;
t_a=0; t_b=1;
#10;
t_a=1; t_b=0;
#10;
t_a=1; t_b=1;
#10;
$finish;
end
endmodule
 Full Subtractor

• Dataflow modeling
module full_subtractor(a,b,bin,difference,borrow);
input a,b,bin;
output difference,borrow;
assign difference = a^b^bin;
assign borrow = ~a&b | b&bin | ~a&bin;
endmodule

• Test Bench
module tb_full_subtractor();
reg a,b,bin;
wire difference,borrow;
full_subtractordut(.a(a),.b(b),.bin(bin),.difference(difference),.borrow(borr
ow));

initial
begin

$monitor("A=%d | B=%d | Cin=%d | Difference=%d |

Borrow=%d",a,b,bin,difference,borrow);

#0; a=0; b=0; bin=0;

#5; a=1'b1; b=1'b0; bin=1'b0;
#5; a=1'b0; b=1'b1; bin=1'b1;
#5; a=1'b0; b=1'b1; bin=1'b0;
#5;
$finish;
end
endmodule
 Experiment No: 6

Date: __________________

Aim: Design Binary to Gray & Gray to Binary encoder using Verilog/VHDL.

Competency and Practical Skills: Basic Digital Design

Relevant CO: CO5

Objectives: Designing of code converters

Equipment / Instruments: Laptop or Computer with Xilinx / Altera (Intel) Tools.

Basic Theory:

Decimal Binary Code Gray code

Equivalent
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0

Binary to Gray Converter Gray to Binary Converter

Student Exrcise
B3 G3

G2
B2

G1
B1

G0
B0
RTL Code:
module bin_to_gray(B, G);
input [3:0] B;
output [3:0] G;
assign G[3] = B[3];
assign G[2] = B[3] ^ B[2];
assign G[1] = B[2] ^ B[1];
assign G[0] = B[1] ^ B[0];
endmodule

RTL Schematic:

Simulation waveforms:
Gray to Binary Encoder (Exercise for Students):

Conclusion:

Suggested Reference:

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 Gray to Binary Encoder

• Dataflow modeling
module BG( input [3:0] g, output [3:0] b);
assign b[0]=b[1]^g[0];
assign b[1]=b[2]^g[1];
assign b[2]=b[3]^g[2];
assign b[3]=g[3];
endmodule

• Test Bench
module graytobinary_tb();
reg [3:0]g;
wire [3:0]b;
BG uut (g,b);
Initial
begin
g=4'b0000;
#10 g=4'b0001;
#10 g=4'b0010;
#10 g=4'b0011;
#10 g=4'b0100;
#10 g=4'b0101;
#10 g=4'b0110;
#10 g=4'b0111;
#10 g=4'b1000;
#10 g=4'b1001;
#10 g=4'b1010;
#10 g=4'b1011;
#10 g=4'b1100;
#10 g=4'b1101;
#10 g=4'b1110;
#10 g=4'b1111;
end
endmodule
 Experiment No: 7

Date: __________________

Aim: Design Multiplexer and Demultiplexer using Verilog / VHDL.

a. 2:1 Mux (Dataflow and Behavioural modeling)
b. 4:1 Mux (Structural and Dataflow modeling)
c. 8:1 Mux (Using 4:1 and 2:1 Mux : Structural modeling)
d. 16:1 Mux (Using Behavioural Modeling & 4:1 Mux : Structural modeling)
e. 1:8 Demux

Competency and Practical Skills: Basic Digital Design

Relevant CO: CO5

Objectives: Designing of Multiplexers and Demultiplexers

Equipment / Instruments: Laptop or Computer with Xilinx / Altera (Intel) Tools.

Basic Theory:

MUX:
A digital logic circuit which is capable of accepting several inputs and generating a single
output is known as multiplexer or MUX.

(a) 2:1 Mux (Dataflow and Behavioural modeling)

S

I1 Y = S I1 + S I0
2:1
MUX
Y I1 T1
I0
Y
S I0
T0

RTL Code (Dataflow Modeling):

module mux2_to_1(I, S, Y);

input [1 : 0] I;
input S;
output Y;
assign Y = S ? I[1] : I[0]; // Data flow modeling
endmodule

RTL Code (Behavioural Modeling):

module mux2_to_1(I, S, Y);

input [1 : 0] I;
input S;
output reg Y;
 always @(I, S)
begin
if (S == 0)
Y <= I[0];
else
Y <= I[1];
endmodule

Test Bench:

`timescale 1ns / 1ps

module tb_mux2to1;
reg [1:0] I; // Inputs
reg S;
wire Y; // Outputs

// Instantiate the Unit Under Test (UUT)

mux2to1 uut (.I(I), .S(S), .Y(Y));
initial
begin
// Initialize Inputs
I[0] = 0; I[1] = 0; S = 0;
// Add stimulus here
#10 I[0] = 0; I[1] = 1; S = 0;
#10 I[0] = 1; I[1] = 1; S = 0;
#10 I[0] = 0; I[1] = 0; S = 1;
#10 I[0] = 0; I[1] = 1; S = 1;
#10 $finish;
end

endmodule

Simulation Waveforms:
(b) 4:1 Mux (Structural and Dataflow modeling)

(4 : 1 MUX using 2 : 1 MUX)

RTL Code (structural modeling):

// 2-to-1 MUX module
module mux2_to_1(I, S, Y);
input [1 : 0] I;
input S;
output Y;
assign Y = S ? I[1] : I[0]; // Data flow modeling
endmodule

// 4-to-1 MUX module

module mux4_to_1(I, S, Y);
input [3 : 0] I;
input [1: 0] S;
output Y;
wire [1: 0] t;
mux2_to_1 mux1(I[1:0], S[0], t[0]);
mux2_to_1 mux1(I[3:2], S[0], t[1]);
mux2_to_1 mux1(t, S[1], Y);
endmodule

RTL Schematic
 // 4-to-1 MUX (DataFlow Modeling):
module mux4_to_1(I, S, Y);
input [3 : 0] I;
input [1: 0] S;
output Y;
assign Y = I[S];
endmodule

Test Bench

`timescale 1ns / 1ps

module tb_mux_4_to_1;
reg [3:0] I; // Inputs
reg [1:0] S;
wire Y; // Outputs

// Instantiate the Unit Under Test (UUT)

mux_4_to_1_st uut (.I(I), .S(S), .Y(Y));
initial
begin
// Initialize Inputs
I = 0; S = 0;
// Add stimulus here
#10 I = 4'b0001; S = 2'b00;
#10 I = 4'b1011; S = 2'b00;
#10 I = 4'b0101; S = 2'b01;
#10 I = 4'b1111; S = 2'b01;
#10 I = 4'b1001; S = 2'b10;
#10 I = 4'b1101; S = 2'b10;
#10 I = 4'b1011; S = 2'b11;
#10 I = 4'b1101; S = 2'b11;
#10 $finish;
end
endmodule

Simulation Results:
(c) 8:1 Mux (Using 4:1 and 2:1 Mux : Structural modeling) (Exercise for Students)

(d) 16:1 Mux (Using Behavioural Modeling & 4:1 Mux : Structural modeling)
(Exercise for Students)

I0 I15
I1 I14 4:1 Y1
I13 MUX
I3 .
. 16 : 1 I12
Y
. MUX
. S1 S0
I14 I11
I15 I10 4:1 Y2
I9 MUX

S3 S2 S1 S0 I8 4:1
MUX Y
S 1 S0
I7
I6 4:1 Y3
I5 MUX
I4
S1 S0
I3
I2 4:1 Y4
I1 MUX
I0

S1 S0 S3 S2

(e) 1:8 DEMUX (Exercise for Students)

DEMUX: A digital combinational circuit which takes one input line and routs it to one of the
multiple output lines depending on the status of the select lines is known as demultiplexer or
DEMUX.

Y7
Y6
Y5
1:8 Y4
I
DEMUX Y3
Y2
Y1
Y0

S 2 S1 S0
Conclusion:

Suggested Reference:

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 8:1 Mux

• Behavioural modeling
module m8X1(out, D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2);
input wire D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2;
output reg out;
always@(*)
begin
case(S0 & S1 & S2)
3'b000: out=D0;
3'b001: out=D1;
3'b010: out=D2;
3'b011: out=D3;
3'b100: out=D4;
3'b101: out=D5;
3'b110: out=D6;
3'b111: out=D7;
default: out=1'b0;
endcase
end
endmodule

• Test Bench
module top;
wire out;
reg D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2;
m8X1 name(.D0(D0), .D1(D1), .D2(D2), .D3(D3), .D4(D4), .D5(D5),
.D6(D6), .D7(D7), .S0(S0), .S1(S1), .S2(S2), .out(out));
initial
begin
D0=1'b0; D1=1'b0; D2=1'b0; D3=1'b0; D4=1'b0; D5=1'b0; D6=1'b0;
D7=1'b0;S0=1'b0; S1=1'b0; S2=1'b0;
#500 $finish;
end
always #1 D0=~D0;
always #2 D1=~D1;
always #3 D2=~D2;
always #4 D3=~D3;
always #5 D4=~D4;
always #6 D5=~D5;
always #7 D6=~D6;
always #8 D7=~D7;
always #9 S0=~S0;
always #10 S1=~S1;
always #11 S2=~S2;
always@(D0 or D1 or D2 or D3 or D4 or D5 or D6 or D7 or S0 or S1 or
S2)
$monitor("At time = %t, Output = %d", $time, out);
endmodule;
16:1 Mux (Using Behavioural Modeling & 4:1 Mux : Structural modeling)

• RTL Code:
module MUX2X1(i, s, y);
input [1 : 0] i;
input s;
output y;
assign y = s ? i[1] : i[0];
endmodule
// 4-to-1 MUX module
module MUX4X1(I, S, Y);
input [3 : 0] I;
input [1: 0] S;
output Y;
wire [1: 0] t;
MUX2X1 M1(I[3:2],S[0],t[1]);
MUX2X1 M2(I[1:0],S[0],t[0]);
MUX2X1 M3(t[1:0],S[1],Y);
endmodule

module MUX16X1(I,S,Y);
input [15:0]I;
input [3:0]S;
output Y;
wire [3:0]t;
//INSTANTIATE 4X1 MUX
MUX4X1 m1(I[3:0],S[1:0],t[0]);
MUX4X1 m2(I[7:4],S[1:0],t[1]);
MUX4X1 m3(I[11:8],S[1:0],t[2]);
MUX4X1 m4(I[15:12],S[1:0],t[3]);
MUX4X1 M(t[3:0],S[3:2],Y);
endmodule

• Test Bench
module MUX16X1_tb;
reg [15:0]I;
reg [3:0]S;
wire Y;
MUX16X1 uut(.I(I),.S(S),.Y(Y));
initial
begin
S = 0; I = 0;
#10 I = 16'b1010101100111010; S = 4'b0111;
#10 I = 16'b1010101100110010; S = 4'b0011;
#10 I = 16'b1011101100111010; S = 4'b0101;
#10 I = 16'b1010101100111011; S = 4'b0110;
#10 I = 16'b1010101100111000; S = 4'b0100;
#10 I = 16'b1010101100111110; S = 4'b0001;
#10 I = 16'b1010101100101010; S = 4'b0000;
#10 I = 16'b1010101110111010; S = 4'b1111;
#10 I = 16'b1011101100111010; S = 4'b1010;
#10 I = 16'b1110101100111010; S = 4'b1110;
end
endmodule
 1:8 DEMUX

• RTL Code:
module DEMUX8X1 (in,s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
input in,s0,s1,s2;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0=(in & ~s2 & ~s1 &~s0),
d1=(in & ~s2 & ~s1 &s0),
d2=(in & ~s2 & s1 &~s0),
d3=(in & ~s2 & s1 &s0),
d4=(in & s2 & ~s1 &~s0),
d5=(in & s2 & ~s1 &s0),
d6=(in & s2 & s1 &~s0),
d7=(in & s2 & s1 &s0);
endmodule

• Test Bench:
module DMUX1X8_tb;
reg in,s0,s1,s2;
wire d0,d1,d2,d3,d4,d5,d6,d7;
DEMUX8X1 uut(in,s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
initial
begin
in=0; s0=0; s1=0;s2=0;
#10 in=1;
#10 s0 = 0; s1 = 0; s2 = 0;
#10 s0 = 0; s1 = 1; s2 = 0;
#10 s0 = 0; s1 = 0; s2 = 1;
#10 s0 = 1; s1 = 0; s2 = 0;
#10 s0 = 0; s1 = 1; s2 = 1;
#10 s0 = 1; s1 = 0; s2 = 1;
#10 s0 = 1; s1 = 1; s2 = 0;
#10 s0 = 1; s1 = 1; s2 = 1;
#10 $finish;
end
endmodule
 Experiment No: 8

Date: __________________

Aim: Design 2:4, 3:8, 4:16 Decoders using Verilog/VHDL.

Competency and Practical Skills:

Relevant CO:

Objectives:

Equipment / Instruments: Laptop or Computer with Xilinx / Altera (Intel) Tools.

Basic Theory: Decoder is a combinational circuit that has 'n' input lines and maximum of 2n output
lines. Depending on the code presented by input lines, one of the output lines will be active high,
when the decoder is enabled. It reveals a decoder detects a particular code presented at input.
(a) 2-to-4 Decoder
Truth Table of 2-to-4 Decoder
D3 Enable Inputs Outputs
I1 2:4 D2 E I1 I0 D3 D2 D1 D0
I0 Decoder D1 0 X X 0 0 0 0
1 0 0 0 0 0 1
D0
1 0 1 0 0 1 0
1 1 0 0 1 0 0
E
1 1 1 1 0 0 0

RTL Code (DataFlow Modeling):

module Decoder2to4_df(I,E,D);
input [1:0] I;
input E;
output [3:0] D;
assign D = {E&I[1]&I[0],E&I[1]&~I[0],E&~I[1]&I[0],E&~I[1]&~I[0]};

endmodule

RTL Schematic:
Test Bench:
`timescale 1ns / 1ps
module tb_Deco2to4;
reg [1:0] I; reg E; // Inputs
wire [3:0] D; // Outputs
// Instantiate the Unit Under Test (UUT)
Decoder2to4_df uut (.I(I), .E(E), .D(D));
initial begin
// Initialize Inputs
E = 0; I = 2'b00;
// Add stimulus here
#10 E = 0; I = 2'b10;
#10 E = 0; I = 2'b11;
#10 E = 0; I = 2'b00;
#10 E = 1; I = 2'b00;
#10 E = 1; I = 2'b01;
#10 E = 1; I = 2'b10;
#10 E = 1; I = 2'b11;
#10 E = 0; I = 2'b00;
#10 $finish;
end
endmodule

Simulation waveform:

(b) 3-to-8 Decoder (Behavioural Modeling):

module Decoder3to8_bh(I,E,D);
input [2:0] I; input E;
output [7:0] D;
always @(I, E)
begin
case({E,I})
4'b1000: D = 8'b00000001;
4'b1001: D = 8'b00000010;
4'b1010: D = 8'b00000100;
4'b1011: D = 8'b00001000;
4'b1100: D = 8'b00010000;
4'b1101: D = 8'b00100000;
4'b1110: D = 8'b01000000;
4'b1111: D = 8'b10000000;
default: D = 8'b00000000;
endcase
end
endmodule
Simulation waveforms:

(c) 4-to-16 Decoder (Structural Modeling using 3-to-8 Decoder): (Exercise for Students)

D15
D14
I2 D13
I1 D12
3:8 D11
I0 Decoder D10
D9
D8
I3 E1

E
D7
D6
D5
D4
3:8 D3
Decoder D2
D1
D0
E0

Conclusion:

Suggested Reference:

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 4-to-16 Decoder (Structural Modeling using 3-to-8 Decoder)
• RTL Code:
module decoder3_to_8( out,in[0],in[1],in[2], en);
output [7:0] out;
input [2:0] in;
input en;
reg [7:0] out;
always @( in or en)
begin
if (en)
begin
out=8'd0;
case (in)
3'b000: out[0]=1'b1;
3'b001: out[1]=1'b1;
3'b010: out[2]=1'b1;
3'b011: out[3]=1'b1;
3'b100: out[4]=1'b1;
3'b101: out[5]=1'b1;
3'b110: out[6]=1'b1;
3'b111: out[7]=1'b1;
default: out=8'd0;
endcase
end
else
out=8'd0;
end
endmodule
module de4x16(I,Y);
input [3:0]I;
output [15:0]Y;
wire t;
not n1(t,I[3]);
// ISTANTIATE 3X8 DECODER
decoder3_to_8 d1(Y[7:0],I[0],I[1],I[2],I[3]);
decoder3_to_8 d2(Y[15:8],I[0],I[1],I[2],t);
endmodule

• Test Bench:
module de_4x16_tb;
reg [3:0]I;
wire [15:0]Y;
de4x16 uut(.I(I),.Y(Y));
initial
begin
I = 4'b0000;
#100 I = 4'b0001;
#100 I = 4'b0001;
#100 I = 4'b0010;
#100 I = 4'b0011;
#100 I = 4'b0100;
#100 I = 4'b0101;
#100 I = 4'b0110;
#100 I = 4'b0111;
#100 I = 4'b1000;
#100 I = 4'b1001;
#100 I = 4'b1010;
#100 I = 4'b1011;
#100 I = 4'b1100;
#100 I = 4'b1101;
#100 I = 4'b1110;
#100 I = 4'b1111;
end
endmodule
 Experiment No: 9

Date: __________________

Aim: Design 4:2, 8:3 Priority Encoder using Verilog / VHDL.

Competency and Practical Skills:

Relevant CO:

Objectives:

Equipment / Instruments: Laptop or Computer with Xilinx / Altera (Intel) Tools.

Basic Theory: An Encoder is a combinational circuit that performs the reverse operation of
Decoder. It has maximum of 2n input lines and ‘n’ output lines. It will produce a binary code
depending on the input line activated.

Truth Table of 4-to-2 Encoder

D3
I1 Enable Inputs Outputs
D2 4:2
E D3 D2 D1 D0 I1 I0
D1 Encoder I0 0 X X X X X X
D0 1 1 0 0 0 1 1
1 0 1 0 0 1 0
E 1 0 0 1 0 0 1
1 0 0 0 1 0 0

Priority Encoder: A priority encoder produces correct code at the output even when multiple lines
at the inputs are simultaneously active high (logic ‘1’). As shown above, the 4-to-2 priority encoder
has four inputs (D3, D2, D1, D0) and two outputs (I1 and I0). Here, the input, D3 has the highest
priority; whereas, the input, D0 has the lowest priority. In this case, even if more than one input
lines are at logic ‘1’ at the same time, the output will be the binary code corresponding to the input,
which is having higher priority.

(a) 4 : 2 Priority Encoder

RTL Code:
module Encoder4to2_bh(D,E,I);
input [3:0] D;
input E;
output reg [1:0] I;

always @(D,E)
begin
casex({E,D})
5'b11xxx: I = 2'b11;
5'b101xx: I = 2'b10;
5'b1001x: I = 2'b01;
5'b10001: I = 2'b00;
default: I = 2'bzz;
endcase
end
endmodule
RTL Schematic:

Simulation waveforms:

(b) 8:3 Priority Encoder

Conclusion:

Suggested Reference:

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 8:3 Priority Encoder

• RTL Code:
module ENC8X3(Y,X,E);
output reg [2:0]Y;
input [7:0]X;
input E;
always@(Y,X,E)
if(E==1)
begin
if(X[7]==1)
begin
Y=3'b111;
end
else if(X[6]==1)
begin
Y=3'b110;
end
else if(X[5]==1)
begin
Y=3'b101;
end
else if(X[4]==1)
begin
Y=3'b100;
end
else if(X[3]==1)
begin
Y=3'b011;
end
else if(X[2]==1)
begin
Y=3'b010;
end
else if(X[1]==1)
begin
Y=3'b001;
end
else if(X[0]==1)
begin
Y=3'b000;
end
 end
else;
endmodule

• Test Bench:
module ENC8X3_tb;
reg [7:0]X;
reg E;
wire [2:0]Y;
ENC8X3 uut(.Y(Y), .E(E),.X(X));
initial
begin
E=1;
X=8'h0_1;
#30;
X=8'h0_2;
#30;
X=8'h0_4;
#30;
X=8'h0_8;
#30;
X=8'h1_0;
#30;
X=8'h2_0;
#30;
X=8'h4_0;
#30;
X=8'h8_0;
#30;
$finish;
end
endmodule
 Experiment No: 10

Date:

Aim: Design 4-bit Comparator using Verilog / VHDL.

Competency and Practical Skills:

Relevant CO:

Objectives:

Equipment / Instruments: Laptop or Computer with Xilinx / Altera (Intel)Tools.

Basic Theory:

Program Code:
module comp4bit(E,G,L,A,B);
input [3:0] A,B;
output E,G,L;
assign E = (A==B) ? 1 : 0;
assign G = (A>B) ? 1 : 0;
assign L = (A<B) ? 1 : 0;
endmodule

RTL Schematic:
Output waveform:

Conclusion:

Quiz:

Suggested Reference:

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 Experiment No: 11

Date:

Aim: Design BCD and Ripple Carry Adder using Verilog / VHDL.

Competency and Practical Skills:

Relevant CO:

Objectives:

Equipment / Instruments: Laptop or Computer with Xilinx / Altera (Intel)Tools.

Basic Theory:

BCD Adder Block diagram:

Program Code:
module HA(S,C,A,B);
input A,B;
output S,C;
xor G1(S,A,B);
and G2(C,A,B);

endmodule
// FUll adder using half adder//
module FA(S,C,A,B,Cin);
input A,B,Cin;
output S,C;
wire W1,S0,C0;
// Instantiate half adder
HA H1(S0,C0,A,B);
HA H2(S,W1,S0,Cin);
or G3(C,C0,W1);
endmodule

//Ripple Carry Adder using FULL adder//

module RCA_4bit(S,Cout,A,B,Cin);
output [3:0]S;
output Cout;
input [3:0]A;
input [3:0]B;
input Cin;
wire C1,C2,C3;
// Instantiate FULL adder
FA F1(S[0],C1,A[0],B[0],Cin);
FA F2(S[1],C2,A[1],B[1],C1);
FA F3(S[2],C3,A[2],B[2],C2);
FA F4(S[3],Cout,A[3],B[3],C3);
endmodule

RTL Schematic:
Output waveform:

Conclusion:

Suggested Reference:

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 Experiment No: 12

Date:

Aim: Design of S-R and D latches with structural / behavioral modeling using Verilog
/ VHDL.
Competency and Practical Skills:

Relevant CO:

Objectives:

Equipment / Instruments: Laptop or Computer with Xilinx / Altera (Intel)Tools.

Basic Theory:

D – Latch SR Latch

Truth Table of D - Latch Truth Table SR Latch

 D_latch

Program Code
module D_LATCH(d,en,rst,q,q_bar);
input d,en,rst;
output reg q;
output q_bar;
always@(*)
begin
if(rst)
q <= 0;
else
begin
if(en)
q <= d;
end
end
assign q_bar=~q;
endmodule

Testcode:
module D_LATCH_tb;
reg d,en,rst;
wire q,q_bar;

D_LATCH dut(d,en,rst,q,q_bar);

initial begin

#0; d=0; en=0; rst=0;

#5; d=1; en=1; rst=1;
#5; d=0; rst=0;
#5; d=1;
#5; d=0; en=0;
#5; $finish;
end
endmodule
RTL Schematic:

Output waveform:

SR_LATCH

Program Code

module sr_latch(s,r,en,rst,q,q_bar);
input s,r,en,rst;
output reg q,q_bar;

always @ (*)
begin

if(rst) //if system is at reset then q=0 and q_bar=1

begin
q<=0;
q_bar<=1;
end
else if(en)
begin
case({s,r})
2'b00 : begin q<=q; q_bar<=q_bar; end
 2'b01 : begin q<=0; q_bar<=1; end
2'b10 : begin q<=1; q_bar<=0; end
2'b11 : begin q<=0; q_bar<=0; end
default : begin q<=1'bx; q_bar<=1'bx; end
endcase
end
end

endmodule

Testcode:

module tb_sr_latch();
reg s,r,en,rst;
wire q,q_bar;

sr_latch dut(s,r,en,rst,q,q_bar);
initial begin

#0; s=0; r=0; en=0; rst=0;

#100; en=1; rst=1;
#100; s=1; rst=0;
#100; s=0; r=1;
#100; s=1; r=1;
#100; s=0; r=0;
#100; s=1; r=0;
#100; $finish;

end
endmodule

RTL Schematic and waveform

 Conclusion:

Suggested Reference:

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 Experiment No: 13

Date:

Aim: Design positive edge triggered D FF with asynchronous / synchronous active high
reset using Verilog / VHDL.

Competency and Practical Skills:

Relevant CO:

Objectives:

Equipment / Instruments: Laptop or Computer with Xilinx / Altera (Intel)Tools.

Basic Theory:

Program Code:
module D_flipflop (
input clk, rst_n,
input d,
output reg q
);

always@(posedge clk) begin

if(rst_n) q <= 0;
else q <= d;
end
endmodule

RTL Schematic:
Output waveform:

Conclusion:

Suggested Reference:

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 Experiment No: 14

Date:

Aim: Design serial in serial out and serial in parallel out shift registers using Verilog /
VHDL.

Competency and Practical Skills:

Relevant CO:

Objectives:

Equipment / Instruments: Laptop or Computer with Xilinx / Altera (Intel) Tools.

Basic Theory:

SISO(Serial in serial out)

Program Code:
module siso(in,clk,out);
input in,clk;
output out;
reg q0,q1,q2,q3;

always@(posedge clk)
begin
q3<=in;
q2<=q3;
q1<=q2;
q0<=q1;
end

assign out = q0;

endmodule

RTL Schematic:

Output waveform:
 SIPO(Serial in Parallel out)
Program Code:
module sipo(in,clk,out);
input in,clk;
output [3:0] out;
reg q0,q1,q2,q3;

always@(posedge clk)
begin

q3<=in;
q2<=q3;
q1<=q2;
q0<=q1;

end
assign out[0]=q0;
assign out[1]=q1;
assign out[2]=q2;
assign out[3]=q3;
endmodule

RTL Schematic:
Outputwaveform:

Conclusion:

Suggested Reference:

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 Experiment No: 15

Date:

Aim: Design Counter using Verilog / VHDL.

1. BCD Counter.
2. Up-Down Counter

Competency and Practical Skills:

Relevant CO:

Objectives:

Equipment / Instruments: Laptop or Computer with Xilinx / Altera (Intel) Tools.

Basic Theory:

BCD Counter

Program Code:
module bcd9(count,rst,clk);
input rst,clk;
output [3:0]count;
reg [3:0]count;
always @(posedge clk , negedge rst)
begin
if(~rst)
count=4'b0000;
else if(count<4'b1001)
count=count+4'b0001;end
endmodule

RTL Schematic:

Output waveform:
 Up-Down Counter

Program Code:
module upordown_counter(
Clk,
reset,
UpOrDown,
//high for UP
counter and low for
Down counter
Count
);
//input ports and
their sizes
input

Clk,reset,UpOrDow

n;

//output ports and

their size

output [3 : 0]

Count;

//Internal
variables
reg [3 : 0] Count
= 0;

always
@(posedge(Clk)or
posedge(reset))
begin
if(reset == 1)
Count <= 0;
else

if(UpOrDown ==
1) //Up mode
selected
if(Count
== 15)
Count
<= 0;
else
Count
<= Count + 1;
//Incremend
Counter
else //Down
mode selected
if(Count
== 0)
Count
<= 15;
else
Count
<= Count - 1;
//Decrement
counter
end
endmodule

RTL Schematic:

Output waveform:
Conclusion:

Suggested Reference:

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 Experiment No: 16

Date:

Aim: Introduction to Microwind tool.

Competency and Practical Skills:

Relevant CO:

Objectives:

Equipment / Instruments: Laptop or Computer with Microwind tool.

Introduction:

MICROWIND TOOL

MICROWIND3 is user friendly layout and simulation tool for sub-micron CMOS design. The
MICROWIND3 allows the designer to simulate and design an integrated circuit at physical
description level. The package contains a library of common logic and analog ICs to design and
simulate. MICROWIND3 includes all the commands for a mask editor as well as verification
tools never gathered before in a single module.

MICROWIND3 is truly a complete and cost-effective design solution for your CMOS design.
nanoLambda
VirtuosoFab
MEMsim
PROthumb
PROtutor

DSCH Schematic editor and simulator

User-friendly environment for rapid design of logic circuits.
Handles both conventional pattern-based logic simulation and intuitive on-screen mouse-
driven simulation.
Supports hierarchical logic design.
Built-in extractor which generates a SPICE netlist from the schematic diagram (Compatible
with PSPICE™ and WinSpice™).
Current and power consumption analysis.
Generates a VERILOG description of the schematic for layout editor.
Immediate access to symbol properties (Delay, fanout).
Sub-micron, deep-submicron, nanoscale technology support.
Supported by huge symbol library.
NanoLambda Precision CMOS Layout tool upto 35 nanometers.
Sub-micron, deep-submicron, nanoscale technology support.
Unsurpassed illustration capabilities.
Design-error-free cell library (Contacts, vias, MOS devices, etc..)
Advanced macro generator: capa, self, matrix, ROM, pads, path, etc..)
Incredible translator from logic expression into compact design-error free layout.
Powerful automatic compiler from VERILOG circuit into layout.
On-line design rule checker: width, spacing, overlap, extension rule verification.
Built-in extractor which generates a SPICE netlist from layout.
Extraction of all MOS width and length.
Parasitic capacitance, crosstalk and resistance extracted for all electrical nodes.
Import/Export CIF layout from 3rd party layout tools.
Up to 100,000 elementary boxes.
Lock & unlock layers to protect some part of the design from any changes.
Enhanced editing commands and layout control.
Support upto 8 metal layers for DSM technologies.
Global delay evaluation of circuit.
Global cross talk analyzer.
Inversion of diffusions boxes.
Easy label listing.
Enhanced mathematical signal description.
Zoom in navigator.
Support till 22 nanometer technology.
Enhanced memory utilization for faster simulation.
Silicon atom viewer.
Technology library available Minimum feature size
Cmos12.rul 1.2mm
Cmos08.rul 0.7mm
Cmos06.rul 0.5mm
Cmos035.rul 0.4mm
Cmos025.rul 0.25mm
Cmos018.rul 0.2mm
Cmos012.rul 0.12mm
Cmos90n.rul 0.1mm
Cmos70n.rul 0.07mm
Cmos50n.rul 0.05mm

Conclusion:

Suggested Reference:

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 Experiment No: 17

Date:

Aim: Implementation of Resistive load and CMOS inverters using Microwind.

Competency and Practical Skills:

Relevant CO:

Objectives:

Equipment / Instruments: Laptop or Computer with Microwind Tool.

Resistive Load Inverter Layout (CMOS 0.12um TECHNOLOGY using Microwind3)

Simulation Waveforms
 CMOS Inverter Layout (CMOS 0.12um TECHNOLOGY using Microwind3)

Simulation Waveforms
Conclusion:

Suggested Reference:

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks
 Experiment No: 18

Date:

Aim: Implementation of CMOS NAND and NOR gate using Microwind.

Competency and Practical Skills:

Relevant CO:

Objectives:

Equipment / Instruments: Laptop or Computer with Microwind Tool.

Basic Theory:

2-input NAND Gate Layout (CMOS 0.12um TECHNOLOGY using Microwind3)

Simulation Waveforms

2-Input NOR Gate Layout (CMOS 0.12um TECHNOLOGY using Microwind3)

Simulation Waveforms

Conclusion:

Suggested Reference:

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks