CS222: Computer Architecture

Instructors:
Dr Fatma Sakr https://bu.edu.eg/staff/fatma
 Chapter 3 :: Topics
• Introduction
• Latches and Flip-Flops
• Synchronous Logic Design
• Finite State Machines
• Timing of Sequential Logic
• Parallelism

Chapter 3 <2>
 Introduction
• Outputs of sequential logic depend on current
and prior input values – it has memory.
• Some definitions:
– State: all the information about a circuit necessary
to explain its future behavior
– Latches and flip-flops: state elements that store
one bit of state
– Synchronous sequential circuits: combinational
logic followed by a bank of flip-flops

Chapter 3 <3>
 Sequential Circuits
• Give sequence to events
• Have memory (short-term)
• Use feedback from output to input to store
information

Chapter 3 <4>
 State Elements
• The state of a circuit influences its future
behavior
• State elements store state
– Bistable circuit
– SR Latch
– D Latch
– D Flip-flop

Chapter 3 <5>
 Bistable Circuit
• Fundamental building block of other state
elements
• Two outputs: Q, Q
• No inputs
I1 Q
Q Q
I2 I1

I2 Q

Chapter 3 <6>
 Bistable Circuit Analysis
• Consider the two possible cases:
– Q = 0: I1
0
Q
1
then Q = 1, Q = 0 (consistent)
0 1
I2 Q

– Q = 1:
1
I1 Q
then Q = 0, Q = 1 (consistent) 0

1 0
I2 Q

• Stores 1 bit of state in the state variable, Q (or Q)

• But there are no inputs to control the state
Chapter 3 <7>
 SR Latch Analysis
– S = 1, R = 0: R
0
1
N1 Q
then Q = 1 and Q = 0 0

Set the output 0

1 N2
0
Q
S

– S = 0, R = 1: 1
R 0
N1 Q
then Q = 1 and Q = 0 1
Reset the output 0
1
0 N2 Q
S

Chapter 3 <8>
 SR Latch Symbol
• SR stands for Set/Reset Latch
– Stores one bit of state (Q)
• Control what value is being stored with S, R
inputs
SR Latch
– Set: Make the output 1 Symbol
(S = 1, R = 0, Q = 1)
R Q
– Reset: Make the output 0
(S = 0, R = 1, Q = 0) S Q

Chapter 3 <9>
 D Latch
• Two inputs: CLK, D
– CLK: controls when the output changes
– D (the data input): controls what the output changes to
• Function D Latch
– When CLK = 1, Symbol
D passes through to Q (transparent) CLK
– When CLK = 0,
D Q
Q holds its previous value (opaque)
Q
• Avoids invalid case when
Q ≠ NOT Q
Chapter 3 <10>
D Latch Internal Circuit
CLK R CLK
D R Q Q

S
D Q
S Q Q
D
Q

CLK D D S R Q Q
0 X X 0 0 Qprev Qprev
1 0 1 0 1 0 1
1 1 0 1 0 1 0

Chapter 3 <11>
 D Flip-Flop
• Inputs: CLK, D D Flip-Flop
Symbols
• Function
– Samples D on rising edge of CLK
• When CLK rises from 0 to 1, D D Q
passes through to Q Q
• Otherwise, Q holds its previous
value
– Q changes only on rising edge of
CLK
• Called edge-triggered
• Activated on the clock edge
Chapter 3 <12>
 D Flip-Flop Internal Circuit
• Two back-to-back latches (L1 and L2) controlled by
complementary clocks
CLK
• When CLK = 0
– L1 is transparent
– L2 is opaque CLK CLK
– D passes through to N1 N1
D D Q D Q Q
• When CLK = 1 L1 Q L2 Q Q
– L2 is transparent
– L1 is opaque
– N1 passes through to Q
• Thus, on the edge of the clock (when CLK rises from 0 1)
– D passes through to Q

Chapter 3 <13>
 D Latch vs. D Flip-Flop
CLK
D Q D Q
Q Q

CLK

Q (latch)

Q (flop)

Chapter 3 <14>
Registers
CLK

D0 D Q Q0

CLK
D1 D Q Q1 4 4
D3:0 Q3:0
D2 D Q Q2

D3 D Q Q3

Chapter 3 <15>
 Enabled Flip-Flops
• Inputs: CLK, D, EN
– The enable input (EN) controls when new data (D) is stored
• Function
– EN = 1: D passes through to Q on the clock edge
– EN = 0: the flip-flop retains its previous state
Internal
Circuit
Symbol
EN CLK

0
D Q Q D Q
D 1
EN

Chapter 3 <16>
 Resettable Flip-Flops
• Inputs: CLK, D, Reset
• Function:
– Reset = 1: Q is forced to 0
– Reset = 0: flip-flop behaves as ordinary D flip-flop

Symbols

D Q
r
Reset

Chapter 3 <17>
 Resettable Flip-Flops
• Two types:
– Synchronous: resets at the clock edge only
– Asynchronous: resets immediately when Reset = 1
• Asynchronously resettable flip-flop requires
changing the internal circuitry of the flip-flop
• Synchronously resettable flip-flop?

Chapter 3 <18>
 Resettable Flip-Flops
• Two types:
– Synchronous: resets at the clock edge only
– Asynchronous: resets immediately when Reset = 1
• Asynchronously resettable flip-flop requires
changing the internal circuitry of the flip-flop
• Synchronously resettable flip-flop?
Internal
Circuit
CLK

D
D Q Q
Reset

Chapter 3 <19>
 Settable Flip-Flops
• Inputs: CLK, D, Set
• Function:
– Set = 1: Q is set to 1
– Set = 0: the flip-flop behaves as ordinary D flip-flop

Symbols

D Q
s
Set

Chapter 3 <20>
 Synchronous Sequential Logic Design
• Breaks cyclic paths by inserting registers
• Registers contain state of the system
• State changes at clock edge: system synchronized to the
clock
• Rules of synchronous sequential circuit composition:
– Every circuit element is either a register or a combinational circuit
– At least one circuit element is a register
– All registers receive the same clock signal
– Every cyclic path contains at least one register
• Two common synchronous sequential circuits
– Finite State Machines (FSMs)
– Pipelines

Chapter 3 <21>
 Finite State Machine (FSM)
• Consists of: CLK

– State register S’
Next
S
Current
• Stores current state State State

• Loads next state at clock edge

– Combinational logic
• Computes the next state
• Computes the outputs
Next State Output
Logic Logic

CL Next
State
CL Outputs

Chapter 3 <22>
 Finite State Machines (FSMs)
• Next state determined by current state and inputs
• Two types of finite state machines differ in output logic:
– Moore FSM: outputs depend only on current state
– Mealy FSM: outputs depend on current state and inputs
Moore FSM

CLK
M next
next k state k state output N
inputs state outputs
logic
logic

Mealy FSM

CLK
M next
next k state k state output N
inputs state outputs
logic
logic

Chapter 3 <23>
 FSM Example
• Traffic light controller
– Traffic sensors: TA, TB (TRUE when there’s traffic)
– Lights: LA, LB

Bravado
Dining
Hall
LB

LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms
Blvd.

Fields

Chapter 3 <24>
 FSM Black Box
• Inputs: CLK, Reset, TA, TB
• Outputs: LA, LB
CLK

TA Traffic LA
Light
TB Controller LB

Reset

Chapter 3 <25>
 FSM State Transition Diagram
• Moore FSM: outputs labeled in each state
• States: Circles
Reset
• Transitions: Arcs S0
LA: green
LB: red
Bravado

Dining
Hall
LB

LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms
Blvd.

Fields

Chapter 3 <26>
 FSM State Transition Diagram
• Moore FSM: outputs labeled in each state
• States: Circles T
Reset A

• Transitions: Arcs S0 T S1 A

LA: green LA: yellow

LB: red LB: red
Bravado

Dining
Hall
LB

LA TB
LA

Academic TA TA Ave.
LB Dorms
S3 S2
Labs TB
LA: red LA: red
LB: yellow LB: green
Blvd.

TB
Fields
TB

Chapter 3 <27>
FSM State Transition Table
TA
Reset
S0 TA S1
LA: green LA: yellow
Current Next LB: red LB: red
State Inputs State
S TA TB S'
S0 0 X
S3 S2
S0 1 X LA: red LA: red
LB: yellow LB: green
TB
S1 X X TB
S2 X 0
S2 X 1
S3 X X

Chapter 3 <28>
 FSM State Transition Table
TA
Reset
S0 TA S1
LA: green LA: yellow
Current Next LB: red LB: red
State Inputs State
S TA TB S'
S0 0 X S1
S3 S2
S0 1 X S0 LA: red LA: red
LB: yellow LB: green
TB
S1 X X S2 TB

S2 X 0 S3
S2 X 1 S2
S3 X X S0

Chapter 3 <29>
 FSM Encoded State Transition Table
Current State Inputs Next State
S1 S0 TA TB S'1 S'0 State Encoding
0 0 0 X
S0 00
0 0 1 X
0 1 X X S1 01
1 0 X 0 S2 10
1 0 X 1 S3 11
1 1 X X

Chapter 3 <30>
 FSM Encoded State Transition Table
Current State Inputs Next State
S1 S0 TA TB S'1 S'0 State Encoding
0 0 0 X 0 1
S0 00
0 0 1 X 0 0
0 1 X X 1 0 S1 01
1 0 X 0 1 1 S2 10
1 0 X 1 1 0 S3 11
1 1 X X 0 0

S'1 = S1  S0
S'0 = S1S0TA + S1S0TB

Chapter 3 <31>
 FSM Output Table

Current State Outputs

S1 S0 LA1 LA0 LB1 LB0 Output Encoding
0 0 green 00
0 1 yellow 01
1 0
red 10
1 1

Chapter 3 <32>
 FSM Output Table

Current State Outputs

S1 S0 LA1 LA0 LB1 LB0 Output Encoding
0 0 0 0 1 0 green 00
0 1 0 1 1 0 yellow 01
1 0 1 0 0 0
red 10
1 1 1 0 0 1

LA1 = S1
LA0 = S1S0
LB1 = S1
LB0 = S1S0

Chapter 3 <33>
FSM Schematic: State Register

CLK
S'1 S1

S'0 S0
r
Reset
state register

Chapter 3 <34>
 FSM Schematic: Next State Logic
CLK
S'1 S1

TA S'0 S0
r
TB Reset
S1 S0

inputs next state logic state register

Chapter 3 <35>
 FSM Schematic: Output Logic
CLK LA1
S'1 S1
LA0

TA S'0 S0
LB1
r
TB Reset
S1 S0 LB0

inputs next state logic state register output logic outputs

Chapter 3 <36>
 FSM Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)
TA
Reset
S0 TA S1
LA: green LA: yellow
LB: red LB: red

S3 S2
LA: red LA: red
LB: yellow LB: green
TB
TB

Chapter 3 <37>
 FSM State Encoding
• Binary encoding:
– i.e., for four states, 00, 01, 10, 11
• One-hot encoding
– One state bit per state
– Only one state bit HIGH at once
– i.e., for 4 states, 0001, 0010, 0100, 1000
– Requires more flip-flops
– Often next state and output logic is simpler

Chapter 3 <38>
 Moore vs. Mealy FSM
• Alyssa P. Hacker has a snail that crawls down a paper tape
with 1’s and 0’s on it. The snail smiles whenever the last two
digits it has crawled over are 01. Design Moore and Mealy
FSMs of the snail’s brain.

Chapter 3 <39>
 State Transition Diagrams
Moore FSM
Reset
0 1

S0 S1 S2
0 0 1
1 0 0
1

Mealy FSM
Reset
0/0

S0 S1
1/0 0/0

1/1

Mealy FSM: arcs indicate input/output

Chapter 3 <40>
Moore FSM State Transition Table

Current
State Inputs Next State State Encoding
S1 S0 A S'1 S'0 S0 00
0 0 0
0 0 1 S1 01
0 1 0 S2 10
0 1 1
1 0 0
1 0 1

Chapter 3 <41>
Moore FSM State Transition Table

Current
State Inputs Next State State Encoding
S1 S0 A S'1 S'0 S0 00
0 0 0 0 1
0 0 1 0 0 S1 01
0 1 0 0 1 S2 10
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0

S1’ = S0A
S0’ = A
Chapter 3 <42>
Moore FSM Output Table

Current State Output

S1 S0 Y
0 0
0 1
1 0

Chapter 3 <43>
Moore FSM Output Table

Current State Output

S1 S0 Y
0 0 0
0 1 0
1 0 1

Y = S1

Chapter 3 <44>
Mealy FSM State Transition & Output Table

Current Next
State Input State Output
S0 A S'0 Y State Encoding
0 0
0 1 S0 00
1 0 S1 01
1 1

Chapter 3 <45>
Mealy FSM State Transition & Output Table

Current Next
State Input State Output
S0 A S'0 Y State Encoding
0 0 1 0
0 1 0 0 S0 00
1 0 1 0 S1 01
1 1 0 1

Chapter 3 <46>
Moore FSM Schematic

A CLK
S'1 S1
Y

S'0 S0

r
Reset

Chapter 3 <47>
Mealy FSM Schematic

CLK
S'0 S0 Y

r
Reset

Chapter 3 <48>
 Moore & Mealy Timing Diagram

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Cycle 11

CLK

Reset

A 0 1 0 1 1 0 1 1 1
Moore Machine
S ?? S0 S1 S2 S1 S2 S0 S1 S2 S0

Y
Mealy Machine
S ?? S0 S1 S0 S1 S0 S1 S0

Chapter 3 <49>
 FSM Design Procedure
1. Identify inputs and outputs
2. Sketch state transition diagram
3. Write state transition table
4. Select state encodings
5. For Moore machine:
1. Rewrite state transition table with state encodings
2. Write output table
6. For a Mealy machine:
1. Rewrite combined state transition and output table with state
encodings
7. Write Boolean equations for next state and output logic
8. Sketch the circuit schematic
Chapter 3 <50>
 Parallelism
• Two types of parallelism:
– Spatial parallelism
• duplicate hardware performs multiple tasks at once
– Temporal parallelism
• task is broken into multiple stages
• also called pipelining
• for example, an assembly line

Chapter 3 <51>
 Parallelism Definitions
• Token: Group of inputs processed to produce
group of outputs
• Latency: Time for one token to pass from
start to end
• Throughput: Number of tokens produced
per unit time

Parallelism increases throughput

Chapter 3 <52>
 Parallelism Example
• Ben Bitdiddle bakes cookies to celebrate traffic light
controller installation
• 5 minutes to roll cookies
• 15 minutes to bake
• What is the latency and throughput without parallelism?

Chapter 3 <53>
 Parallelism Example
• Ben Bitdiddle bakes cookies to celebrate traffic light
controller installation
• 5 minutes to roll cookies
• 15 minutes to bake
• What is the latency and throughput without parallelism?

Latency = 5 + 15 = 20 minutes = 1/3 hour

Throughput = 1 tray/ 1/3 hour = 3 trays/hour

Chapter 3 <54>
 Parallelism Example
• What is the latency and throughput if Ben
uses parallelism?
– Spatial parallelism: Ben asks Allysa P. Hacker to
help, using her own oven { i.e. He uses duplicated H/W }
– Temporal parallelism:
• two stages: rolling and baking
• He uses two trays
• While first batch is baking, he rolls the
second batch, etc.

Chapter 3 <55>
 Spatial Parallelism
Latency:
time to
first tray
0 5 10 15 20 25 30 35 40 45 50

Time
Tray 1 Ben 1 Ben 1
Roll
Parallelism
Spatial

Tray 2 Alyssa 1 Alyssa 1

Bake
Tray 3 Ben 2 Ben 2
Legend
Tray 4 Alyssa 2 Alyssa 2

Latency = ?
Throughput = ?

Chapter 3 <56>
 Spatial Parallelism
Latency:
time to
first tray
0 5 10 15 20 25 30 35 40 45 50

Time
Tray 1 Ben 1 Ben 1
Roll
Parallelism
Spatial

Tray 2 Alyssa 1 Alyssa 1

Bake
Tray 3 Ben 2 Ben 2
Legend
Tray 4 Alyssa 2 Alyssa 2

Latency = 5 + 15 = 20 minutes = 1/3 hour

Throughput = 2 trays/ 1/3 hour = 6 trays/hour

Chapter 3 <57>
 Temporal Parallelism
Latency:
time to
first tray
0 5 10 15 20 25 30 35 40 45 50

Time
Tray 1 Ben 1 Ben 1
Parallelism
Temporal

Tray 2 Ben 2 Ben 2

Tray 3 Ben 3 Ben 3

Latency = ?
Throughput = ?

Chapter 3 <58>
 Temporal Parallelism
Latency:
time to
4th tray will end at
first tray time = 50+15 = 65
0 5 10 15 20 25 30 35 40 45 50
min
Time
Tray 1 Ben 1 Ben 1
Parallelism
Temporal

Tray 2 Ben 2 Ben 2

Tray 3 Ben 3 Ben 3

Latency = 5 + 15 = 20 minutes = 1/3 hour

Throughput = 1 trays/ 1/4 hour = 4 trays/hour [ for all except
first stage it will take 15 min. to end one tray]

Using both techniques, the throughput would be 8 trays/hour

Chapter 3 <59>