PANIMALAR INSTITUTE OF TECHNOLOGY

JAISAKTHI EDUCATIONAL TRUST

CHENNAI – 600 123

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

GE6252-BASIC ELECTRICAL AND ELECTRONICS ENGINEERING

UNIT-IV

DIGITAL ELECTRONICS
Binary Number System – Logic Gates – Boolean Algebra – Half and Full Adders – Flip-Flops –
Registers and Counters – A/D and D/A Conversion (single concepts)

Prepared By Approved by

Principal
 UNIT IV DIGITAL ELECTRONICS

Important Two mark Questions

1. Write the names of basic logical operators. (Dec 2005, April/May 2009)
1. NOT / INVERT 2. AND 3. OR
2. What are basic properties of Boolean algebra? (May 2008)
a. The basic properties of Boolean algebra are commutative property, associative
property and distributive property.
3. State the associative property of boolean algebra. (Nov/Dec 2010)
a. The associative property of Boolean algebra states that the OR ing of several
variables results in the same regardless of the grouping of the variables. The
associative property is stated as follows: A+ (B+C) = (A+B) +C
4. State the commutative property of Boolean algebra. (April/May 2011)
a. The commutative property states that the order in which the variables are OR ed
makes no difference. The commutative property is: A+B=B+A
5. State the distributive property of Boolean algebra. (May/June 2010)
a. The distributive property states that AND ing several variables and OR ing the
result with a single variable is equivalent to OR ing the single variable with each of the
the several variables and then AND ing the sums. The distributive property is:
A+BC= (A+B) (A+C)
6. What are the classifications of sequential circuits? (May 2007)
a. The sequential circuits are classified on the basis of timing of their signals into
two types.They are,
1) Synchronous sequential circuit. 2) Asynchronous sequential circuit.
7. Define Flipflop. (Dec 2005, (April/May 2011, June/July 2009)
a. The basic unit for storage is flipflop. A flip-flop maintains its output state either at
1 or 0 until directed by an input signal to change its state.
8. What are the different types of flip-flop? (May 2009, (April/May 2011, June/July
2009)
a. There are various types of flipflop. Some of them are mentioned below they are,
i)RS flip-flop ii) D flip-flop iii)JK flip-flop iv)T flip-flop
9. What is the operation of RS flip-flop?
a. *When R input is low and S input is high the Q output of flip-flop is set.
b. *When R input is high and S input is low the Q output of flip-flop is reset.
c. *When both the inputs R and S are low the output does not change
d. *When both the inputs R and S are high the output is unpredictable.
10. What is the operation of SR flip-flop?
a. *When R input is low and S input is high the Q output of flip-flop is set.
b. *When R input is high and S input is low the Q output of flip-flop is reset.
c. *When both the inputs R and S are low the output does not change.
 d. *When both the inputs R and S are high the output is unpredictable.
11. What is the operation of D flip-flop?
a. In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and
if D=0, the output is reset.
12. What is the operation of JK flip-flop? (Dec 2007, Nov/Dec 2010, April/May 2009)
a. *When K input is low and J input is high the Q output of flip-flop is set.
b. *When K input is high and J input is low the Q output of flip-flop is reset.
c. *When both the inputs K and J are low the output does not change
d. *When both the inputs K and J are high it is possible to set or reset
13. What is the operation of T flip-flop? (May 2003)
a. T flip-flop is also known as Toggle flip-flop.
b. *When T=0 there is no change in the output.
c. *When T=1 the output switch to the complement state (ie) the output toggles.
14. What are the different types of shift type? (Dec 2005)
a. There are five types. They are, ._Serial In Serial Out Shift Register ._Serial In
Parallel Out Shift Register ._Parallel In Serial Out Shift Register ._Parallel In
Parallel Out Shift Register ._Bidirectional Shift Register
15. Explain counter(June/July 2009, May/June 2010)
a. Synchronous counters - These counters use common clock pulse. It may be a up
counter or down counter. It uses JK flipflop.
b. Asynchronous counters - There is no common clock pulse. The output of each
flipflop is the clock pulse for next flipflop.It uses JK or T flipflop.
16. What are the classifications of sequential circuits?
a. The sequential circuits are classified on the basis of timing of their signals into
two types. They are,
1) Synchronous sequential circuit. 2) Asynchronous sequential circuit.
17. Define Flip flop. (Dec 2005, (April/May 2011, June/July 2009)
a. The basic unit for storage is flip flop. A flip-flop maintains its output state either
at 1 or 0 until directed by an input signal to change its state.
18. What is the operation of D flip-flop? (May 2009)
a. In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and
if D=0, the output is reset..
19. What is the operation of JK flip-flop?
*When K input is low and J input is high the Q output of flip-flop is set.
*When K input is high and J input is low the Q output of flip-flop is reset.
*When both the inputs K and J are low the output does not change
*When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the
output toggle on the next positive clock edge.
20. What is the operation of T flip-flop?
T flip-flop is also known as Toggle flip-flop.
*When T=0 there is no change in the output.
*When T=1 the output switch to the complement state (ie) the output toggles.
21. Define race around condition.
a. In JK flip-flop output is fed back to the input. Therefore change in the output
results change in the input. Due to this in the positive half of the clock pulse if
both J and K are high then output toggles continuously. This condition is called
‘race around condition’.
22. What is edge-triggered flip-flop?
a. The problem of race around condition can solved by edge triggering flip flop. The
term edge triggering means that the flip-flop changes state either at the positive
edge or negative edge of the clock pulse and it is sensitive to its inputs only at this
transition of the clock.
23. What is a master-slave flip-flop?
a. A master-slave flip-flop consists of two flip-flops where one circuit serves as a
master and the other as a slave.
b. The time required to change the voltage level from 90% to 10% is known as fall
time(tf).
24. 38.Define registers. (May 2008, (June/July 2009, May/June 2010)
a. A register is a group of flip-flops flip-flop can store one bit information. So an n-
bit register has a group of n flip-flops and is capable of storing any binary
information/number containing n-bits.
25. 39.Define shift registers. (Dec 2005) (June 2012)
a. The binary information in a register can be moved from stage to stage within the
register or into or out of the register upon application of clock pulses. This type of
bit movement or shifting is essential for certain arithmetic and logic operations
used in microprocessors. This gives rise to group of registers called shift registers.
26. 40.What are the different types of shift type? (June 2012)
There are five types. They are,
_Serial In Serial Out Shift Register
_Serial In Parallel Out Shift Register
_Parallel In Serial Out Shift Register
_Parallel In Parallel Out Shift Register
_Bidirectional Shift Register
27. Define sequential circuit? (April/May 2011, June/July 2009)
a. In sequential circuits the output variables dependent not only on the present input
variables but they also depend up on the past history of these input variables.
28. Give the comparison between combinational circuits and sequential circuits.
a. A combinational circuit Sequential circuits Memory unit is not required Memory
unity is required. Parallel adder is a combinational circuit Serial adder is a
sequential circuit
29. What do you mean by present state? (Dec 2004)
a. The information stored in the memory elements at any given time define as the
present state of the sequential circuit.
 IMPORTANT 16 MARKS QUESTION WITH ANSWERS

1. Draw and explain the operation of AND, OR, NOT, NAND and NOR gates with
suitable truth table.

The above said logic gates can be classified into following categories:
1. Basic Logic Gates
a. AND Gate
b. OR Gate
c. NOT Gate

2. Universal Gates
a. NAND Gate
b. NOR Gate

3. Combinational Gates
a. X-OR Gate
b. X-NOR Gate
The basic operations are described below with the aid of truth tables.

AND Gate

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high.
A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes
omitted i.e. AB.

OR Gate

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are
high. A plus (+) is used to show the OR operation.
NOT gate

The NOT gate is an electronic circuit that produces an inverted version of the input at its
output. It is also known as an inverter. If the input variable is A, the inverted output is known as
NOT A. This is also shown as A', or A with a bar over the top, as shown at the outputs.

Universal Gates

NAND Gate

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The
outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate
with a small circle on the output. The small circle represents inversion.

NOR Gate

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The
outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a
small circle on the output. The small circle represents inversion.

Combinational Gates

X-OR Gate

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its
two inputs are high. An encircled plus sign (⊕) is used to show the X-OR operation.
X-NOR Gate

The 'Exclusive-NOR' gate circuit does the opposite to the X-OR gate. It will give a low
output if either, but not both, of its two inputs are high. The symbol is an X-OR gate with a
small circle on the output. The small circle represents inversion.
n.

2. Design a full adder and implement it using logic gates.

Half adder is a circuit that will add two bits & produce a sum & a carry bit. It needs two input
bits & two output bits. Fig. Shows the block diagram of a half adder.

Ex-OR gate will only produce an output "1" when "EITHER" input is at logic "1", so we need an
additional output to produce a carry output, "1" when "BOTH" inputs "A" and "B" are at logic
"1" and a standard AND Gate fits the bill nicely. By combining the Ex-OR gate with the AND
gate results in a simple digital binary adder circuit known commonly as the "Half Adder" circuit.
Full Adder

Inputs Outputs
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Logic diagram of a Full adder

Truth Table for Full Adder

A half adder has only two inputs &there is no provision to add a carry coming from the lower
order bits when multi addition is performed. For this purpose, a full adder is designed.

The 1-bit Full Adder circuit is basically two half adders connected together and consists of three
Ex-OR gates, two AND gates and an OR gate, six logic gates in total. The truth table for the full
adder includes an additional column to take into account the Carry-in input as well as the
summed output and carry-output.

3. Draw and explain the operation following flip-flops,(i) RS flip flops using NOR gate (ii)
D flip-flops using NAND gate (iii) JK flip-flops using NAND gate(April/May 2015)16
marks

(i) RS flip flops using NOR gate

Fig shows a NOR SET-RESET flip-flop. Here the inputs are not complemented; therefore they
are active high.
When the SET input goes to a 1 and the RESET remains at 0, then the Q output goes to a 1 state.
Any 1 into a NOR gate will produce 0 output.

When the SET input returns to 0 and RESET is also 0, the outputs Q and  do not change. This
is because the output of the NOR gates are tied back to the opposite gates input. This keeps the
gates changing from states. To bring Q back to a 0, the RESET input must be made 1 while, the
SET input is held at O. The unused slate for the NOR SR flip flop is where the SET is 1 and the
RESET is 1. The first input to return to the 0 state will determine the output state of the Q and 
outputs. The truth table for the NOR SR flip flop is shown below.

Inputs Outputs
Comments
S R Q 

0 0 Q  Unchanged state

0 1 0 1 Reset
1 0 1 0 Set
1 1 1 1 Unused state

The difference between the :\OR SR FF and NAND SR FF are

i) The values of Q and Q in the unused state.
ii) Another difference is the SET and RESET inputs.
 , RESET
The NOR SR FF inputs are active HIGH and theSET  ip/s on the NAND gates are active
low. This means that the NOR SR FF will change state when an input goes HIGH or 1 and the
NAND will change state when input goes LOW or 0.

Clocked RS Flip Flop

CLK S R Qn+1
0 X X Last State Qn
1 0 0 Last State Qn
1 0 1 0
1 1 0 1
1 1 1 undefined

• It is required to set or reset the RS flip-flop in synchronism with a train of pulses known as
clock (CLK). Such a circuit is called a clocked set-reset flip-flop. Figure shows the logic diagram
of a clocked RS flip-flop.
• A flip flop which operates when input clock pulse is positive (not positive edge) in called a
latch. In marking the dock point. a flip flop employs a small triangle, while a latch does not have
it.
Operation

• Initially assume Q = 0 and = 1 and no clock is applied then irrespective of input‘s’ and 'R' the
outputs of G3 and G4 are at ‘1’ state. These outputs are applied to G1 and G2 result in which
there is no change in its previous state.

• If clock pulse is positive is at logic 1 level, then If S = 1 and R = O. then output of G3 is '0' and
output of G4 is '1', results in output of G1 is 1 and G2 is changed as '0'.

• If S = 0 and R = 1, then output of G3 is '1' and the output of 0" is '0' results in output of G1 is '0'
and G2 is changed. as '1'.

Thus the circuit responds to the inputs Sand R only when the clock is present (CLK = 1).

When the clock is not present (CLK = 0), the gates G3 and G4 are inhibited i.e., their outputs are
1, irrespective of the values of S or R and the circuit remains in the last state.

When both S = R = 1 along with a clock pulse, the Next state of the output cannot be determined.
JK Flip Flop

CLK J K Qn+1
0 X X No change
1 0 0 Qo No Change
1 0 1 0
1 1 0 1
1 1 1 Toggles Qo

The uncertain state of output in RS FF was eliminated in D FF by joining the inputs with an
inverter. But D FF is a single input FF which is able to transmit data from input to output. JK FF
is also similar to that of a RS FF, in such a way that it has 2 synchronous control inputs, but the
uncertain state has been eliminated. When J = K = 1, the FF toggles (changes)

Except from the feedback from Q and , the circuit remains the same as a RS FF. This feedback
clears the uncertainty (ambiguity) in the RS FF.

Operation of JK NAND FF

i) When J = K = 0
If Q was previously by 0,  = 1. When we apply clock input, the output of gate - 3 is 1.
This, in turn, along with  produces 0 in Q. If Q was previously 1,  = D. similarly, the output
of gate-3 is 0, if we apply the clock input. This along with  produces 1 in Q. Since, where both
J and K inputs are zero, there is no change in the output.

ii) When J = 0, K = 1
If Q = 1, then Q = 0. The output of gat-4 is zero. This in turn with Q produces a 1 is  .
Hence Q = O. If Q = 0 and  = 1, then output of gate-4 is one. This along with Q produces a 1 in
 . SO Q = 0. Thus, without considering of any previous state outputs, when J = 0 and K = 1, the
FF is reset.

iii) When J = 1 and K = 0

When Q = 1, = 0, the output of gate - 3 is 0, output of gate - 1 is 1. When Q = 0, = 1, the
output of gate - 3 is 0. Output of gate - 1 is I. Hence when J = 1 and K = 0, the output Q is
always 1, the FF is set.

iv] When J = 1 and K = 1

If Q = 1, then  = O. The output of JK FF is to be determined, when both the inputs are 1, by

the previous state. Here Q = 1. Hence along with K produces 0 in the gate-4output. This output
and Q together again produces a 1 in  . Therefore Q = 0. If Q = 0, then  =1.  along with J
produces a in the gate-3output. This output and  then produces a 1 in Q. Hence  = 0.
We can notice that the output is complemented when J = K = 1.

JK Master Slave FUp-Flop

The master Flip flop is positively clocked but the slave if negatively is negatively
clocked. Hence, the master FF responds to J and K inputs before the slave FF does. If J,=l and
K1= 0, the master sets on the positive clock edge. So, Q1 = HIGH. Now, the HIGH output of Q1
drives J2. During the negative clock transmission, the 2nd FF is set, by copying the action of the
master. If J1 = 0 and K, = 1, the master resets on the positive clock edge. :. Q1 = LOW. The
LOW output of Q1 is given to J2. During the negative clock transmission, the 2nd FF is reset,
again by copying the action of the master.

If both the inputs are 1, the master FF toggles positive edge and the slave FF toggles on negative
edge of the clock. If both 111einputs are low, there is no change in the output. This mode is
called "Inhibit. mode".
The four modes of operation for the master-slave FF is given in the table below.

Inputs outputs
J K Q(t) Q(t+1)
0 0 X X-in habit
0 1 X 0-Reset
1 0 X 1-Set
1 1 X X-Toggle
The master-slave if is best-suited for synchronous data transfer. Also
when the FF is edge triggered, the race condition is avoided.

4. Draw a neat diagram of a Ripple counter and explain the working of the Ripple counter
with suitable waveforms and truth table

Asynchronous counter (Ripple counter)

In this counter, the output of each flip-flop is connected to the input of the next flip-flop. These
counters are constructed by using clocked T flip-flops or J-K flip-flops with J = K = 1. The flip-
flop changes its state during the trailing edge of the clock pulse.

Figure shows the circuit of a. 3-bit asynchronous up counter. It has 3 J-K flip-flops connected in
cascade. The system clock, negative edge of square wave drives flip-flop A. The output of A
drives B, and the output of B drives flip-flop C. All the J and K inputs are tied to +Vcc. Each
flip-flop will change state toggle with a negative transition at Its clock input.

The A flip-flop must change state before it can trigger the B flip-flop and the B flip-flop
has to change state before it can trigger the C flip-flop and so on. The triggers move through the
flip-flops like a ripples counter in the counter, hence it is named as ripple counter.
 Count C B A
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

5. Write notes on D/A conversion. (May/June 2010)

Binary Weighted Resistor DAC

'The binary weighted resistor DAC uses operational amplifier to sum n binary weighted currents
derived from a reference voltage VR via current scaling resistors 2R, 4R, 8R ... 2nR. It is shown
in figure

Here, the switch positions are controlled by the digital inputs. When the digital input is one, the
corresponding switch is closed and digital input is zero, the switch is opened.

Here, the operational amplifier is used as a summing amplifier. Due to the high input impedance
of op-amp, summing current will flow through feedback resistor Rf. Now, the total current is
IT= I1+I2+I3+………+In

The output voltage is the voltage drop across Rf and it is given as

Vo= -ITRF
= -( I1+I2+I3+………+In) RF

 V V V V 
= −  d1 R + d 2 R + d3 R + ....... + d n nR +  R f
 2R 4R 8R 2 R 

VR
=−
R
( d1 2−1 + d 2 2−2 + d3 2−3 + ........ + d n 2−n ) R f

When Rf = R, the output voltage becomes

Vo = −VR ( d1 2−1 + d 2 2−2 + d3 2−3 + ........ + d n 2− n )

From this equation, analog output voltage is directly proportional to the input digital data.
R-2R Ladder

Figure shows R 2R ladder network. The input to the ladder network must switch from a voltage
representing '1' to ground representing '0'. It should be never being left open circuited. The
resistors which is load, is same for all bits of digital input. Figure shows 3-bit DAC. The switch
positions dl, d2, d3 corresponds to the binary word '100'. The circuit can be simplified to the
equivalent form. It is shown in figure.

From the above figure, the equivalent resistance at node 'A' with respect to ground is R.

2R × 2R
2R
2R = =R
2R + 2R
The resistance between node '8' and ground = R + R = 2R

Now, the equivalent 'resistance at node 'B' = 2R
2R = R

The resistance between node 'C' and ground = R + R = 2R as shown in figure.

Now from figure, the equivalent resistance.at node 'C' with respect to ground.

2R × R 2
= R
2R + R 3

From figure 6.83, the voltage at node te' is calculated as

-2
3 V,.RR
8R
3
Then, output voltage Va = -2R l'-VR ')
R4

6. Write notes on ADC conversion. (May/June 2010)

Successive Approximation Technique

The basic drawback of counter method (given above) is that it has longer conversion
time. Because it always starts from 0000 at every measurement, until the analog voltage is
matched. This drawback is removed in successive approximation method. In the adjacent figure,
the method of successive approximation technique is shown. When unknown voltage (Va) is
applied, the circuit starts up from 0000, as shown above. The output of SAR advances with each
MSB. The output of SAR does not increase step–by–step in BCD bus pattern, but individual bit
becomes high–starting from MSB. Then by comparison, the bit is fixed or removed.
Thus, it sets first MSB (1000), then the second MSB (0100) and so on. Every time, the
output of SAR is converted to equivalent analog voltage by binary ladder. It is then compared
with applied unknown voltage (Va). The comparison process goes on, in binary search style,
until the binary equivalent of analog voltage is obtained. In this way following steps are carried
out during conversion.
(1) The MSB is initially set to 1 with the remaining three bits set as 000. The digital equivalent
voltage is compared with the unknown analog input voltage.
(2) If the analog input voltage is higher than the digital equivalent voltage, the MSB is retained
as 1 and the second MSB is set to 1. Otherwise, the MSB is set to 0 and the second MSB is set to
1. Comparison is made as given in step (1) to decide whether to retain or reset the second MSB.
The above steps are more accurately illustrated with the help of an example.
Let us assume that the 4-bit ADC is used and the analog input voltage is VA = 11 V. when the
conversion starts, the MSB bit is set to 1.
Now VA = 11V > VD = 8V = [1000]2
Since the unknown analog input voltage VA is higher than the equivalent digital voltage VD, as
discussed in step (2), the MSB is retained as 1 and the next MSB bit is set to 1 as follows
VD = 12V = [1100]2

Now VA = 11V < VD = 12V = [1100]2

Here now, the unknown analog input voltage VA is lower than the equivalent digital voltage VD.
As discussed in step (2), the second MSB is set to 0 and next MSB set to 1 as
VD = 10V = [1010]2

Now again VA = 11V > VD = 10V = [1010]2

Again as discussed in step (2) VA>VD, hence the third MSB is retained to 1 and the last bit is set
to 1. The new code word is
VD = 11V = [1011]2
Now finally VA = VD, and the conversion stops.

The Staircase Ramp Type

The N bit counter generates an n bit digital output which is applied as an input to the
DAC. The analog output corresponding to the digital input from DAC is compared with the input
analog voltage using an op amp comparator. The op amp compares the two voltages and if the
generated DAC voltage is less, it generates a high pulse to the N bit counter as a clock pulse to
increment the counter. The same process will be repeated until the DAC output equals to the
input analog voltage.

If the DAC output voltage is equal to the input analog voltage, then it generates low clock
pulse and it also generates a clear signal to the counter and load signal to the storage resistor to
store the corresponding digital bits. These digital values are closely matched with the input
analog values with small quantization error.

For every sampling interval the DAC output follows a ramp fashion so that it is called as
Digital ramp type ADC. And this ramp looks like stair cases for every sampling time so that it is
also called as staircase approximation type ADC.