SRM VALLIAMMAI ENGINEERING COLLEGE

(AnAutonomousInstitution)
SRMNagar, Kattankulathur–603203

DEPARTMENT OF COMPUTER SCIENCE AND

ENGINEERING

QUESTION BANK

IV SEMESTER

1908006 – COMPUTER ARCHITECTURE

Regulation–2019

AcademicYear 2022–2023 (EVEN SEMESTER)

Preparedby

Dr.Samydurai.A, Professor ,
Ms.Sangeetha.G, AssistantProfessor(Sel.G),
Ms.Suma.S, Assistant Professor (Sel.G),
 SRM VALLIAMMAI ENGINEERING COLLEGE
(An Autonomous Institution)
SRM Nagar, Kattankulathur–603203.

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

QUESTION BANK

SUBJECT :1908006-COMPUTER ARCHITECTURE

SEM/ YEAR : IV Sem / IIYear

UNIT I-BASIC STRUCTURE OF A COMPUTER SYSTEM

Functional Units–Basic Operational Concepts–Performance–Instructions: Language of the Computer
Operations, Operands–Instruction representation–Logical operations–decision making–MIPS
Addressing–Bus structure–Bus operation
PART–A

1 Give the addressing modes in MIPS. BTL 2 Understanding

2 Identify general characteristics of Relative addressing mode with an example. BTL 4 Analyzing

3 Define ComputerArchitecture BTL1 Remembering

4 Tabulate the components of computer system BTL 1 Remembering

5 Give the addressing modes in MIPS. BTL 2 Understanding

6 Interpret the instruction set Architecture. BTL 2 Understanding

7 Differentiate DRAM and SRAM. BTL4 Analyzing

Give the difference between auto increment and auto decrement addressing
8 BTL 2 Understanding
mode.

9 Judge the functions of control unit? BTL5 Evaluating

10 Calculate throughput and response time. BTL 3 Applying

11 Compose the three categories of the Bus BTL6 Creating

12 Measure the Address line. BTL5 Evaluating

13 Distinguish pipelining from parallelism BTL 2 Understanding

14 Articulate the need for indirect addressing mode. Give an example. BTL 3 Applying

15 Show the control Line in Bus Structure. BTL 3 Creating

16 Define Bus Arbitration. BTL 1 Remembering

17 What are the various units in the computer? BTL1 Remembering

18 Compare multi-processor and uniprocessor. BTL4 Analyzing

 Classify the instructions based on the operations they perform and give one
19 BTL 3 Applying
example to each category.
20 Examine Bus in Computer Architecture? BTL 5 Evaluating

21 How CPU execution time for a program is calculated? BTL6 Applying

22 What are called Instruction? BTL 1 Remembering

23 What are the functional units of a computer? BTL 1 Remembering

24 Convert a hexadecimal number 7 into binary number. BTL 4 Analyzing

PART–B
Evaluate the various techniques to represent instructions in a computer
1 BTL5 Evaluating
system.(13)
i) Express the various components of computer system and explain with
2 neat diagram(10) BTL3 Applying
ii) List the classes of applications of computers (3)
i). What is an addressing mode in a computer? (2)
3 ii). Describe the MIPS addressing modes with suitable examples to each BTL1 Remembering
category(11)
i). Identify the various operations in computer system. (7)
4 BTL1 Remembering
ii). Examine the operands of computer hardware. (6)
i). Discuss the logical operations and control operations of computer. (8)
5 BTL 2 Understanding
ii). Explain the concept of Arithmetic operation with examples (5)
Consider and explain the centralized and distributed bus system in computer
6 BTL2 Understanding
organization.
Consider three different processors P1, P2, and P3 executing the same
instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz
clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2.
i) Which processor has the highest performance expressed in instructions per
second? (5)
7 BTL 4 Analyzing
ii) If the processors each execute a program in 10 seconds, find the number of
cycles and the number of instructions? (4)
iii) We are trying to reduce the execution time by 30% but this leads to an
increase of 20% in the CPI. What clock rate should we have to get this time
reduction? (4)
8 Describe the branching operations in detail with suitable example.
(13) BTL1 Remembering
i) Formulate the performance of CPU. (7)
9 BTL6 Creating
ii) Compose the factors that affect performance. (6)
i).Illustratethedifferenttypesofinstructionsetarchitectureindetail (7)
10 BTL 3 Applying
ii).Examine the basic instruction types with examples (6)
i) Illustrate in detail about Technologies for Building Processors
11 and Memory(7) BTL3 Applying
ii) Show the bus structure in computer system and explain it(6)
i).Compare uniprocessors and multi-processors. (8)
12 BTL 4 Analyzing
ii).Draw the Simple Bus architecture and explain it. (5)
13 Assess the various instruction formats and illustrate with an example.(13) BTL5 Evaluating
What is Bus? Describe in detail the bus structure. (13)
14 BTL 2 Understanding
15 Discuss in detail about the performance of a computer?(13) BTL 2 Understanding

16 Explain the basic operational concepts of a computer. (13) BTL 1 Remembering

 i) If computer A runs a program in 10 seconds and computer B runs the
17 BTL4 Analyzing
same program in 15 seconds, how much faster is A than B?(4)
ii) Suppose we have two implementations of the same instruction set
architecture. Computer A has a clock cycle time of 250ps and a CPI
of 2.0 for some program, and computer B has a clock cycle time of
500ps and CPI of 1.2 for the same program. Which computer is faster
for this program and by how much?(9)

PART-C

Evaluate a MIPS assembly instruction in to a machine instruction, for the

1 BTL5 Evaluating
add $to,$s1,$s2 MIPS instruction.(15)
Assume a two address format specified as source, destination. Examine the
following sequence of instructions and explain the addressing modes used
and the operation done in every instruction.(15)
MOVE (R5)+,
2 R0ADD (R5)+, BTL6 Creating
R0MOVE R0,
(R5)MOVE16(R5)
,R3ADD#40,R5

Assume that the variables f and g are assigned to register $s0 and $s1
respectively. Assume that base address of the array A is in register $s2.
Assume f is zero initially.(15)
F = g – A[4]
3
A[5]=f+100
BTL6 Creating
Translate the above C statement into MIPS code. How many MIPS assembly
instructions are needed to perform the C statements and how many different
registers are needed to carry out the C statements?
Evaluate which code sequence will execute faster according to execution time
for the following conditions. (15)
The computer with three instruction classes and CPI measurements as given
below and instruction counts for each instruction class for the same program
from two different compilers are given. Assume that the computer’s clock
rate is 1GHZ.
Code from CPI for the instruction class
4 BTL5 Analyzing
A B C
CPI 1 2 3

Code from CPI for the instruction class

A B C
Compiler1 2 1 2
Compiler2 2 1 1
Summarize the functional units of a computer? Explain the functions of the
5 BTL5 Evaluating
above unit? (15)

UNIT II-ARITHMETIC FOR COMPUTERS

ALU–Addition and subtraction–Multiplication–Division–Floating Point Representation and operation-
Sub word parallelism.
PART– A
 BT
Q.No Questions Competence
Level
Calculate the following:
1 BTL 3 Applying
Add 510 to 610 in binary and Subtract -610 from 710 in binary.
2 Analyze overflow conditions for addition and subtraction. BTL4 Analyzing

3 Construct the Multiplication hardware diagram. BTL 3 Applying

4 x=00001011 1110 1111and y= 1111 0010 1001 1101. Examine x-y BTL 1 Remembering

5 What is fast multiplication? BTL1 Remembering

Subtract (11011)2–(10011)2 using 1’s complement and 2’s complement
6 BTL 2 Understanding
Method.
7 Illustrate scientific notation and normalization with example. BTL 3 Applying

8 Multiply 100011*100010 BTL 4 Analyzing

9 Give the representation of double precision floating point number. BTL 2 Understanding

10 For the following C statement, Develop MIPS assembly code.

BTL6 Creating
f = g + (h − 5).
11 Name the floating point instructions in MIPS. BTL1 Remembering

12 Formulate the steps of floating point addition. BTL 6 Creating

13 Evaluate the sequence of floating point multiplication. BTL5 Evaluating

14 Assess the use of guard bit. What are the ways to truncate the guard bits? BTL5 Evaluating
Express the IEEE 754 floating point format.
15 BTL 2 Understanding
Represent (-0.75)10 in single precision
16 State sub-word parallelism. BTL 1 Remembering

17 Interpret single precision floating point number representation with example. BTL 2 Understanding

18 Divide 1001010 by 1000. BTL 4 Analyzing

19 Label the steps of division algorithm. BTL1 Remembering

For the following MIPS assembly instructions above, what is the
corresponding C statement?
20 BTL5 Evaluating
add f, g, h
add f, i, f
21 Sketch the half adder circuit. Write the truth table for the half adder. BTL 3 Applying

22 Define Little-endian arrangement. BTL 1 Remembering

23 Interpret the representation of double precision floating point number. BTL2 Understanding

24 Add the Binary numbers 1110 and 1011. BTL 4 Analyzing

PART–B
1 i) Discuss the multiplication algorithm in detail with diagram. (7)
BTL 2 Understanding
ii) Express the steps to multiply 2*3. (6)
Illustrate the multiplication of signed 2’s complement numbers? Give
BTL 3 Applying
2 Algorithm and example.
3 Describe about basic concepts of ALU design. BTL 1 Remembering
 Develop algorithm to implement A*B. Assume A and B for a pair of signed
4 BTL6 Creating
2’s complement numbers with values: A=010111, B=101100
i) State the integer division algorithm with diagram. (7)
5 BTL1 Remembering
ii) Divide 00000111 by 0010. (6)
6 i) Express in detail about Division algorithm. (7)
BTL 2 Understanding
ii) Divide (12)10 by (3)10 (6)
7 Point out the division of A and B
BTL4 Analyzing
A=1111 B=0011
(13)
i) Examine, how floating point addition is carried out in a computer system?(7)
8 BTL1 Remembering
ii) Give an example for a binary floating point addition. (6)
i) Explain how the floating point numbers are represented in IEEE 752? (7)
9 ii) Tabulate the IEEE 752 binary representation of the number -0.7510 to BTL2 Understanding
Single precision and Double precision. (6 )
i) Design an arithmetic element to perform the basic floating point
10 operations. (7) BTL 2 Understanding
ii) Discuss sub word parallelism. (6)
i) Explain floating point addition algorithm with diagram. (7)
BTL5
11 ii) Assess the result of the numbers (0.5) 10 and (0.4375)10 using binary Evaluating
Floating point Addition algorithm. (6)
Prioritize using single precision IEEE 754 representation. (7 + 6)
12 BTL5 Evaluating
i) 32.75 ii)18.125
Arrange the given number 0.0625 in
13 i) Single precision and (6) BTL4 Analyzing
ii) Double precision formats. (7)
Solve using Floating point multiplication algorithm
14 )A=1.10 10 X1010 B= 9.200X10-5 (7) BTL 3 Applying
ii) 0.510X0.437510 (6)
Multiply the following pair of signed Nos. using multiplication algorithm
15 BTL 3 Applying
Multiplier. A =+ 13 (Multiplicand) and B =-6 (Multiplier). (13)
Divide (12)10 by (3)10 using the division algorithm with step by step
16 BTL4 Analyzing
intermediate results and explain. (13)
Discuss in detail about division algorithm in detail with diagram and explain.
17 BTL1 Remembering
(13)
PART-C
Multiply the following signed numbers using multiplication algorithm
1 A=( -34)10 =(1011110)2 and B=(22)10= (0010110) 2where B is multiplicand BTL6 Creating
and A is multiplier
Evaluate the sum of 2.6125*101 and 4.150390625*101 by hand, assuming
2 A and B are stored in the 16-bit half precision. Assume 1 guard, 1 round bit BTL5 Evaluating
and 1 sticky bit and round to the nearest even. Show all the steps.
Summarize 4 bit numbers to save space, which implement the multiplication
3 BTL5 Evaluating
algorithm for 00102, 00112 with hardware design.
Design 4 bit version of the algorithm to save pages, for dividing 000001112 by
4 BTL6 Creating
00102 with hardware design.
Assess the floating point instructions in MIPS. BTL5
5 Evaluating

UNIT III–PROCESSOR AND CONTROL UNIT

A Basic MIPS implementation –Building a Data path–Control Implementation Scheme –Pipelining–
Pipelined data path and control–Handling Data Hazards & Control Hazards–Exceptions
PART– A
 BT
Q.No Questions Competence
Level
1 Express the control signals required to perform arithmetic operations. BTL2 Understanding

2 Define hazard. Give an example for data hazard. BTL 2 Understanding

3 Recall pipeline bubble. BTL 1 Remembering

4 List the state elements needed to store and access an instruction. BTL1 Remembering

5 Draw the diagram of portion of data path used for fetching instruction. BTL 2 Understanding

6 Distinguish Sign Extend and Vector interrupts. BTL2 Understanding

7 Interpret the R-type instructions. BTL 2 Understanding

8 Evaluate branch taken and branch not taken in instruction execution. BTL5 Evaluating

9 State the two steps that are common to implement any type of instruction. BTL 1 Remembering

10 Design the instruction format for the jump instruction. BTL 6 Creating

11 Classify the different types of hazards with examples. BTL 4 Analyzing

12 Illustrate data forwarding method to avoid data hazards. BTL3 Applying

13 Assess the methods to reduce the pipelines tall. BTL5 Evaluating

14 Articulate the use of branch prediction buffer. BTL 3 Applying

15 Show the 5 stages pipeline. BTL 3 Applying

16 Point out the concept of exceptions and interrupts. BTL4 Analyzing

17 What is pipelining? BTL1 Remembering

18 Illustrate the various phases in executing an instruction. BTL 3 Applying

19 Classify the types of instruction classes and their instruction formats. BTL4 Analyzing

20 Generalize what is exception. Give one example for MIPS exception. BTL6 Creating

21 Assess the need of I type instructions. BTL5 Evaluating

22 What is meant by branch prediction? BTL 1 Remembering

23 Identify the Structural Hazards in pipelining. BTL 4 Analyzing

24 What is meant by Control Hazard? BTL 1 Remembering

PART–B

1 Discuss the basic MIPS implementation of instruction set.(13) BTL 2 Understanding

State and draw a simple MIPS data path with control unit and explain the
2 BTL1 Remembering
execution of ALU instruction.(13)
i) List the types of hazards. (5)
3 BTL1 Remembering
ii) Describe the methods for dealing with the control hazards. (8)
Design and develop an instruction pipeline working under various situations of
4 BTL6 Creating
pipeline stall.(13)
 i) What is datahazard? How do you over come it? (7)
5 BTL1 Remembering
ii) What are its side effects? (6)
i) Summarize control implementation scheme. (7)
6 BTL 2 Understanding
ii) Distinguish the data and control path methods in pipelining. (6)
i) Differentiate sequential execution and pipelining. (7)
7 BTL4 Analyzing
ii) Select the model for building a data path. (6)
Recommend the techniques for
8 i) Dynamic branch prediction.(7) BTL5 Evaluating
ii) Static branch prediction. (6)
9 Examine the approaches would you use to handle exceptions in MIPS. (13) BTL 3 Applying
i) Analyze the hazards caused by unconditional branching statements. (7)
BTL4 Analyzing
10 ii) Describe operand forwarding in a pipeline processor with a diagram.(6)
Express the modified data path to accommodate pipelined executions with
11 BTL 2 Understanding
adiagram. (13)
i) Explain single cycle and pipelined performance with examples. (7)
12 BTL4 Analyzing
ii) Point out the advantages of pipeline oversingle cycle. (6)
i) Tabulate the ALU control with suitable truthtable. (7)
13 BTL1 Remembering
ii) Differentiate R-type instruction and memory instruction. (6)
With a suitable set of sequence of instructions show what happens when
14 thebranch is taken, assuming the pipeline is optimized for branches that are BTL 3 Applying
not taken and that we moved the branch execution to the IDstage.
15 Explain in detail about the Exceptions. (13) BTL 2 Understanding

16 Sketch the Implementing Jumps and Finalizing Control. (13) BTL 3 Applying

17 Evaluate the two stage instruction pipeline with neat diagram illustration. (13) BTL5 Evaluating

PART-C
Assume the following sequence of instructions are executed on a 5 stage
pipelined datapath:
add r5, r2,
r1lw r3,
4(r5)lw r2,
0(r2)or r3,
r5, r3swr3,
1 0(r5) BTL6 Creating
If there is no forwarding or hazard detection, insert NOPS to ensure
correctexecution.
i) If the processor has forwarding, but we forgot to implement the hazard
detection unit,what if happens when this code executes? (5)
ii) If there is forwarding, for the first five cycles, compose which signals are
asserted in each cycle. (5)
iii) If there is no forwarding,what if new inputs and output signals do we need
for the hazard detection unit. (5)
Explain in detail about the laundry process through which the pipelining
2 BTL5 Evaluating
techniques can be established. (15)
Consider the following loop:
Loop:lwr1,0(r1) and r1,r1,r2lw r1,0(r1)lw r1,0(r1) beqr1,r0,loop
Assume that perfect branch prediction is used (no stalls) that there are no
delay slots, and that the pipeline has full forwarding support. Also assume that
many iterations of this loop are executed before the loop exits.
3 i) Assess a pipeline execution diagram for the third iteration of this loop.(8) BTL5 Evaluating
ii) Show all instructions that are in the pipeline during these cycles (for all
iterations). (7)
 Plan the pipelining in MIPS architecture and generate the exceptions handled
4 BTL6 Creating
in MIPS.(15)
5 Write in detail how exceptions are handled in MIPS architecture.(15) BTL6 Creating

UNIT IV- MEMORY & I/O SYSTEMS

Memory Hierarchy - memory technologies – cache memory – measuring and improving cache
performance– virtual memory, TLB’s– Accessing I/O Devices–Interrupts–Direct MemoryAccess –Bus
structure–Bus operation–Arbitration.
PART– A
BT
Q.No Questions Competence
Level
1 Distinguish the types of localityof references. BTL 2 Understanding

2 Draw the structure of memory hierarchy BTL1 Remembering

3 Give the definition of memory–mapped I/O. BTL 2 Understanding

4 Compare and contrast SRAM and DRAM. BTL4 Analyzing

5 What is the need to implement memory as a hierarchy ? BTL1 Remembering

6 Define Rotational Latency. BTL1 Remembering

7 Criticize direct-mapped cache. BTL5 Evaluating

Evaluate the following instance where in the cache size is 64 blocks and
8 BTL5 Evaluating
block size is 16 bytes.What block number does byte address 1200 map?
Formulate, how many total bits are required for a direct-mapped cache with 16
9 BTL6 Creating
KB of data and 4-word blocks, assuming a 32-bitaddress ?
10 Analyze the writing strategies in cache memory. BTL4 Analyzing

11 Integrate the functional steps required in an instruction cache miss. BTL6 Creating

12 Articulate hitrate and missrate. BTL 3 Applying

13 Summarize the various block placement schemes in cache memory. BTL 2 Understanding

14 Quote the purpose of Dirty/Modified bit in Cache memory. BTL1 Remembering

15 Point out how DMA can improve I/O speed. BTL4 Analyzing

16 Show the role of TLB in virtual memory. BTL 3 Applying

17 Illustrate the advantages of virtual memory. BTL 3 Applying

18 Assess the relationship between physical address and logical address. BTL5 Evaluating

19 Differentiate Programmed I/O and InterruptI/O. BTL 2 Understanding

Demonstrate the sequence of events involved in handling an interrupt request
20 BTL 3 Applying
froma single device.
21 Summarize the various memory technologies ? BTL 2 Understanding

22 Define Hit Ratio. BTL1 Remembering

23 Illustrate a busmaster? BTL4 Analyzing

24 What is an Interrupt? BTL1 Remembering

PART-B
i) List the various memory technologies and examine its relevance in
1 architecture design. (7) BTL1 Remembering
ii) Identify the characteristics of memory system.(6)
2 Elaborate in detail the memory hierarchy with neat diagram. BTL1 Remembering
i) Give the advantages of cache.(7)
3 BTL 2 Understanding
ii) Identify the basic operations of cache in detail with diagram.(6)
Express the following various mapping schemes used in cache design.
i) Direct.(4)
4 BTL 2 Understanding
ii) Associative.(4)
iii) Set associative.(5)
i) Analyze the given problem:(7)
A byte addressable computer has a small data cache capable of holding eight
32-bit words.Each cache block contains 132-bit word. When a given
program is executed, the processor reads data from the following sequence of
hex addresses – 200, 204, 208, 20C, 2F4, 2F0, 200,204,218, 21C, 24C, 2F4.
5 BTL4 Analyzing
The pattern is repeated four times. Assuming that the cache is initially empty,
show the contents of the cache at the end of each pass, and compute the hit rate
for a direct mapped cache.
ii) What are the methods used to measure and improve the performance of the
cache.(6)
i) Define virtual memory and its importance. (7)
6 BTL1 Remembering
ii) Examine TLB with necessary diagram. (6)
7 i) Demonstrate the DMAcontroller.(7) BTL 3 Applying
ii) Illustrate how DMA controller isused for direct data transfer between
memory and peripherals ?(6)
i) Evaluate the advantages of interrupts.(7)
8 BTL5 Evaluating
ii) Summarize the concept of interrupts with neat diagrams.(6)
Design standard input and output interfaces required to connect the I/O device
9 BTL6 Creating
to the bus.(13)
10 Classify the bus arbitration techniques of DMA in detail.(13) BTL4 Analyzing
Point out the following in detail
11 i) Programmed I/O. (7) BTL4 Analyzing
ii) Instructions executed by IOP.(6)
12 Describe in detail about the methods used to reduce cache misses.(13) BTL1 Remembering
Discuss virtual memory address translation in detailwith necessary
13 BTL 2 Understanding
diagram.(13)
Calculate the performance the processor:
Assume the miss rate of an instruction cache is 2% and the miss rate of the
data cache is 4%. If a processor has a CPI of 2 without any memory stalls and
14 BTL 3 Applying
the miss penalty is 100 cycles for all misses, estimate how much faster a
processor would run with a perfect cache that never missed. Assume the
frequency of all loads and stores is 36%.(13)
15 Examine about Interrupts and its use.(13) BTL 3 Applying

16 Describe in detail about the Cache Basics (CacheMemory).(13) BTL1 Remembering

17 Explain in detail about the Interface Circuits.(13) BTL 2 Understanding

 PART-C
Mean Time Between Failures (MTBF), Mean Time To Replacement
(MTTR)and Mean Time To Failure (MTTF) are useful metrics for evaluating
thereliability and availability of a storage resource. Explore these concepts
byansweringthe questions aboutdevices with the following metrics:
1 MTTF:3 years MTTR: 1 day BTL6 Creating
i) Develop and calculate the MTBF for each of the devices.(4)
ii) Develop and calculate the availability for each of the devices.(4)
iii) What if happens to availability as the MTTR approaches ?(4)
iv) What if happens to availability as the MTTR gets very high? (3)
Design and explain parallel priority interrupt hardware for a system with eight
2 BTL6 Creating
interrupt sources. (15)
For a direct mapped cache design with a 32 bit address, the following bits
oftheaddressareusedto access the cache.
Tag:31-10Index:9-5Offset:4-0
3 i) Judge what is the cache block size? (5) BTL5 Evaluating
ii) Decide how many entries does the cache have ? (5)
iii) Assess what is the ratio between total bits required for such a cache
implementation over the data storage bits? (5)
Summarize by considering web application. Assuming both client and servers
are involved in the process of web browsing application, where can caches be
placed to speed upthe process.Design a memory hierarchy forthe system.
4 Show the typical size and latency at various levels of the hierarchy. What is the BTL5 Evaluating
relationship between the cache size and its access latency?What are the units of
data transfers between hierarchies? What is the relationship between data
location,data size and transfer latency? (15)
5 Formulate in detail about USB.(15) BTL 6 Creating

UNIT V-PARALLELISM
Instruction-level-parallelism - Parallel processing challenges – Flynn‘s classification – SISD, MIMD, SIMD, SPMD, and
Vector Architectures – Multi-core processors and other Shared Memory Multiprocessors.

PART– A
BT
Q.No Questions Competence
Level
1 State the main idea of ILP. BTL 2 Understanding
Illustrate the overall speedup if a webserver is to be enhanced with a new CPU
2 which is10 times faster on computation than an old CPU.The original CPU BTL 3 Applying
spent 40% of its time processing and 60% of its time waiting for I/O.
3 Illustrate the three important properties of vector instructions. BTL4 Analyzing

4 Analyze the main characteristics of SMT processor. BTL4 Analyzing

5 Quote the importance of loop unrolling technique. BTL1 Remembering

6 Define VLIW processor. BTL1 Remembering

7 Express anti-dependence.How is it removed ? BTL 2 Understanding

8 State the efficiency of super scalar processor. BTL1 Remembering

9 Differentiate between strong scaling and weak scaling. BTL 2 Understanding

10 Show the performance of cluster organization. BTL 3 Applying

11 Compare SMT and hardware multithreading. BTL5 Evaluating

12 Define the Flynn classification. BTL1 Remembering

13 Integrate the idea so fin-order execution and out-of-order execution. BTL6 Creating

14 Discriminate UMA and NUMA. BTL5 Evaluating

15 Quote fine grained multithreading. BTL1 Remembering

16 Express the need for instruction level parallelism. BTL 2 Understanding

17 Formulate the various approaches to hardware multithreading. BTL6 Creating

18 Categorize the various multithreading options. BTL4 Analyzing

19 Differentiate fine grained multithreading and coarse-grained multithreading. BTL4 Analyzing

20 Classify shared memory multiprocessor based on the memory access latency BTL 3 Applying

21 State Amdahl’s law. BTL1 Remembering

22 Criticize the styles of vector architectures ? BTL5 Evaluating

23 Brief about Multithreading. BTL 3 Applying

24 Interpret Warehouse-scale computer ? BTL 2 Understanding

PART–B
i) Define parallelism and its types. (7)
1 ii) List the main characteristics of Instruction level parallelism.(6) BTL1 Remembering
i) Give the concept of parallel processing. (7)
2 ii) Summarize the challenges faced by parallel processing. (6) BTL 2 Understanding

3 Express in detail about hardware multithreading. (13) BTL 2 Understanding

Solve:suppose you want to achieve a speed up to 90 times faster with100
4 processors.What percentage of the original computation can be sequential? BTL 3 Applying
(13)
List the software and hardware techniques to achieve Instruction Level
5 Parallelism. (13) BTL1 Remembering
i) Point out how will you use shared memory concept in multi-processor ? (7)
6 ii) Compare and contrast Fine grained and Coarse grained multithreading.(6) BTL4 Analyzing
i) Evaluate the features of Multi core processors. (7)
7 ii) How message passing is implemented in Multiprocessors (6) BTL5 Evaluating
i). Classify the types of multithreading. (7)
8 ii). Analyze the advantages in multithreading. (6) BTL4 Analyzing

9 Formulate the ideas of Flynn’s classification. (13) BTL6 Creating

Sketch in detail about the following(7+6)
10 i)SISD ii)MIMD BTL3 Applying

11 Explain simultaneous Multithreading with example.(13) BTL4 Analyzing

i) Describe about Graphics Processing unit(7)
12 ii) Discuss about cluster and warehouse architecture(6)
BTL1 Remembering
Illustrate the following in detail
i) Data Dependence (5) Applying
13 BTL3
ii) Name Dependence (4)
iii) Control dependence (4)
 Discuss the following in detail
14 i) Vector processor. (7) BTL 2 Understanding
ii) Super scalar processor.(6)
Elaborate in detail about the following (7+6)
15 i)SIMD ii)SPMD BTL2 Understanding
Explain in detail about
i) Vector Registers (3)
16 BTL5 Evaluating
ii) Vector Functional Units (5)
iii) Vector Load Store Units (5)
17 Describe in detail about the warehouse-scale computers.(13) BTL1 Remembering

PART-C
1 Explain how would this loop be scheduled on a static two issue pipeline for
MIPS?
Loop: lw $t0,0($s1) #$t0=array element
BTL6 Creating
Addu $t0,$t0,$s2 #add scalar in $s2
Sw $t0, 0($s1) #storeresult
Addi; %s1,$s1, -4 #decrementpointer
Bne $s1,$zero,loop # branch $s1!=0
Decide and reorder the instruction to avoid as many pipeline stalls as
possible. Assume branches are predicted, so that control hazards are
handled by the hardware. (15)
A pipelined processor uses delayed branch technique. Recommend any one
ofthe following possibility for the design of the processor. In the first
possibility,the processor has a 4-satge pipeline and one delay slot. In the second
possibility, it has a 6-stage pipeline and two delay slots. Compare the
2 performance of these two alternatives, taking only the branch penalty into BTL5 Evaluating
account. Assume that 20% of the instructions are branch instructions and thatan
optimizing compiler has an 80% success rate in filling in the single
delayslot.For these cond alternative,the compiler is able to fill the seconds lot
25% of the time. (15)
Consider the following portions of two different programs running at the same
time on four processors in a symmetric multicore processor (SMP). Assume
that before this code is run,both x and yare 0?
Core 1: x=2;
Core 2: y=2;
3 Core 3: w= x + y +1; BTL6 Creating
Core4: z= x+y;
i. What if all the possible resulting values of w, x, y, z ? For each possible
outcome,explain how we might arrive at those values. (8)
ii. Develop the execution more deterministic so that only one set of values
ispossible? (7)
Suppose we want to perform 2 sums: one is a sum of 10 scalar variables and one
is a matrix sum of a pair of two dimensional arrays, with dimensions 10 by
4 10. For now let’s assume only the matrix sum is parallelizable. What if the BTL5 Evaluating
speed up do you get with 10 versus 40 processors and next calculate the speed
up assuming the matrices grow to 20 by 20. (15)
5 Write about the Cluster Architecture and the types of clusters.(15) BTL6 Creating