Complete ASIC Flow of

I2C communication
protocol

Advanced Digital Design Course

May 2024

SUPERVISORS: Dr. Eslam Yahya

Table of content
Section #19&21 Group #............................................................................................................. 0
SUPERVISORS....................................................................................................................... 0
Project description:................................................................................................................................... 3
Introduction..................................................................................................................................3
I2C Master communication protocol................................................................................................... 3
HOW I2C WORKS?.................................................................................................................4
ADVANTAGES AND DISADVANTAGES OF I2C............................................................................. 5
Synthesis....................................................................................................................................................... 6
RTL: Synthesizable HDL Code................................................................................................ 8
Translation: Analyze & Elaborate.............................................................................................8
Top Module After Elaboration:................................................................................................. 9
Netlist Synthesis:..................................................................................................................... 9
Netlist Synthesis inner module:............................................................................................. 10
Netlist Synthesis inner module bit_controller:........................................................................10
After Synthesis:...................................................................................................................... 11
Synthesis output files:............................................................................................................ 11
Synthesis reports:.................................................................................................................. 12
Formal Verification................................................................................................................................. 12
Static Timing Analysis (STA).................................................................................................... 14
Floorplanning.............................................................................................................................16
Floor planning before sizing:..................................................................................................16
Initial Floor planning:..............................................................................................................17
Pin placement:....................................................................................................................... 17
Placement and Routing:.........................................................................................................................18
Power planning:.........................................................................................................................19
● Rings.................................................................................................................................. 19
● Mesh................................................................................................................................... 19
● After STD rail insertion....................................................................................................... 20
● Cell Placement optimization with legalisation:....................................................................20
● Check Legality.................................................................................................................... 21
Clock Tree Synthesis (CTS):.....................................................................................................22
After Placing and Routing:..................................................................................................... 23
Cell Density:...........................................................................................................................24
● After placement:............................................................................................................24

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 ● After CTS:..................................................................................................................... 24
Pin Density:............................................................................................................................25
STA, ECO & solving hold violations:...................................................................................................25
Inspecting worst slack path example:.................................................................................... 26
Solution Of worst slack path example :..................................................................................27
Buffer insertions till zero hold violations :...............................................................................28
PrimeTime Reports:...................................................................................................................29
ICC II Output Files:.................................................................................................................... 30
Final Project Folders:................................................................................................................ 31
References................................................................................................................................................. 32

Project description:
In this project we go through the complete ASIC flow to create the layout (GDS) of an I2C
which is a two-wire. We have used the same PDK we used in labs.
Here are the tasks we have done:
1. Synthesis of the code
2. Formal Verification.
3. Performing static timing analysis
4. Creating the floorplan and power plan.
5. Performing clock tree synthesis.
6. Placing and routing the core.
7. Design and layout of the pad ring with all the required inputs and outputs.
8. Signoff and final complete layout

Figure 1- ASIC flow diagram

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Introduction

I2C Master communication protocol

I2C stands for Inter-Integrated Circuit. It is a bus interface connection protocol incorporated into
devices for serial communication. It was originally designed by Philips Semiconductor in 1982.
Recently, it is a widely used protocol for short-distance communication. It is also known as Two
Wired Interface(TWI). It uses only 2 bi-directional open-drain lines for data communication
called SDA and SCL. Both these lines are pulled high.
● Serial Data (SDA) – Transfer of data takes place through this pin.
● Serial Clock (SCL) – It carries the clock signal.

Figure 2- Internal structure of I2C Master communication protocol

I2C combines the best features of SPI and UARTs. With I2C, you can connect multiple slaves to
a single master (like SPI) and you can have multiple masters controlling single, or multiple
slaves. This is really useful when you want to have more than one microcontroller logging data
to a single memory card or displaying text to a single LCD.

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HOW I2C WORKS?
With I2C, data is transferred in messages. Messages are broken up into frames of data. Each
message has an address frame that contains the binary address of the slave, and one or more data
frames that contain the data being transmitted. The message also includes start and stop
conditions, read/write bits, and ACK/NACK bits between each data frame:

Figure 3 - I2C The message bits

Start Condition: The SDA line switches from a high voltage level to a low voltage level before
the SCL line switches from high to low.

Stop Condition: The SDA line switches from a low voltage level to a high voltage level after
the SCL line switches from low to high.

Address Frame: A 7 or 10 bit sequence unique to each slave that identifies the slave when the
master wants to talk to it.

Read/Write Bit: A single bit specifying whether the master is sending data to the slave (low
voltage level) or requesting data from it (high voltage level).

ACK/NACK Bit: Each frame in a message is followed by an acknowledge/no-acknowledge

bit. If an address frame or data frame was successfully received, an ACK bit is returned to
the sender from the receiving device.

ADVANTAGES AND DISADVANTAGES OF I2C

There is a lot to I2C that might make it sound complicated compared to other protocols, but there
are some good reasons why you may or may not want to use I2C to connect to a particular
device:

ADVANTAGES

● Only uses two wires

● Supports multiple masters and multiple slaves
● ACK/NACK bit gives confirmation that each frame is transferred successfully
● Hardware is less complicated than with UARTs

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 ● Well known and widely used protocol
DISADVANTAGES
● Slower data transfer rate than SPI
● The size of the data frame is limited to 8 bits
● More complicated hardware needed to implement than SPI

Synthesis
● Synthesis is achieving an optimal gate level netlist from HDL code
● (Synopsys tool: Design compiler ).
● The logic synthesis process consists of 3 steps:
1. Translation: Translation involves transforming a HDL (RTL) description to gates.
2. Optimization:Synthesis optimises the design for various metrics, such as area, power
consumption, and timing. By leveraging advanced algorithms, it improves the
performance and efficiency of the resulting netlist.
3. Mapping:Technology mapping is the phase of logic synthesis when gates are selected
from a technology library to implement the circuit .

Figure 4- Synthesis flow in synopsys tool

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RTL: Synthesizable HDL Code

Figure 5-RTL files

Translation: Analyze & Elaborate

Analyse:
● Reads HDL source files and performs syntax checking.
● Check files for errors without building generic logic for the design.
● Create HDL library objects in an intermediate form.
● Stores the intermediate files in a location defined.
Elaborate:
● Translates the design into its GTECH representation.
● Allows changing of parameter values defined in the source code.
● Replaces HDL arithmetic operators in the code with the design ware components.

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Top Module After Elaboration:
Cells are generic technology cells and not mapped to the specific technology yet.

Figure 6-Top Module After Elaboration

Netlist Synthesis:

Figure 7-Netlist Synthesis

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Netlist Synthesis inner module:

Figure 8-inner module netlist synthesis

Netlist Synthesis inner module bit_controller:

Figure 9- bit_controller netlist synthesis

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After Synthesis:
Now we observe that cells are mapped to the technology instead of GTECH. cell_library
saed90nm_max_lth

Figure 10- After synthesis

Synthesis output files:

Figure 11- Synthesis output files

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Synthesis reports:

Figure 12- Synthesis reports

Formal Verification
● Formal Verification: An alternative to verification through simulation. As design
becomes larger and more complex and requires more simulation vectors, regression
testing with traditional simulation tools becomes a bottleneck in the design flow.
● It verifies the logical equivalence of RTL, gate, or transistor level netlist to each
other.
- Ignores timing information
- Only Boolean Equivalence.
- Verifies logic functions independent of technology and timing therefore no timing
check.
● Purpose: detect unexpected differences that might have been introduced into a design
during development

Figure 13- Formal Equivalence Checking

Flow chart

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 Figure 14- Formality Flow Overview

Figure 15- Formality verification succeeded(GUI)

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 Figure 16- Formality verification succeeded (log.txt)

Static Timing Analysis (STA)

● Static timing analysis is a method of validating the timing performance of a
design by checking all possible paths for timing violations.
● STA breaks a design down into timing paths, calculates the signal propagation
delay along each path, and checks for violations of timing constraints inside the
design and at the input/output interface.
● Method of determining if a circuit meets timing constraints without having to
simulate
● (Synopsys tool: PrimeTime ).
● STA is used to validate if the design can operate at the set timing constraints and
report timing violations including setup, hold, recovery, removal, and min pulse
width in a design for a specified clock without applying test vectors.
● STA validates if the design can operate at the set timing constraints. [reports
timing violations]
● STA is a complete and exhaustive verification of all timing checks of a design.
● STA is used instead of simulation.

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 Figure 17- STA overview

Figure 18- QOR report that shows the critical path slack
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Floorplanning
Floor planning helps to determine the locations, shape, and size of the modules in a chip, and
such it estimates chip area, delay, and wiring congestion therefore providing a groundwork for
layout

Floor planning before sizing:

Figure 19- Floor planning before sizing (GUI)

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Initial Floor planning:
Sets the boundary and defines standard cell placement site array within the core area.

Figure 20- Initial Floor planning (GUI)

Pin placement:

Figure 21- Pin placement (GUI)

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Placement and Routing:
Includes 4 Stages (Synopsys tool: IC compiler ii):
● Power Planning
Power Planning is the step where a power grid network is created to
distribute power to each part of the design.
● Placement
Process of placing the standard cells inside the core boundary in an
optimal location.
● Clock Tree Synthesis (CTS)
Building a buffer/inverter network to balance the relative delay of
FlipFlops belonging to a clock domain. (triggered by the same clock)
● Routing
Create physical connections to all clock and signal pins through metal
interconnects.
It includes 2 steps (Global Routing and Detailed Routing).

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Power planning:

● Rings
Rings Carries VDD and VSS around the chip

Figure 22- Ring power planning (GUI)

● Mesh
● To distribute the Power from power pads/pins to all elements of the chip.
● Uniformly distribute power with less voltage drop.
● Meeting timing requirements.
● Provides multiple paths from PG sources to destinations (less series resistance).

Figure 23- Mesh power planning (GUI)

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● After STD rail insertion
Rails are used to Connect VDD and VSS to the standard cell VDD and VSS

Figure 23- Rail power planning (GUI)

● Cell Placement optimization with legalisation:

Figure 24- After cell Placement optimization with legalisation (GUI)

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● Check Legality

Figure 25- Check Legality (GUI)

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Clock Tree Synthesis (CTS):
– Automatic insertion of buffers/inverters along the clock paths of the design to balance
the clock delay to all clock inputs.
– CTS is performed to balance clock skew and minimise insertion delay.

Figure 26- Clock Tree Synthesis (CTS)

Figure 27- A clear screenshot of Clock Tree Synthesis (CTS)

20
After Placing and Routing:

Figure 28- After Placing and Routing (CTS)

Figure 29- A clear screenshot After Placing and Routing (CTS)

21
Cell Density:
● After placement:

Figure 30- Cell Density after placement

● After CTS:

Figure 31- Cell Density after CTS

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Pin Density:

Figure 32- Pin Density

STA, ECO & solving hold violations:

Figure 33- A Histogram showing number of paths that have a hold violations

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 ● Hold violations are critical to be solved since post fabrication they cannot be solved,
unlike setup violations where we can reduce the clock speed.
● We have here 57 paths that have a hold violation and need to solved

Figure 34- details of the critical paths that have a hold violation
Inspecting worst slack path example:

Figure 35- Inspecting worst slack path

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 Figure 36- More details of the worst slack path

Figure 37-Schematic the worst slack path

Solution Of worst slack path example :

To solve hold violation we need to insert delays in the data path, this can be achieved by
inserting buffers/inverter pairs

Figure 38-Schematic the worst slack path after inserting some buffers

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We can notice here that the endpoints got reduced from 57 to 56

Figure 39-A Histogram after solving one path

Buffer insertions till zero hold violations :

Figure 40-No hold violation

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PrimeTime Reports:

Figure 41-PrimeTime Reports

27
ICC II Output Files:

Figure 42-ICC II Output Files

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Final Project Folders:
• All scripts used can be found here: (Note the standard Cell folder would not be
uploaded)

Figure 43-Final Project Folders

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References

1-https://www.design-reuse.com/articles/38949/hold-fixin
g-techniques.html
2-https://link.springer.com/chapter/10.1007/978-3-030-49
636-4_6#:~:text=Download%20chapter%20PDF-,The%20co
ncept%20of%20Clock%20Tree%20Synthesis%20(CTS%20)
%20is%20the%20automatic,insertion%20delay%2C%20CTS
%20is%20performed.
3-lab manuals
4-https://www.geeksforgeeks.org/i2c-communication-prot
ocol/

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