DesignCon 2013

A Removable Signal Probing

and Monitoring Solution for
Gigabit Memory ATE
Applications
José Moreira, Advantest
[email protected]

Marc Mössinger, Advantest

[email protected]
Tom Bresnan, R&D Circuits
[email protected]
Masayuki Takahashi, Elpida
[email protected]
Abstract

This paper presents an approach for monitoring the signals exchanged between the
digital pin electronics of an automated test equipment (ATE) measurement system
and a device under test (DUT) for applications running at data rates of 4 Gbps and
above. This capability is especially important for bi-directional interfaces like those
on a DDR application where it can be of significant help to an ATE test engineer
developing an ATE test program for testing/characterizing a DUT. Since the objective
is to be able to monitor or probe signals in the 4 Gbps range and above, signal
integrity is critical. Because of that, the monitoring approach consists of a very thin
printed circuit board (PCB) interposer that is placed between the test fixture PCB and
the DUT socket. The probing circuit inside the interposer PCB is implemented using
embedded passive components. The connection to the test fixture PCB is done using
an elastomeric conductive layer on the bottom of the interposer PCB. We named this
PCB interposer a monitoring interposer. This approach not only minimizes the size of
the discontinuity generated by the probing circuit but also allows the test engineer to
remove the monitoring interposer once it is no longer needed. In this paper we will
describe the monitoring interposer concept and also some of the possible probing
circuits. We will then use a DDR4 application example to demonstrate the layout
challenges and present the results obtained with a manufactured prototype. The results
will include not only bench measurements results showing the performance of the
monitoring interposer but also measurements obtained on an ATE system using the
monitoring interposer together with DDR4 and GDDR5 DUTs.

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Authors’ Biographies

Jose Moreira is a staff engineer in the test cell innovations team of the SOC business
unit at Advantest in Böblingen, Germany. He focuses on the challenges of testing
high-speed digital devices especially in the area of test fixture design, signal integrity,
jitter testing and focus calibration. He joined Agilent Technologies in 2001 (later
Verigy and in 2011 acquired by Advantest) and holds a Master of Science degree in
Electrical and Computer Engineering from the Instituto Superior Técnico of the
Technical University of Lisbon, Portugal. He is a senior member of the IEEE and co-
author of the book “A Engineers Guide to Automated Testing of High-Speed Digital
Interfaces”.

Marc Mössinger is a R&D project manager with Advantest (Böblingen, Germany)

responsible for the PCB design team and signal path development. He started his
career with Hewlett-Packard in 1997 as Hardware Design Engineer and developed
Firmware, Hardware and ASICs for Automated Test Equipment for HP, Agilent
Technologies, and Verigy. Since 2003 he has been managing projects and leading the
High-Speed Memory Hardware R&D team responsible for Test-Cell developments.
He holds an Engineering Degree from the University of Applied Science in Ulm,
Germany, and an MSc from Brunel University of West London, UK.

Tom Bresnan is the marketing manager with R&D Circuits of South Plainfield, NJ.
His more than 30 years of printed circuit manufacturing experience includes positions
in various engineering and management roles for some of the world’s largest
manufacturers of complex printed circuit boards. He is a distinguished lifetime
member of the IPC (a US based, global trade organization representing the printed
circuit industry) technical activities executive committee, and has presented and
published numerous technical articles for the industry on MCM-L’s, board fabrication
and advanced plating capabilities. He is presently studying at Seton Hall University in
NJ for an advanced degree in Theology.

Masayuki Takahashi is a professional with the Design Department of the Advanced

DRAM Design Group at Elpida Sagamihara, Japan. He has an electrical engineering
degree from Kogakuin University and joined Elpida in 2002.

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Introduction

In some situations when developing an application to test/characterize an integrated

circuit (IC) using automated test equipment (ATE) [1], it might be of help for the test
engineer to observe the signals being exchanged between the device under test (DUT)
and the ATE pin electronics using an external instrument as shown in the diagram of
Figure 1. The critical point is that this probing should have a negligible effect on the
signals exchanged between DUT and ATE.

Figure 1: Monitoring the signals exchanged between the ATE pin electronics and the DUT with
an external instrument (e.g. oscilloscope).

In a coaxial environment this problem can be addressed by using for example a

Pickoff Tee [1,2] like the one shown in Figure 2. However, on an ATE test fixture
environment this is usually not possible because the DUT to ATE pin electronics
connections are done through a test fixture printed circuit board (PCB).

Figure 2: Picosecond Pulse Labs Pickoff Tee [2].

One approach to address this requirement is to probe the bottom via pads of the test
fixture PCB vias that go to the DUT. Figure 3 shows an example of a DUT test fixture
designed with this approach.
This method worked well in the past since the vias were not back-drilled. However,
current devices running at multi-gigabit data rates require back-drilled vias to achieve
good signal performance [3], which makes this approach no longer feasible. This
method also required the DUT to be mounted in a reverse way on the ATE DUT test
fixture. A similar approach is shown in Figure 4 where the DUT can be mounted in a
standard way and the probing is accomplished through a resistor at the bottom of the
BGA via. But a via stub is still present on the setup.

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Figure 3: Example of a DUT test fixture with the DUT socket mounted on the bottom side (right)
so that when docked to the ATE system (left) the bottom side of the DUT vias can be easily
probed using an high impedance probe and the DUT I/O measured with an external instrument.

Figure 4: Monitoring the ATE to DUT signaling using a probing resistor at the bottom of the
DUT BGA via of the signal trace to be probed.
This paper presents a different approach to this challenge. Current state of the art PCB
manufacturing allows the embedding of small discrete components (e.g. 0201 size
resistors). Together with an elastomeric electrical connection layer it is possible to
develop a PCB that can be placed between the ATE DUT test fixture PCB and the
socket. This PCB, that we will refer to as a monitoring interposer, will contain the
probing circuit to monitor the signaling between the DUT and the ATE pin
electronics.

A similar approach is used by Agilent Technologies for system level test where a PCB
interposer with an embedded resistor is soldered between the PCB (e.g. DIMM
module) and the memory package [4]. A high-impedance probe is soldered on the
interposer to measure the probed signal. Another similar approach but for a different
application (DUT current sensing) was presented in [5] where a sense resistor was
embedded in an interposer between the PCB test fixture and the DUT socket.

The monitoring interposer approach presented in this paper is intended to be used for
ATE applications providing a high-performance monitoring solution for applications

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running at data rates of 4 Gbps and above. It is designed to be used with high-
impedance or 50 Ohm probing approaches. Another important feature is that this
monitoring interposer approach is removable without any impact on the ATE test
fixture performance.

Note that in case the objective is to measure the performance at the DUT socket (e.g.
for test fixture verification or focus calibration), the best approach is to use an
interposer on top of the DUT socket as shown in Figure 5 and discussed in
[1,6,7,8,9,10]. We refer to this type of interposer as a probing interposer.

Figure 5: Measuring the ATE performance at the test fixture DUT socket using a probing
interposer on the top of the DUT socket [7].

In the next section we will introduce the monitoring interposer using the example of a
DDR4 application followed by a discussion on the monitoring interposer
manufacturing. We will then present real examples of using the monitoring interposer
for GDDR5 and DDR4 ATE applications. We will finalize the paper with some
conclusions.

The Monitoring Interposer Approach

Figure 6 shows a high-level block diagram of the monitoring interposer approach

[11]. The main idea is to insert a very thin PCB interface that contains a probing
circuit between the DUT socket and the DUT test fixture PCB and a connection point
to measure the probed signal using an external instrument. This connection point can
be a simple signal/ground pad that is probed with a soldered probe or with a micro-
coaxial probe or even a surface mounted coaxial connector. The monitoring interposer
must have copper pads on the top to connect to the DUT socket and a conductive
elastomeric layer on the bottom to connect to the test fixture PCB BGA pads.

There are several options for the probing circuit inside the monitoring interposer. One
implementation is shown in Figure 7 where a simple resistor is used as probing
circuit. In this case a resistor value of 200 Ohm is chosen. The figure also shows the
simulated insertion and return loss using a very simple model for the monitoring
interposer.
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Figure 6: High-level block diagram of the monitoring interposer approach.

Figure 7: Simulation of a simple model for a monitoring interposer with a probing circuit
consisting of a single 200 Ohm resistor circuit.
From the simulation results it is possible to observe that a small additional loss
between the DUT and the ATE pin electronics is added by the monitoring interposer
probing circuit. This added loss can easily be compensated by the ATE pin
electronics. Also as expected the signal measured at the monitoring point will be
attenuated by a factor of 5.54 (-14.87 dB) in the case of a 200 Ohm resistor. The
choice of the probing resistor value is important. Figure 8 shows a simulation of the
very simple interposer model of Figure 7 for different values of the probing resistor
(100, 200, 300, 400, 500 and 600 Ohm).

From the results it is possible to observe that there is a trade-off between reducing the
loss on the monitored signal by using a smaller probing resistor and the impact on the
return loss on the DUT and ATE ports which gets worst when using small resistor
values. The optimal value will depend on the application requirements and on the
capabilities of the measurement instrumentation.
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Figure 8: Simulation results of a monitoring interposer with a probing circuit consisting of a
single resistor for different values of the probing resistor.
Another possible probing circuit is shown in Figure 9 (top) where a matched network
of three resistors is used. The results of a simulation shown in Figure 9 (bottom)
demonstrate that this type of probing circuit provides an improvement on the return
loss at the expense of a higher insertion loss between the ATE pin electronics and the
DUT. As mentioned before, this insertion loss can be compensated on the ATE pin
electronics side. The main drawback of this probing circuit is the increased
complexity of using three resistors which can create design challenges when trying to
embed the resistors within a fine pitch via array.

Figure 9: Simple simulation of a monitoring interposer with a probing circuit consisting of a

three resistor network.
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DDR4 Application Monitoring Interposer Example

A DDR4 application is a good example of the usage of the monitoring interposer

approach especially for the DQ pins since they are bidirectional. Figure 10 shows the
ball assignment of a DDR4x8 memory IC [12]. For this assignment with a pitch of 0.8
mm, it is possible to create a monitoring interposer that is able to probe all DQ, clock,
command and address pins using only 2 signal layers. Figure 11 shows an example of
a monitoring interposer layout using coaxial connectors (mini-SMP) on the probed
signal output (top) and probing pads for a micro-coaxial probe (bottom).

Figure 10: DDR4x8 ballout.

Figure 11: Layout example of a monitoring interposer using a single resistor probing circuit and
a mini-SMP coaxial connector for a DDR4 application (top) and using probing pads for a micro-
coaxial probe (bottom).
It is also possible to implement a monitoring interposer for DDR4 applications using a
probing circuit consisting of a matched network of three resistors as described in
Figure 9. The layout is in this case more complex. Figure 12 shows the layout of a
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monitoring interposer using a matched resistor network probing circuit where all the
DQ pins are probed. In the remainder of this paper we will only concentrate on
monitoring interposer designs using a single resistor probing circuit.

Figure 12: Layout example of a monitoring interposer using a resistor network probing circuit
and probing pads for a micro-coaxial probe for all DQ pins.
Figure 13 shows a picture of the manufactured monitoring interposers presented in
Figure 11. Note that the area of the monitoring interposer will depend significantly on
the type of socket being used since the coaxial connector or probing pads need to
reside outside the socket area. Figure 14 shows a picture of another monitoring
interposer intended for a DDR4x16 DDR production HiFix [13] where the socket and
socket guide assembly have a larger area than the socket for the monitoring
interposers in Figure 13. Figure 14 also shows the elastomeric connection layer at the
bottom side of the monitoring interposer.

Figure 13: Picture of the manufactured monitoring interposer using mini-SMP coaxial
connectors (left) and probing pads for a micro-coaxial probe (right).

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Figure 14: Picture of a DDR4x16 monitoring interposer for a DDR production HiFix where the
socket and socket guide assembly occupy a larger area than the example shown in Figure 13.

Monitoring Interposer Design and Manufacturing

As mentioned in the previous sections, the options for selecting the dielectric
materials, components and related circuitry are dependent on space available within
the monitoring interposer PCB and the pitch of the DUT BGA. A device with a 1.0
mm or 1.27 mm pitch allows for larger components to be placed inside the monitoring
interposer PCB. Components with footprint dimensions of 0603 and 0402 can easily
be placed adjacent to device pins in this pitch category. For smaller pitch size one
would need to use smaller size components so that they can fit between the BGA pins
and minimize the stub of the connection to probing circuit. In the examples presented
in this paper, 0201 size resistors were used exclusively.

Design constraints may help determine the manufacturing techniques to use; through
hole or multi-lamination methods can be employed depending on the application
requirements. This then leads to choosing materials and component placements.

Each of the designs we produced for the monitoring interposer application presented
on this paper have not been material or component dependent. All commercially off-
the-shelf dielectric materials and components can be used. This includes capacitors
and inductors, though only resistors are used on the presented probing circuits. Once
materials and component value and size are chosen, this leads to selecting locations
for placement within the board. Physical space within the board needs to be
determined, so that placement and routing can be determined.

As can be seen in the micrographs shown in Figure 15, sub-surface placement of

components looks much like traditional surface placement, except that it does occur
one or more layers below the outside surface of the PCB. The significant difference is
that during layout, the designer must be sensitive to the component placement and
physical space needed for the component. It is important to note that care is to be
taken when placing components internally, e.g. that adequate spacing is left between
them because there is a need to be a remaining wall of laminate material between the
embedded components (e.g. resistors) to insure there is adequate surface and z-axis
support for the monitoring interposer PCB.
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 Figure 15: Monitoring interposer PCB micrographs.

Figure 16: Monitoring interposer PCB X-ray analysis.

In the X-ray shown in Figure 16, the lighter areas between components (highlighted
by the arrow) is the space or wall left between component placements that is filled
with the dielectric material.

All other traditional PCB design and fabrication rules would apply. A schematic is
created and critical part placement is completed and reviewed. Routing begins and
traditional rules for signal length matching and impedance control are employed. All
design outputs remain the same; design file, Gerber files, assembly files and drawings
are all output as usual. The PCB fabrication processes all take place in their usual
order, with some obvious exceptions needed to add operations to make room for the
components inside and their placement. Once that is accomplished, final lamination
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can take place and through hole drilling and plating or other manufacturing operations
can then be completed.

The final step needed for the monitoring interposer application is the addition of the
elastomeric contact layer on the bottom of the monitoring interposer using R&D
Circuits Elastech® technology. In this application, the elastomer columns are
integrated directly onto the bottom of the monitoring interposer PCB as shown in
Figure 17. The elastomer columns act as a very short electrical pathway to connect the
monitoring interposer to the ATE test fixture PCB, while allowing for some surface
planarity mismatch that might occur. Electrically equivalent to a solder ball, the use of
the elastomer allows for a non-permanent assembly, while not degrading the electrical
performance. The pitch of the connection to be made determines the physical
dimensions of the elastomer columns. The columns may also be custom engineered
for electrical and mechanical performance enhancements. For the monitoring
interposer examples presented in this paper, these elastomer columns were made to
our standard configuration, allowing for a 75 micron compression.

Figure 17: Monitoring interposer elastomeric contact layer diagram.

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Bench Measurement Results

To measure the monitoring interposer performance without the DUT test fixture or the
DUT socket, a two-side probing station was used with 0.8 mm signal to ground pitch
micro-coaxial probes as shown in Figure 18. The figure also shows the measured
results for the DDR4 monitoring interposer with a single 200 Ohm resistor on the
probing circuit and mini-SMP coaxial connectors on the monitoring port (shown
previously in Figure 13 left). A 4-port vector network analyzer (VNA) was used to
measure the monitoring interposer S-parameters to a maximum frequency of 24 GHz.

Figure 18: DDR4 monitoring interposer (with mini-SMP coaxial connectors) measured S-
parameters using a bench probing setup. Note that a 35 cm mini-SMP to SMA coaxial cable is
used on the monitoring connector port that is not part of the VNA calibration. The two GGB 40A
VP-style micro-coaxial probes were also not included on the VNA calibration.
One interesting result is the high-frequency resonance that can be observed on the
ATE to DUT (and vice-versa) insertion loss. The reason for this resonance is the
signal trace stub that exists between the ATE to DUT via and the probing resistor. The
effect of this stub is demonstrated on the simple simulation example shown in Figure
19. The frequency of the resonance will depend on the probing signal trace stub
length [14], so it is critical to try to make this stub as short as possible. This is can be
a challenge for large BGAs with a tight-pitch.

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Figure 19: Simple simulation example to demonstrate the effect of the signal trace stub length on
the insertion loss between the DUT and the ATE pin-electronics and vice-versa.
Another improvement to achieve optimal performance of the monitoring interposer is
to terminate all monitoring ports with 50 Ohm. This is demonstrated in Figure 20
which shows the measured insertion loss between the ATE pin electronics and the
DUT with and without the 50 Ohm termination on the monitoring port. This
termination can easily be accomplished in the mini-SMP connector case by a mini-
SMP 50 Ohm termination as also shown in Figure 20.

Figure 20: Impact of the monitoring port 50 Ohm termination on the ATE to DUT signal
integrity (left: insertion loss, right: return loss).
Figure 21 shows the measurement configuration when using a monitoring interposer
with a DUT test fixture on an ATE system where the DUT resides on the DUT socket.
Two examples are shown: one using a monitoring interposer together with a micro-
coaxial probe and the other using a monitoring interposer with a coaxial connector
(mini-SMP). Note that in the case of using a micro-coaxial probe, a special
mechanical setup is required. It connects to the top of the ATE DUT test fixture and
allows the use of a positioner with a magnetic base [15,16]. A microscope is also
needed.

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Figure 21: Picture of using the monitoring interposer on a test fixture docket to an ATE system.
Using a micro-coaxial probe (left) and a mini-SMP coaxial connector (right).
To demonstrate the performance of the monitoring interposer on an ATE setup
without a real DUT, the measurement setup shown in Figure 22 was used. In the
measurement setup the DUT is simulated by the 50 Ohm termination of a real time
oscilloscope channel. A second oscilloscope channel measures the monitoring port on
the monitoring interposer. The signals are generated by an Advantest V93000 ATE
system equipped with a HSM6800 instrument. The real-time oscilloscope is an
Agilent Technologies DSOX92504A with 80 Gsps and 25 GHz bandwidth. The DUT
test fixture used in this measurement is described in a later section and is shown in
Figure 26.

Figure 22: Picture of a monitoring interposer performance measurement setup with an ATE
system using the 50 Ohm impedance of a real time oscilloscope as a DUT replacement.
Figure 23 shows the measured data eyes for a PRBS7 data pattern at 4.266 Gbps. The
results show the expected impact on the peak-to-peak voltage that can be easily
compensated by the ATE pin electronics. The important point, however, is that the
16
rise time degradation is very small and the measured data eye on the monitoring port
correlates very well with the data eye at the DUT.

Figure 23: Measured results from the setup in Figure 22 for a DDR4 DQ pin at 4.266 Gbps.

Monitoring Interposer Impact on the ATE Pin Electronics

Termination Voltage

It is important to note that the monitoring interposer probing circuit might have an
impact on the termination voltage seen by the DUT I/O and therefore requires some
adjustment.
Using the case of a DDR4 DQ I/O as an example, let us assume that a certain
termination voltage (Vt) is required. If a monitoring interposer with a 200 Ohm
probing resistor is added, then the output driver of the DDR4 DQ I/O will now see a
different circuit as shown in Figure 24. The test engineer needs to calibrate the
termination voltage Vt to a new value that guarantees that the current driven from the
DUT I/O stays the same as on the case where there is no monitoring interposer.

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Figure 24: Circuit schematic of using a monitoring interposer with a 200 Ohm resistor probing
circuit together with a real time sampling oscilloscope input termination (50 Ohm to ground).
Another possible option to address this impact of the monitoring interposer would be
to use a DC-blocking capacitor at the oscilloscope measurement input. Unfortunately
this approach usually does not work for memory applications due to the fact that the
patterns are not AC balanced as shown in Figure 25.

Figure 25: Impact of using a DC-blocking capacitor on the measured waveform at the
monitoring port to address the 50 Ohm to ground termination of a real-time sampling
oscilloscope. Top waveform: no DC-blocking capacitor and compensated termination voltage at
the ATE pin electronics. Bottom waveform: a DC-blocking capacitor (45 MHz to 26.5 GHz) was
added to the real-time oscilloscope input without any change on the ATE pin electronics
termination voltage.

Results with a DDR4 Application

To test the monitoring interposer with a DDR4x8 application the DUT test fixture
shown in Figure 26 was used. This ATE test fixture is designed for the Advantest
V93000 ATE system. The DUT socket is a pogo pin type socket with a compressed
length of 2.05 mm. In this example, the monitoring interposer used probing pads for a
micro-coaxial probe (GGB 40A VP style probe with 0.8 mm signal to ground pitch)
on the monitoring port.

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Figure 26: Advantest V93000 DDR4x8 ATE test fixture.
Figure 27 shows the measurement setup used on the ATE system together with a
DDR4 monitoring interposer and a micro-coaxial probe to monitor the signaling
between the ATE pin electronics and the DUT. In the measurement results the DUT
DDR4 DQ I/O is driving a signal. The top right area of the picture shows the signal
measured by the real-time oscilloscope connected to the monitoring port and the
lower right area shows the signal measured by the ATE pin electronics.

Figure 27: Monitoring a DDR4 DQ pin using the monitoring interposer and also measuring the
waveform with the ATE pin electronics oscilloscope tool.

Figure 28 shows a shmoo plot measured by the ATE pin electronics of the DDR4
DUT data rate (tCK) in the Y-axis to the DQ data eye width (tAC) in the X-axis with
and without the monitoring interposer. By comparing both shmoo plots, it is possible
to observe that there is only a very minor degradation on the highest data rates the
DUT can achieve which are in fact outside the device target specifications. Also note
that the setup was not ideal since all the monitoring ports were left open and not
terminated with 50 Ohm.

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Figure 28: Comparison of a data rate (tCK) versus data eye width (tAC) shmoo plots of a DDR4
application without the monitoring interposer (left) and with the monitoring interposer (right).
All monitoring ports were left open.

Results with a GDDR5 Application

To test the monitoring interposer with a GDDR5 application the DUT test fixture
shown in Figure 29 was used. This ATE test fixture is designed for the Advantest
V93000 ATE system. The DUT socket is a pogo pin type socket with a compressed
length of 2.05 mm. In this example, the monitoring interposer used mini-SMP coaxial
connectors on the monitoring port.

Figure 29: Advantest V93000 DDR3x8 and GDDR5 ATE test fixture

Figure 30 shows an overlay of the measured DQ data eyes on the DQ16 I/O pin by the
ATE pin electronics (Advantest V93000 HSM6800) with and without the monitoring
interposer at a data rate of 4 Gbps. From the results it is possible to see that there is a
minimal impact on the data eye width when the monitoring interposer is added. Figure
31 shows the measurement setup on the ATE system with the measured waveform by
the ATE pin electronics timing diagram software and the monitored waveform
measured by the real time sampling oscilloscope.

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Figure 30: Overlay of the GDDR5 DQ16 I/O pin data eye diagram measured by the ATE pin
electronics without the monitoring interposer and with the monitoring interposer at 4 Gbps. All
monitoring ports were left open.

Figure 31: Measurement setup picture with the measured waveform by the ATE pin electronics
(top) and the monitored waveform measured by the real time sampling oscilloscope (bottom).

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Conclusions

The monitoring interposer approach described in this paper presents two major
advantages in regards to previous approaches designed to address this challenge:

• Higher performance due to its small size.

• It can be easily removed when no longer required. This completely removes
the impact of the monitoring interposer on the signal path between the ATE
pin electronics and the DUT.

The demonstrated performance of the monitoring interposer allows the test engineer
to use it not only for monitoring the ATE to DUT signaling but also to perform
parametric measurements like rise-time, data eye diagram and jitter measurements.
This is especially useful in situations where a low-performance (low-cost) ATE
system is used with limited parametric measurement capabilities since the test
engineer can use any type of external bench instrument with the monitoring interposer
to measure the DUT.

The main impact on the monitoring interposer performance is clearly the stub length
to the probing circuit (e.g. the probing resistor). This presents a challenge when
applying this approach to signal inside large BGAs with a small pitch. Another
possible impact is the added inductance on the DUT power pins due to the thickness
of the interposer.

The monitoring interposer manufacturing costs can be reduced by merging designs for
different applications/packages on a single PCB panel instead of handling each
monitoring interposer as a single project with a single manufactured panel.

One possible approach to further improve the accuracy of the waveform measured at
the monitoring port is to de-embed the monitoring interposer using the monitoring
interposer measured S-parameters.

Acknowledgments

We would like to thank Tomoaki Kobayashi, Takeshi Sonoda, Noritoshi Obara, Koji
Sakai and Hubert Werkmann from Advantest for their help in this project and to Yoko
Kato and the Advantest Gunma FA lab team for the physical analysis pictures.

References

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High-Speed Interfaces”, Artech House 2010.
[2] Picosecond Pulse Labs, “Model 5361 5x Pickoff Tee”, Product Specification
2009.
[3] Eric Bogatin, Lambert Simonovich, Sanjeev Guota and Mike Resso, “Practical
analysis of Backplane Vias”, DesignCon 2009.
[4] Agilent Technologies, “W2635A and W2636A DDR3 BGA Probe Adapters for
the Infiniium Oscilloscopes”, Data Sheet 5989-7643, January 2011.
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[5] Shaul Lupo and Omer Vikinski, “Pin Grid Array Current Sense Interposer
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[12] DDR4 SDRAM Component Spec (JESD79).
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[14] David M. Pozar, “Microwave Engineering, 4th Edition”, Wiley 2011.
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