EE 2255 Microelectronics

Lecture 8: Design of Single-Stage Amplifiers

− General Considerations and Biasing
• General considerations
BJT vs. MOSFET − input/output impedance
− different amplifier topologies rout
− DC and small-signal analysis r
in
• Different biasing configurations
− simple biasing very important in practical circuit design

− resistive divider
− self-bias
− current source bias
pp. 153-179, 281-286 in the textbook
EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 1/26
 General Considerations
• A voltage-controlled current source along with a load
resistor can form an amplifier.
• Most of the electronic circuits both sense and produce voltage quantities,
and thus our discussion focuses on “voltage amplifiers” and “voltage gain.”
• In addition to gain, there are other important aspects of amplifiers:
(1) power dissipation (2) speed (3) noise.
• The input and output (I/O) impedances (resistances for low-frequency
operation) also play a critical role.
𝑅𝐿 𝑉𝑜𝑢𝑡
∗ 𝑃𝑑𝑖𝑠𝑠 = 𝑃𝐷𝐶 = 𝑉𝐶𝐶 × 𝐼𝐶 (BJT) 𝑉𝑖𝑛

* Often neglect the

base or gate current

Zin Zout

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 2/26

 Input and Output Impedances (1/3)
Z= V/ I
• Impedance: the ratio of the voltage phasor to the current phasor
− Z= R+jx (real part + imaginary part). At DC and/or low frequencies, the
𝐼𝑚 impedance is often simplified to resistance R.
𝑍 = 𝑅 + 𝑗𝑋
𝑋 * How about if considering 𝐶𝜋 ?
𝜃
𝑅 𝑅𝑒

small-signal model of BJT

Zin

Zout

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 3/26

 Input and Output Impedances (2/3)
• Why is the input and output (I/O) impedances of an amplifier important?
− determine the transfer of signals from one stage to the next.
− in an ideal case, Zin should be infinite and Zout should be zero for a
voltage amplifier. 𝑍
𝑅𝑆 𝑜𝑢𝑡
′
RS: internal resistance 𝑉𝑜𝑢𝑡
+
of a signal source 𝑟𝜋 𝑣𝜋
𝑉𝑖𝑛 − 𝑅𝐿 Vout 𝑍𝐿′
𝑔𝑚 𝑣𝜋

VDD

 ideal case:
A
𝑉𝐷𝐷

𝑉𝑜𝑢𝑡
 real case:
Zin Zout

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 4/26

 Input and Output Impedances (3/3)
• How to determine the input and output impedances under small-signal
condition?
− the input (output) impedance is measured between the input (output)
nodes of the circuit while all independent sources in the circuit are set to
zero.
− identical to the approach for obtaining the Thevenin impedance.
* How about Zin from emitter?
+ +
𝑣𝜋 𝑟𝜋 𝑟𝑜 𝑣𝜋 𝑟𝜋 𝑔𝑚 𝑣
𝑣𝑥 −
−
+
𝑣𝑥
−

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 5/26

 Single-Stage vs. Multi-stage Amplifier
• A single-stage amplifier is normally referred to an amplifier constructed
by one basic transistor amplifier topology, namely, common-source
(common-emitter), common-gate (common-base), or common-drain
(common-collector).
• A more complicated amplifier can be constructed by two or more
signal-stage amplifiers and is called the “multi-stage” amplifier.
* CS or CE stage
⟹ good for input stage

single-stage amplifier

vin A vout vin A1 A2 An vout

.….
𝑉𝐷𝐷
𝑅𝐿
𝑅𝐿 𝑅𝐿
𝑉𝑜𝑢𝑡
𝑉𝑖𝑛

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 6/26

 Basic Single-Stage Amplifier Topologies (1/3)
• Since a transistor (BJT or MOS, neglect body effect) has three terminals,
there are nine possible input/output combinations for amplifiers.
• For functional amplifiers, only three possible topologies remain.

  
+ Input
⟹ common-emitter * If Vin is connected
(common-source) at collector or drain

+
⟹

Output   

+
⟹

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 7/26

 Basic Single-Stage Amplifier Topologies (2/3)
• For both BJT (MOS) amplifiers, there are three basic amplifier topologies.
− common-emitter (common-source)
𝑅𝑆
− common-base (common-gate) 𝑉𝑜𝑢𝑡
− common-collector (common-drain) +
𝑣𝑔𝑠 𝑔𝑚 𝑣𝑔𝑠 𝑟𝑜
𝑉𝑖𝑛 − 𝑅𝐷

common node for both

input and output

Common-emitter Common-source

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 8/26

 Basic Single-Stage Amplifier Topologies (3/3)
* CE, CS ⟹ large Zin and Zout small Zin, large Zout
* In general, gm is
designed to be large

Common-base Common-gate

Common-collector Common-drain

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 9/26

 Biasing of Amplifiers
• A bipolar transistor operates as an amplifying device if it is biased in
the active mode. Similarly, a MOSFET must be biased in the saturation
mode for amplifier design. operating point
• Also, the small-signal model parameters of transistors depend on
BJT:
the quiescent point (Q-point; bias point).
MOSFET:
• How to bias the transistor properly for amplification?
 
 In practical design, resistors and/or current sources are often used for
amplifier biasing.

EE2255 Microelectronics, S. Hsu, EE NTHU 10/26

 DC and Small-Signal Analysis (1/2)
separate DC and AC  simplify the analysis
• Procedure for amplifier analysis:
(1) DC analysis (set the AC signals to zero): compute the operating point
(terminal voltages and currents) in the absence of signals.
(2) small-signal analysis (set the DC sources to zero): study the response
of the circuit to small signals and compute quantities such as the
voltage gain and I/O impedances. DC+AC  final results
 the two steps follow the superposition principle.
𝑉𝑖𝑛 + 𝐶1 𝐵2 +
𝑣𝜋1 𝑟𝜋1 𝑔𝑚1 𝑣𝜋1 𝑅𝐶1 𝑣𝜋2 𝑔𝑚2 𝑣𝜋2
−
−

a two-stage amplifier

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 11/26

 DC and Small-Signal Analysis (2/2)
• More details about small-signal analysis:
(1) voltage and current sources (independent sources) that do not vary
with time, must be set to zero. Ground all the constant voltage sources
(AC ground) and open all constant current sources. gm, r, ro, …
(2) determine the small-signal equivalent circuit model parameters based on
𝐼𝐶
the DC bias point. BJT: 𝑔𝑚 =
𝑉𝑇
• Design of amplifiers follows a similar procedure with amplifier analysis:
(1) the circuitry around the transistor (biasing circuit) is designed to establish
proper bias conditions and hence the necessary small-signal parameters.
(2) study (design) the small-signal parameters for the required performance.
Some iterations may often be necessary for the desired performance.
• In practical circuit design, one criterion to justify the small-signal condition
is that the AC current signal is within 10 % of the total bias current (collector
or drain current).
* In practice, if 𝑖𝐷 ≤ 0.1 𝐼𝐷

S. S. BJT： 𝑉𝐵𝐸 ~ 𝑉𝑇 (26 mV)

input
MOS：𝑉𝐺𝑆 ~ (10 ~ 50 mV) ID

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 12/26

 Operating Point Analysis and Design
• A student tried to design an amplifier to enhance the signal from a
microphone based on what he has learned in the class. Will these two
designs work? What are the problems?
* What is the problem of topology ? * What is the problem of topology?
(a) 𝑉𝐵𝐸 = 𝑉CC 
(b) VCC is AC ground 

 

microphone

Common-emitter amplifier

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 13/26

 Simple Biasing for BJTs
• A simple bias scheme of BJT is to connect the VCC through a
relatively large resistor RB
 use only one power supply to bias both BE and CB junctions.
* Why a large RB ?
⟹ solve problem 
⟹ solve problem 

 +
𝑅𝐵 𝑟𝜋 𝑣𝜋 𝑔𝑚 𝑣𝜋 𝑟𝑜 𝑅𝐶
𝑉𝑖𝑛
−

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 14/26

 Resistive Divider Biasing for BJTs (1/2)
• In the simple bias scheme, there exists a dependence of IC upon the
current gain . 𝐼𝐶 = 𝑉𝐶𝐶 − 𝑉𝐵𝐸 × 𝛽
𝑅𝐵
• How to precisely determine the bias current IC for amplifier design?
 resistive divider configuration.

* Assume IB is negligible

CB

Rs

vin

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 15/26

 Resistive Divider Biasing for BJTs (2/2)
• The assumption for the resistive divider bias is that the base current
can be neglected. But what if IB is not negligible?
 𝑅𝑇ℎ𝑒𝑣  𝑉𝑇ℎ𝑒𝑣

IB
VX

* How about for MOS amplifier?

𝑉𝐷𝐷
𝑉𝐷𝐷
𝑅1
𝑅𝐶
𝑉𝐶𝐶 𝑅1
𝑉𝑜𝑢𝑡
𝑅2 ≡ 𝑉𝑥
𝑅2

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 16/26

 Biasing with Emitter Degeneration
• A biasing configuration that reduces the sensitivity of IC to  and VBE
is called “Emitter degeneration.”
• The linear I-V relationship of RE somehow “absorb” the error introduced
from Vx due to the inaccuracies in R1, R2, or VCC.
 stabilize the bias point.
* R1, R2 variation (10% ~ 20% in real circuit)
* Rules in practical design ⟹ 𝑉𝑋 changes from designed value
 𝐼1 ≫ 𝐼𝐵
* Add RE to reduce sensitivity

 𝑉𝑅𝐸 ≫ ∆𝑉𝑋
* w/o RE ⟹ all ∆𝑉𝑋 will drop on 𝑉𝐵𝐸

 𝑅𝐶 cannot be too large

* w/i RE, most of ∆𝑉𝑋 drops on 𝑅𝐸

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 17/26

 Design Example of Emitter Degeneration
• Design the emitter degeneration bias to provide a transconductance
of 0.02 A/V for Q1. Assume VCC= 2.5 V, = 100 and IS= 510-17 A.
What is the maximum tolerable value of RC?

VY = VCC - ICRC

IC
I1
VY
VX IB
vout

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 18/26

 Self-Biased Stage for BJTs
• Since the base current and voltage are provided from the collector, this
configuration is called “self-biased.”
• In this design, the base voltage is always lower than the collector voltage
 Q1 is guaranteed to operate in the active mode.

VX = VY - IBRB

IC
IB VY = VCC - ICRC
VY
VY = RBIB + VBE
VX

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 19/26

 Design Guideline for Self-Biased Stage
• Two important guidelines for self-biased stage design:
(1) VCC-VBE >> the uncertainty of VBE  relatively easy to be satisfied
(2) RC >> RB/

• Design procedure:
(1) Based on the small-signal circuit specifications to determine the
required IC
(2) Since RC must be much greater than RB/
 assuming RC = 10 (RB /)

 RB / = 0.1 RC

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 20/26

 Design Example for Self-Biased Stage
• Design the self-biased stage for gm= 0.077 A/V and VCC= 1.8 V.
Assume IS= 510-16 A and = 100.

VCC

RB RC

RS
vin

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 21/26

 Summary of Biasing Techniques for BJT
Amplifiers

Resistive divider
Simple biasing
biasing

𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐶 = ∙𝛽
𝑅𝐵

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 22/26

 Biasing For MOS Amplifiers
• Some of the biasing techniques of MOS amplifiers are similar with BJTs.
• Owing to the lack of gate current (iG= 0), the situation in MOS amplifier
is in general simpler when using a similar bias topology as BJTs.

𝑅2
𝑉𝑋 = ∙ 𝑉𝐷𝐷
𝑅1 + 𝑅2

Resistive divider biasing

with source degeneration

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 23/26

 Example of Resistive Divider Biasing for
MOS Amplifiers
• Determine the bias current ID. Assuming VTH= 0.5 V, mnCox= 100 mA/V2,
W/L= 5/0.18, and neglecting the channel-length modulation. What is the
maximum allowable RD for M1 to remain in saturation?
Method : iteration 

Method : find exact solution 

*when RD   gain 

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 24/26

 Self-biased MOS Stage
• Similar to BJTs, the self-biasing technique can also be applied to MOS
amplifiers.
• In this design, the MOS is guaranteed to operate in the saturation mode.

IG = 0  VX = VY  VX – VY = 0

RG is typically large
~ k ID
VY

VX

IG

EE2255 Microelectronics, S. Hsu, EE NTHU Lecture_8 25/26

 Biasing with Current Sources
• Since MOS transistors operating in saturation can act as current sources,
they can be used to bias other transistors for amplifier design.
• More details about biasing by current sources will be discussed later
together with the current mirror. 𝐼𝐷 *S. S. output impedance of
ideal current source 

𝑉𝐷𝑆

𝑉𝐷𝐷

𝑉𝐺
𝑀2
𝑉𝑜𝑢𝑡
𝑉𝑖𝑛 𝑀1 𝑉𝐷𝐷
𝑉𝐷𝐷

𝑉𝐺 𝑅𝐿
PMOS
𝑉𝑜𝑢𝑡
𝑉𝑜𝑢𝑡 𝑉𝑖𝑛
𝑉𝑖𝑛 NMOS

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