IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO.

2, FEBRUARY 2022 1201

Letters
Generic PLL-Based Grid-Forming Control
Lennart Harnefors , Fellow, IEEE, Mario Schweizer , Member, IEEE, Jarno Kukkola ,
Mikko Routimo , Member, IEEE, Marko Hinkkanen , Senior Member, IEEE,
and Xiongfei Wang , Senior Member, IEEE

Abstract—In grid-forming control, the swing equation of a syn- applied [4]. During normal operation, the PLL can be disengaged
chronous machine is emulated by a power controller. Thereby, and the PC solely be relied upon.
frequency droop, power-oscillation damping, and/or virtual inertia Unfortunately, as a consequence, during current limitation,
can be obtained. In this letter, it is shown that a phase-locked
loop—which is normally grid following—can be designed so as an ON/OFF chattering behavior of the PLL may occur. One way
to, in turn, emulate a generic power controller, thus, becoming of preventing this would be somehow to make the PLL fulfill
grid-forming. Property 2, allowing the PC to be eliminated, thus, simplifying
Index Terms—Grid-connected converters, grid-forming control, the structure of the SC. Steps in that direction have been taken. A
phase-locked loops, voltage-source converters. PLL in [5] is shown to have structural similarities to the swing
equation, and can reproduce certain characteristics thereof if
tuned properly [6], [7].
I. INTRODUCTION The contribution of this letter—in relation to prior art, where
RID-FORMING control of a voltage-source converter has certain special cases are considered—is the design of a PLL-
G two fundamental properties.
r Property 1: The back electromotive force of a synchronous
based grid-forming control (PLL-GFC) scheme that emulates a
generic PC.1 See Section III. The emulation is not exact, but the
machine is emulated, giving a stiff converter voltage. accuracy is sufficient as seen from the fairly slow time scale of
r Property 2: The swing equation of a synchronous ma- grid-frequency variations. Thus, Property 2 is fulfilled. Design
chine is emulated, giving an active-power response to for PSC correspondence, fulfilling also Property 1, is considered
grid-frequency variations. in Section IV. (The design in Section IV summarizes the key
Schemes based on vector current control are normally grid- results of [1], but PC emulation by the PLL is not considered
following. Yet, in [1], it is shown that Property 1 can be fulfilled in [1].) Experimental evaluation with performance comparison
by a vector-current-control scheme, designed for correspon- of PLL-GFC and PSC is made in Section V.
dence to power-synchronization control (PSC).
Property 2 is, in conventional PSC, fulfilled by a power II. PRELIMINARIES
controller (PC) [2]. In [1], a hybrid synchronization controller
Boldface letters denote the complex space vectors. The super-
(SC) is proposed, where the PC is combined with a phase-locked
script s denotes a vector referred to the stationary αβ reference
loop (PLL). A similar scheme is suggested in [3]. In PSC, the
frame. The corresponding vector referred to the synchronous
PLL is needed for synchronization at startup [2] as well as to
dq reference frame, which has angle θ as reference, is denoted
prevent loss of synchronism when converter-current limitation is
without a superscript. Italic letters denote the scalar variables and
real transfer functions. The reference for a controlled variable is
Manuscript received June 2, 2021; revised July 12, 2021; accepted August
11, 2021. Date of publication August 19, 2021; date of current version October denoted by appending the sub- or superscript ref. The Laplace
15, 2021. This work was supported in part by ABB. (Corresponding author: variable s is to be considered as the operator s = d/dt, where
Lennart Harnefors.) appropriate.
Lennart Harnefors is with the ABB AB, Corporate Research, 722 26 Västerås,
Sweden (e-mail: [email protected]). Fig. 1 illustrates the main circuit and the controller block
Mario Schweizer is with the ABB Switzerland Ltd., Corporate Research, 5405 diagram. The former consists of an inductor, with inductance
Baden-Dättwil, Switzerland (e-mail: [email protected]). L and inner resistance R, between the converter and point-of-
Jarno Kukkola and Marko Hinkkanen are with the Department of Electrical
Engineering and Automation, Aalto University, 02150 Espoo, Finland (e-mail: common-coupling (PCC) buses. The respective voltage vectors
[email protected]; [email protected]). are vs and Es , whereas the output current is is . The active output
Mikko Routimo is with the ABB Oy Drives, 00380 Helsinki, Finland (e-mail:
[email protected]).
Xiongfei Wang is with the Department of Energy Technology, Aalborg
University, 9100 Aalborg, Denmark (e-mail: [email protected]). 1 Important special cases of the generic PC are pure proportional, giving
Color versions of one or more figures in this article are available at frequency droop; proportional–integral, giving power-oscillation damping and
https://doi.org/10.1109/TPEL.2021.3106045. virtual inertia; and lead–lag, giving frequency droop, power-oscillation damping,
Digital Object Identifier 10.1109/TPEL.2021.3106045 and virtual inertia [8].

0885-8993 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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1202 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO. 2, FEBRUARY 2022

Fig. 1. Circuit and controller block diagram. Fig. 3. Generalized AVC with current-reference selection and SAT.

quasi-stationary relation, which captures the dynamics of grid-

frequency variations well enough, can be obtained, as will now
be demonstrated.
Since active power, according to (1), is produced by id , the
first step is to create a coupling from Eq to iref
d , in turn, giving a
coupling to P . This can be accomplished by implementing (2)
as shown in Fig. 3, in equation form
Fig. 2. Hybrid SC, combining a PLL with controller Fp (s) with a PC Kp (s).
AVC(Eref , E) = Yv (s)(Eref − E) − Yq (s)Eq
− jFv (s)(Eref − Ed ). (3)
power at the PCC is calculated as
Here, Fv (s) is a conventional AVC, coupling from Ed to iref q . It
3 needs to have integral action to make Ed = Eref statically. Yv (s)
P = κRe{Es (is )∗ } = κRe{Ei∗ }, κ= (1)
2 K2 is an active damper consisting of a gain (active conductance) Ga
where the superscript ∗ denotes the complex conjugate and K in cascade with a low-pass filter. It is vital for fulfilling Property
is the space-vector scaling constant. The dq frame is statically 1; see Section IV. Yq (s) similarly consists of a gain (active
aligned with the PCC voltage, so that E = E (i.e., real), giving susceptance) Ba in cascade with a low-pass filter. It creates the
P = κEid in the steady state. required coupling from Eq to irefd .
Voltage reference vref is computed by a current controller Let us now analyze the impact of (3) seen from the time scale
(CC). The ideal current reference is set as of grid-frequency variations. This time scale is given by the
characteristic inertia constant of the grid, which is typically in
Pref
i0ref = iref
P + AVC(Eref , E), iref
P = (2) the range of seconds. This is substantially slower than the closed-
κEref loop-system rise times assumed in Section II. Consequently, in
where the second term is the complex output of a generalized the time scale of grid-frequency variations, the static relations
ac-bus-voltage controller (AVC); see Section III for details. i = iref and Ed = Eref can be considered. In addition, the filters
To avoid absolute values exceeding the maximum permissi- in Yv (s) and Yq (s) are assumed to have high enough bandwidths
ble current, vector saturation (SAT) is then applied, forming to be considered statically as well, i.e., Yv (0) = Ga and Yq (0) =
iref = SAT(i0ref ). The CC and the AVC are assumed to be tuned Ba . Assuming that SAT is not effectuated, (2) and (3) then yield
such that the resulting closed-loop step-response rise times are i = iref
P − Ba Eq − j (Ga Eq + iv ) (4)
in the ranges of tens and hundreds of milliseconds or less,   
−iq
respectively. In addition, zero static control errors are assumed,
i.e., i = iref and Ed = Eref statically. The latter is achieved by where iv is the quasi-static value of the integrator of the conven-
the AVC adjusting irefq . tional AVC. Substitution in (1) yields
P = κRe{Ei∗ } = Pref − κ(Eref Ba − iq )Eq . (5)
III. MAIN RESULT
Solving for Eq in (5) gives the desired proportionality between
Fig. 2 shows the hybrid SC of [1], where ω1 is the nominal
the PC and PLL input signals as
angular grid frequency. The objective is now to make the PLL
emulate the PC, i.e., the signal path through Fp (s) should have a 1
Eq = (Pref − P ). (6)
similar effect [for Kp (s) = 0] as the signal path through Kp (s) κ(Eref Ba − iq )
[for Fp (s) = 0]. Clearly then, a mechanism that forces the PLL
Consequently, for the PLL to emulate the PC, the PLL controller
input signal Eq to be proportional to the PC input signal Pref − P
should be selected as
is needed. A static relation between the two input signals cannot
be obtained, so an exact emulation is impossible. However, a Fp (s) = κ(Eref Ba − ifq )Kp (s) (7)

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO. 2, FEBRUARY 2022 1203

TABLE II
EXPERIMENTAL SETUP DATA

Fig. 4. Proportional–decoupling–feedforward CC.

TABLE I
CONTROLLER SELECTIONS

2) PSC uses neither a conventional AVC, nor a PLL. To

ensure that E = Eref statically, despite that, an integral
part (with gain αa ) is included in Yv (s).
3) For PLL-GFC, in addition to Fp (s), also Fv (s) is made
proportional to Kp0 (s). Under idealized conditions, this
where ifq is a low-pass filtering of iq (or, if preferred, iref
q ). Low-
gives the same small-signal dynamics as the PC.
pass filtering is desired to suppress noise in the variable gain
4) For simplicity, the low-pass filter in Yq (s) is chosen iden-
of (7).
tical to that in Yv (s).
The working principle of the proposed scheme is perhaps
easiest understood by expressing the PCC voltage in po-
lar form as Es = Eejθp ⇒ E = EejΔθ , Δθ = θp − θ, giving V. EXPERIMENTAL AND SIMULATION RESULTS
Eq = E sin Δθ. Suppose that Δθ = 0 initially. A variation in The experimental setup—see Table II for data—uses back-to-
the grid frequency, let us say a drop, results in θp lagging θ, back converters, allowing dc-bus-voltage control from the con-
i.e., Δθ becomes negative. Via the second term in (3), this verter not being studied. There is a shunt capacitor (with capaci-
causes an active-power injection. The characteristics thereof are tance C) at the PCC, forming an inductive–capacitive–inductive
determined solely by Kp (s); due to the factor κ(Eref Ba − ifq ) filter with the grid inductance Lg behind the grid-voltage source.
in (7), the characteristics are invariant of Ba . A larger Ba merely Performance comparisons of PLL-GFC and PSC, designed
results in smaller transients in Δθ and, thus, in Eq . At the very according to Section IV, are made. A proportional–integral PC
least, to avoid the risk that the gain of (7) changes sign, Ba > is considered as
max(iq )/Eref should be selected. Normally, max(iq )/Eref ≤ 1 1
per unit (p.u.). Kp0 (s) = Kp + . (9)
Ms
As shown in [8], the proportional part corresponds to a power-
IV. DESIGN FOR PSC CORRESPONDENCE oscillation damper and the integral part to a virtual inertia. The
As long as the assumptions relied upon in Section III are following p.u. parameter values are selected:
fulfilled, the CC and blocks Yv (s) and Fv (s) of the AVC can be
Ra = 0.2, Kp = 0.05, M = 1000
chosen freely. However, of particular interest is a design giving
near equivalence between PLL-GFC and the slightly modified Ba = 5, αa = 0.1. (10)
PSC variant considered in [1], thus, ensuring that Property 1 is
fulfilled. As shown in [1], such a design is obtained by using a First, Lg is selected to get a short-circuit ratio of 1. The grid
proportional–decoupling–feedforward CC (see Fig. 4) voltage is 1 p.u. In Fig. 5, the grid frequency ωg /(2π) is ramped
from 50 Hz (1 p.u.) down to 49 Hz (0.98 p.u.) with the rate
vref = Ra (iref − i) + (R + jω1 L)i + H(s)E. (8) of change 5 Hz/s. As can be observed, near-identical inertial
responses in P are obtained from the two schemes. Due to the
In the PCC-voltage feedforward term, the recommended low- proportional (damping) part of (9), there are no power oscil-
pass filter selection is H(s) = αc /(s + αc ), where αc = Ra /L lations. The transient in Eq for PLL-GFC results in a slightly
is the bandwidth of the closed current control loop that results different transient in iq compared to PSC.
from (8). Next, the configuration is changed to islanded operation,
With Kp0 (s) as the desired PC (to be implemented in PSC with zero grid voltage. Lg is reduced to 0.5 p.u. and a 6-p.u.
and emulated in PLL-GFC), Table I shows the controller selec- load resistance is put in series. M is made infinite, giving a
tions, with reference to Figs. 2 and 3, for PSC and PLL-GFC, proportional-only PC, i.e., a frequency droop [8]. In Fig. 6, at
respectively. The following should be noted (see [1] for details). t = 0.2 s, the load resistance is decreased to 2 p.u., giving an
1) To fulfill Property 1, the active conductance is selected as increased power draw and, as a result, a frequency reduction.
Ga = 1/Ra . It is interesting to note that the instantaneous frequencies of

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1204 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO. 2, FEBRUARY 2022

Fig. 7. Islanded operation with load-resistance step; simulation of two parallel

converters (I and II) using PLL-GFC.

Fig. 5. Grid-frequency ramp.

corresponding experimental curves in Fig. 6, but scaled with half
due to the load sharing.

VI. CONCLUSION
Previous findings concerning the similarity between a PLL
and the swing equation of a synchronous machine were general-
ized. The scheme PLL-GFC results, where the PLL is designed
to emulate a generic PC, fulfilling Property 2. Design for PSC
correspondence was considered, fulfilling also Property 1.
Experimental comparison of PLL-GFC and PSC showed
near-identical performance. The most notable difference is that,
in PLL-GFC, transients in P are reflected by transients in Eq
(and vice versa). This is caused by the coupling from Eq to iref
d ,
with gain Ba , introduced to fulfill Property 2. The transients in
Eq diminish as Ba is increased.

REFERENCES
[1] L. Harnefors, J. Kukkola, M. Routimo, M. Hinkkanen, and X.
Wang, “A universal controller for grid-connected voltage-source con-
verters,” IEEE J. Emer. Sel. Top. Power Electron., early access,
doi: 10.1109/JESTPE.2020.3039407.
[2] L. Zhang, L. Harnefors, and H.-P. Nee, “Power-synchronization control
Fig. 6. Islanded operation with load-resistance step.
of grid-connected voltage-source converters,” IEEE Trans. Power Syst.,
vol. 25, no. 2, pp. 809–920, May 2010.
[3] L. Huang, H. Xin, Z. Wang, L. Zhang, K. Wu, and J. Hu, “Transient stability
PSC and PLL-GFC deviate transiently. This is because the PLL analysis and control design of droop-controlled voltage source converters
emulation of the PC is not exact. Yet, the active-power responses considering current limitation,” IEEE Trans. Smart Grid, vol. 10, no. 1,
pp. 578–591, Jan. 2019.
are virtually identical, showing that the quasi-stationary design [4] L. Harnefors, “Method and control system for controlling a voltage source
principle in Section III is relevant. converter using power-synchronisation control,” Patent EP 3 534 522 B1.
The experimental setup unfortunately does not facilitate mul- [5] X. Wang, M. G. Taul, H. Wu, Y. Liao, F. Blaabjerg, and L. Harnefors,
“Grid-synchronization stability of converter-based resources-an overview,”
tiple converters. To show that PLL-GFC has the capability of IEEE Open J. Ind. Appl., vol. 1, pp. 115–134, 2020.
islanded operation with multiple converters, the experimental [6] H. Alatrash, A. Mensah, E. Mark, G. Haddad, and J. Enslin, “Generator
setup is replicated in Simulink, but with two converters (I and emulation controls for photovoltaic inverters,” IEEE Trans. Smart Grid,
vol. 3, no. 2, pp. 996–1011, Jun. 2012.
II) connected in parallel at the PCC. The converters and their [7] M. Zhang, X. Yuan, and J. Hu, “Inertia and primary frequency provisions
controls are identical, but to introduce an asymmetry, they have of PLL-synchronized VSC HVDC when attached to islanded ac system,”
slightly different filter inductances: LI = 1.1 L and LII = 0.9 L. IEEE Trans. Power Syst., vol. 33, no. 4, pp. 4179–4188, Jul. 2018.
[8] W. Zhang et al., “Comparison of different power loop controllers for
As can be observed in Fig. 7, the converters share the load power synchronous power controlled grid-interactive converters,” in Proc. IEEE
equally. In fact, the curves (for voltage, Eq only) replicate the Energy Conv. Congr. Expos., Montreal, 2015, pp. 3780–3787.
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