BASIC COMPUTER

ORGANIZATION
CHAPTER 2
ARCHITECTURE & ORGANIZATION

•Computer architecture
• Logical aspects of system implementation as seen by the programmer.
• E.g., instruction sets, instruction formats, data types, addressing modes.
• How do I design a computer?

•Computer organization
• Encompasses all physical aspects of computer systems.
• E.g., circuit design, control signals, memory types.
• How does a computer work?
ARCHITECTURE & ORGANIZATION

• Principle of Equivalence of Hardware and Software:

•Anything that can be done with software can also be done

with hardware, and anything that can be done with
hardware can also be done with software.*
• * Assuming speed is not a concern.
BASIC COMPONENTS OF A COMPUTER
SYSTEM
BASIC COMPONENTS OF A COMPUTER
SYSTEM
• A computer system consists of three basic elements
•Processing units (processors)
• Executes instructions in a program
• A processor has an architecture that determines the form and sequence of instructions
• A processor has an organization that explains how circuits are organized
BASIC COMPONENTS OF A COMPUTER
SYSTEM
BASIC COMPONENTS OF A COMPUTER
SYSTEM

•Memory
• The storage area in which programs are kept when they are running and that
contains the data needed by the running programs
• The architecture of a memory defines the methods by which data may be
taken from and placed in the memory
• Structure of the elements that the memory hold
• The organization of a memory defines it’s physical structure , the physical
layout of data elements into memory units
BASIC COMPONENTS OF A COMPUTER
SYSTEM

•Input/output (I/O)
• The I/O architecture defines the form and conventions that must be used
in a program in order to move elements between I/O devices and memory
• The I/O organization defines structure of an I/O subsystems, how
functions are distributed between the elements, the various speeds of
different elements
BASIC COMPONENTS OF A COMPUTER
SYSTEM
BASIC COMPONENTS OF A COMPUTER
SYSTEM
• The main three components are interconnected by a system bus.
• The term “bus” is used to represent a group of electrical signals or the wires
that carry these signals

• the three major components of the system bus are the address bus, data bus,
and control bus.

• The control bus consists of a set of control signals include memory read,
memory write, I/O read, I/O write, interrupt, interrupt acknowledge, bus
request, and bus grant.
BASIC COMPONENTS OF A COMPUTER
SYSTEM
• The width of the address bus determines the memory addressing capacity of the
processor (Go to BOOK)

• The width of the data bus indicates the size of the data transferred between the
processor and memory or I/O device

• Every bus transaction involves a Master and a Slave.

• The master is the initiator of the transaction and the slave is the target of the
transaction. For example, when the processor wants to read data from the memory, it
initiates a bus transaction, also called a bus cycle, in which the processor is the bus
master and memory is the slave.

• The processor usually always acts as the master of the system bus
THE PROCESSOR

• The processor acts as the controller of all actions or services provided by the
system. It can be thought of as executing the following cycle forever:
1. Fetch an instruction from the memory;
2. Decode the instruction (i.e., identify the instruction);
3. Execute the instruction (i.e., perform the action specified by the instruction).

• This process is often referred to as the fetch-decode-execute cycle, or simply

the execution cycle.
THE PROCESSOR

• Fetching an instruction involves placing the appropriate address on the

address bus and activating the memory read signal on the control bus to read
from the specific memory location.
THE PROCESSOR

• Decoding involves identifying the instruction that has been fetched from the
memory. To facilitate the decoding process, machine language instructions
follow a particular instruction encoding scheme.

• To execute an instruction, the processor contains hardware consisting of

control circuitry and an arithmetic and logic unit (ALU). The ALU is mainly
responsible for performing arithmetic operations (such as add, divide) and
logical operations (such as and, or) on data.
THE PROCESSOR

• The System Clock (from BOOK)

• The system clock provides a timing signal to synchronize the operations of the system
• The clock frequency is measured in the number of cycles per second. This number is
referred to as Hertz (Hz).
• The system clock defines the speed at which the system operates
• With every tick(cycle) of the clock, the CPU is able to process one piece
of data or execute one instruction.
NUMBER OF ADDRESSES

• Most operations can be divided into binary or unary operations

• Binary operations such as addition and multiplication require two input
operands whereas the unary operations such as the logical NOT need only a
single operand

• The division operation produces two outputs: a quotient and a remainder

• We need a total of three addresses: two addresses to specify the two input
operands and one to specify where the result should go.

• Most processors use either two or three addresses

NUMBER OF ADDRESSES

•Three-Address Machines
•A = B + C * D - E + F + A
is converted to the following code:
mult T,C,D ; T = C*D
add T,T,B ; T = B + C*D
sub T,T,E ; T = B + C*D - E
add T,T,F ; T = B + C*D - E + F
add A,A,T ; A = B + C*D - E + F + A
NUMBER OF ADDRESSES

•Two-Address Machines
•A = B + C * D - E + F + A
load T,C ;T=C
mult T,D ; T = C*D
add T,B ; T = B + C*D
sub T,E ; T = B + C*D - E
add T,F ; T = B + C*D - E + F
add A,T ; A = B + C*D - E + F + A
NUMBER OF ADDRESSES

• One-Address Machines
• In accumulator machines, most operations are performed on the contents of
the accumulator and the operand supplied by the instruction.

• Thus, instructions for these machines need to specify only the address of a
single operand.

• There is no need to store the result in memory

NUMBER OF ADDRESSES

•Zero-Address Machines
• the locations of both operands are assumed to be at a default location.
• These machines use the stack as the source of the input operands and the
result goes back into the stack
• Stack is a LIFO (last-in–first-out) data structure that all processors
support
• All operations on this type of machine assume that the required input
operands are the top two values on the stack.
NUMBER OF ADDRESSES

• The Load/Store Architecture

• instructions operate on values stored in internal processor registers.
• Only load and store instructions move data between the registers and memory
•X = B + C * D - E + F + A
is converted to the following code:

• load R1,B ; load B

• load R2,C ; load C

• load R3,D ; load D

NUMBER OF ADDRESSES

• load R5,F ; load F

• load R6,A ; load A

• mult R2,R2,R3 ; R2 = C*D

• add R2,R2,R1 ; R2 = B + C*D
• sub R2,R2,R4 ; R2 = B + C*D - E
• add R2,R2,R5 ; R2 = B + C*D - E + F
• add R2,R2,R6 ; R2 = B + C*D - E + F + A
PROCESSOR REGISTERS

• Processors have a number of registers to hold data, instructions, and state

information

• We can divide the registers into general-purpose or special-purpose registers.

• Special-purpose registers can be further divided into those that are accessible to the
user programs and those reserved for the system use.

• RISC processors typically have a large number of registers.

FLOW OF CONTROL

• Program execution, by default, proceeds sequentially

• The program counter (PC) register plays an important role in managing the
control flow

• When an instruction is fetched, the PC is incremented to point to the next

instruction.

• we can use procedure calls to alter the sequential execution.

• processors support flow control both branch and procedure calls.
FLOW OF CONTROL

•Branching
• Branching is implemented by means of a branch instruction. This instruction
carries the address of the target instruction explicitly. Branch instructions in
processors such as the Pentium are also called the jump instructions.

• Branches are one-way jumps: once the control has been transferred to the target
location, computation proceeds from that location (Figure 2.6)

• Processors support two types of branches: unconditional and conditional

FLOW OF CONTROL

•Procedure calls
• The use of procedures facilitates modular programming. Procedure calls are
slightly different from the branches. (Figure 2.7)

• We have to return control to the calling program after executing the procedure.
• This return requires two pieces of information
• End of Procedure: We have to indicate the end of the procedure so that the control can be
returned. This is normally done by a special return instruction.
• Return Address: This piece of information is normally stored when the procedure is called.
MEMORY

• The memory of a computer system consists of tiny electronic switches, with

each switch set in one of two states: 0 and 1. The memory unit consists of
millions of such bits

• Each byte in this memory can be identified by its sequence number starting
with 0, This is referred to as the memory address of the byte. (Fig 2.8)

• The actual memory in a system, however, is always less than or equal to the
memory address space.
TWO BASIC MEMORY OPERATIONS

• The memory unit supports two fundamental operations: read and write. The
read operation reads a previously stored data and the write operation stores a
value in memory.

• Both of these operations require an address in memory from which to read a

value or to which to write a value. (Figure 2.9)

• The address and data of the memory unit are connected to the address and data
buses, respectively. The read and write signals come from the control bus.
TWO BASIC MEMORY OPERATIONS

•Steps in a typical read cycle

• 1. Place the address of the location to be read on the address bus,
• 2. Activate the memory read control signal on the control bus,
• 3. Wait for the memory to retrieve the data from the addressed memory
location and place it on the data bus,

• 4. Read the data from the data bus,

• 5. Drop the memory read control signal to terminate the read cycle.
TWO BASIC MEMORY OPERATIONS

•Steps in a typical write cycle

• 1. Place the address of the location to be written on the address bus,
• 2. Place the data to be written on the data bus,
• 3. Activate the memory write control signal on the control bus,
• 4. Wait for the memory to store the data at the addressed location,
• 5. Drop the memory write signal to terminate the write cycle.
DYNAMIC RAM

• Bits stored as charge in capacitors

• Need refreshing even when powered
• Simpler construction and Less expensive
• Smaller per bit
• Need refresh circuits
• Slower
• Main memory
STATIC RAM

• Bits stored as on/off switches

• No refreshing needed when powered
• More complex construction
• More expensive
• Does not need refresh circuits
• Faster, Cache
• Uses flip-flops
SRAM V DRAM

• Both volatile
• Power needed to preserve data
• Dynamic cell
• Simpler to build, smaller
• More dense
• Less expensive
• Needs refresh
• Larger memory units
• Static
• Faster
TYPES OF ROM
• Written during manufacture. Very expensive
• Programmable (once)
• PROM
• Needs special equipment to program
• Erasable
• Erasable Programmable (EPROM)
• Erased by UV
• Electrically Erasable (EEPROM)
• Takes much longer to write than read
• Flash memory
INPUT / OUTPUT

• I/O devices are not directly connected to the system bus. Instead, there is
usually an I/O controller that acts as an interface between the system and the
I/O device.

• There are two main reasons for using an I/O controller. First, different I/O
devices exhibit different characteristics and, if these devices were connected
directly, the processor would have to understand and respond appropriately to
each I/O device.

• Linux provides a set of system calls to access system I/O devices.

INPUT / OUTPUT

• In Windows, access to I/O devices can be obtained from two layers of system
software: the basic I/O system (BIOS), and the operating system.

• The amount of electrical power used to send signals on the system bus is very
low.

• I/O controllers typically contain driver hardware to send current over long
cables that connect the I/O devices

• I/O controllers typically have three types of internal registers—a data register, a
command register, and a status register.
REFERENCE

• Text book
• https://www.teachict.com/gcse_new/computer%20systems/cpu/miniweb/pg2.htm