UNISONIC TECHNOLOGIES CO.

, LTD
7106 CMOS IC

3½ DIGIT, LCD DISPLAY, A/D

CONVERTERS

„ DESCRIPTION
The UTC 7106 is a high performance, low power,3½ digits A/D
converter. Included are seven segment decoders, display drivers, a
reference, and a clock.
The UTC 7106 is designed to interface with a liquid crystal
display (LCD) and includes a multiplexed backplane drive.
The UTC 7106 bring together a combination of high accuracy,
versatility, and true economy. It features auto zero to less than
10μV, zero drift of less than 1μV/°C, input bias current of 10pA
(Max), and rollover error of less than one count. True differential
inputs and reference are useful in all system, but give the designer
an uncommon advantage when measuring load cells, strain
gauges and other bridge type transducers. Finally, the true
economy of single power supply operation, enables a high
performance panel meter to be built with the addition of only 10
passive components and a display.

„ FEATURES
*Guaranteed Zero Reading for 0V Input On All Scales
*True Polarity At Zero for Precise Null Detection
*1pA Typical Input Current
*True Differential Input And Reference, Direct Drive
LCD Display
*Low Noise-Less than 15μVp-p
*On chip Clock and Reference
*Low Power Dissipation-Typically Less than 10mW
*No Additional Active Circuits Required
*Enhanced Display Stability

„ ORDERING INFORMATION
Ordering Number
Package Packing
Lead Free Halogen Free
7106L-D40-T 7106G-D40-T DIP-40 Tube
7106L-R40-R 7106G-R40-R SSOP-40 Tape Reel
7106L-R40-T 7106G-R40-T SSOP-40 Tube
7106L-QM1-Y 7106G-QM1-Y QFP-44 Tray

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7106 CMOS IC

„ PIN CONFIGURATION

DIP- 40/SSOP-40

V+ 1 40 OSC 1
D1 2 39 OSC 2
C1 3 38 OSC 3
B1 4 37 TEST
, A1 5 36 REF HI
(1 s)
F1 6 35 REF LO
G1 7 34 CREF +
E1 8 33 CREF -
D2 9 32 COMMON
C2 10 31 IN HI
B2 11 30 IN LO
,
(10 s) A2 12 29 A-Z
F2 13 28 BUFF
E2 14 27 INT
D3 15 26 V-
,
, B3 16 25 G2(10 s)
(100 s) F3 17 24 C3
,
E3 18 23 A3 (100 s)
(1000) AB4 19 22 G3
(MINUS) POL 20 21 BP

MQFP - 44

44 43 42 41 40 39 38 37 36 35 34
NC 1 33 NC
NC 2 32 G2
TEST 3 31 C3
OSC 3 4 30 A3
NC 5 29 G3
OSC 2 6 28 BP/GND
OSC 1 7 27 POL
V+ 8 26 AB4
D1 9 25 E3
C1 10 24 F3
B1 11 23 B3
12 13 14 15 16 17 18 19 20 21 22

A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3

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7106 CMOS IC

„ ABSOLUTE MAXIMUM RATINGS(TA=25°C)

PARAMETER SYMBOL RATINGS UNIT
Supply Voltage (V+ ~ V-) VDD 15 V
Analog Input Voltage (Either Input) (Note 1) VI,ANG V+ ~ V- V
Reference Input Voltage (Either Input) VI,REF V+ ~ V- V
Junction Temperature TJ 150 °C
Operating Temperature TOPR 0 ~ +70 °C
Storage Temperature TSTG -65 ~ +150 °C
Note: 1. Input voltages may exceed the supply voltages provided the input current is limited to ±100μA.
2. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
„ THERMAL DATA
PARAMETER SYMBOL RATINGS UNIT
DIP-40 50
Junction to Ambient SSOP-40 θJA 70 °C/W
QFP-44 75

„ ELECTRICAL CHARACTERISTICS (TA=25℃, fCLOCK=48kHz, measured by the circuit of Fig.1)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
SYSTEM PERFORMANCE
Digital
Zero Input Reading RZ VIN=0.0V, Full Scale=200mV -000.0 ±000.0 +000.0
Reading
Digital
Ratio metric Reading RR VIN=VREF, VREF=100mV 999 999/1000 1000
Reading
-VIN=+VIN≒200mV
Difference in Reading for
Rollover Error ER ±0.2 ±1 Counts
Equal Positive and Negative
Inputs Near Full Scale
Full Scale=200mV or Full
Scale=2V Maximum Devi-
Linearity L ±0.2 ±1 Counts
ation from Best Straight Line
Fit (Note 2)
VCM=1V,VIN=0V,
Common Mode Rejection Ratio CMRR 50 μV/V
Full Scale=200mV(Note 2)
VIN=0V,Full Scale=200mV
Noise VN (Peak-To-Peak Value Not 15 μV
Exceeded 95% of Time)
Leakage Current Input IL VIN=0(Note 2) 1 10 pA
Zero Reading Drift DZR VIN=0, 0℃ ~ 70℃ (Note 2) 0.2 1 μV/°C
Scale Factor Temperature VIN=199mV, 0℃ ~ 70℃,
ΦT,S 1 5 ppm/°C
Coefficient (Ext.Ref.0ppm/℃) (Note 2)
End Power Supply Character V+
IEP VIN=0 1.0 1.8 mA
Supply Current
25kΩ Between Common and
COMMON Pin Analog Common
VCOM Positive Supply (With 2.7 3.05 3.3 V
Voltage
Respect to +Supply)
25kΩ Between Common and
Temperature Coefficient of Analog
ΦT,A Positive Supply (With 80 ppm/°C
Common
Respect to +Supply)

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7106 CMOS IC

„ ELECTRICAL CHARACTERISTICS(Cont.)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
DISPLAY DRIVER
Peak-to-Peak Segment Drive Voltage
Peak-to-Peak Backplane Drive VD,PP V+ ~ V-=9V(Note 1) 4 5.5 6 V
Voltage
Note: 1. Back plane drive is in phase with segment drive for”off”segment,180 degrees out of phase for ”on” segment .
Frequency is 20 times conversion rate. Average DC component is less than 50mV.
2. Not tested, guaranteed by design.

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7106 CMOS IC

„ TYPICAL APPLICATIONS AND TEST CIRCUIT

(LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE)

+ -
9V
IN + -
R1 R5
C5
R4 C1 C2 R2 C3 DISPLAY
R3 C4

IN HI 31

BP 21
OSC 1 40
OSC 2 39
OSC 3 38
TEST 37
REF HI 36
REF LO 35
CREF + 34
CREF - 33
COM 32

IN LO 30
A-Z 29
BUFF 28
INT 27
V- 26
G2 25
C3 24
A3 23
G3 22
C1=0.1μF
C2=0.47μF
C3=0.22μF
UTC 7106 C4=100pF
C5=0.02μF
R1=24kΩ

20 POL
19 AB4
7 G1

9 D2
10 C2

15 D3
5 A1

11 B2
12 A2

14 E2

16 B3

18 E3
2 D1
3 C1

F1

13 F2

17 F3
1 V+

4 B1

8 E1

R2=47kΩ
R3=91kΩR
6

4=1kΩ
DISPLAY
R5=1MΩ

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7106 CMOS IC
„ DESIGN INFORMATION SUMMARY SHEET
*OSCILLATOR FREQUENCY
fosc=0.45/RC
COSC>50pF, ROSC>50kΩ
fOSC (Typ)=48kHz

*OSCILLATOR PERIOD
tOSC=RC/0.45
*INTEGRATION CLOCK FREQUENCY
fCLOCK=fOSC/4

*INTEGRATION PERIOD
tINT=1000×(4/fOSC)

*60/50Hz REJECTION CRITERION

tINT/t60Hz or tINT/t50Hz=Integer

*OPTIMUM INTEGRATION CURRENT

IINT=4μA

*FULL SCALE ANALOG INPUT VOLTAGE

VINFS (Typ)=200mV or 2V

*INTEGRATE ESISTOR
RINT= VINFS/ IINT

*INTEGRATE CAPACITOR
CINT=(tINT)(IINT)/ VINT

*INTEGRATOR OUTPUT VOLTAGE SWING

VINT=(tINT)(IINT)/ CINT

*VINT MAXIMUM SWING

(V- + 0.5V)<VINT<(V+ - 0.5V), VINT (Typ)=2V

*DISPLAY COUNT
COUNT=1000×VIN/VREF

*CONVERSION CYCLE
tCYC=tCLOCK×4000
tCYC=tOSC×16,000
When fOSC=48kHz, tCYC=333ms

*COMMON MODE INPUT VOLTAGE

(V- + 1V)<VIN<(V+ - 0.5V)

*AUTO-ZERO CAPACITOR
0.01μF<CAZ<1μF

*REFERENCE CAPACITOR
0.1μF<CREF<1μF

*VCOM
Biased between Vi and V-

*VCOM≒V+ - 2.8V
Regulation lost when V+ to V- <≒6.8V
If VCOM is externally pulled down to (V+ to V-)/2, the VCOM circuit will turn off.

*POWER SUPPLY: SINGLE 9V

V+ - V- =9V
VGND≒V+ - 4.5V
Digital supply is generated by internal parts.

*DISPLAY: LCD
Type: Direct drive with digital logic supply amplitude.

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7106 CMOS IC

„ TYPICAL INTEGRATOR AMPLIFIER OUTPUT WAVEFORM (INT PIN)

„ DETAILED DESCRIPTION
ANALOG SECTION
Fig.1 shows the Analog Section for the UTC 7106. Each measurement cycle is divided into three phases. They
are(1) auto-zero(A-Z), (2)signal integrate (INT)and (3)de-integrate(DE).

AUTO-ZERO PHASE
During auto-zero three things happen. First, input high and low are disconnected from the pins and internally
shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback
loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the
buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited
only by the noise of the system. In any case, the offset referred to the input is less than 10μV.

SIGNAL INTEGRATE PHASE

During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and
low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN
LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. if,
on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to
analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the
integrated signal is determined.

DE-INTEGRATE PHASE
The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and
input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the
capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required
for the output to return to zero is proportional to the input signal. Specifically the digital reading displayed is:

DISPLAY COUNT=1000( VIN/ VREF ).

DIFFERENTIAL INPUT
The input can accept differential voltages anywhere within the common mode range of the input amplifier, or
specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a
CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst
case condition would be a large positive common mode voltage with a near full scale negative differential input
voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the
positive common mode voltage. For these critical applications the integrator output swing can be reduced to less
than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.3V
of either supply without loss of linearity.

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7106 CMOS IC

„ DETAILED DESCRIPTION(Cont.)

DIFFERENTIAL REFERENCE
The reference voltage can be generated anywhere within the power supply voltage of the converter. The main
source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to
stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge
(increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up
to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a
roll-over error. However, by selecting the reference capacitor such that it is large enough in comparison to the stray
capacitance, this error can be held to less than 0.5 count worst case. (See Component Value Selection)

STRAY
CREF STRAY RINT CAZ CINT
BUFFER
CREF + REF HI REF LO CREF - A-Z INT
V+
V+ 34 36 35 33 28 1 29 27
INTEGRATOR
A-Z A-Z
TO
10μ A - - -
DIGITAL
+ 2.8V + +
31 SECTION
IN HI
DE- DE+ A-Z
INT INPUT
6.2V
HIGH

A-Z - COMPARATOR
N +

32 DE+ DE-
COMMON
INT A-Z AND DE(±) INPUT
30 LOW
IN LO

V-

Fig.1 Analog Section

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7106 CMOS IC

„ DETAILED DESCRIPTION(Cont.)
ANALOG COMMON
This pin is included primarily to set the common mode voltage for battery operation (UTC 7106) or for any system
where the input signals are floating with respect to the power supply. The COMMON pin sets a voltage that is
approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery
voltage of about 6V. However, analog COMMON has some of the attributes of a reference voltage. When the total
supply voltage is large enough to cause the zener to regulate(>7V), the COMMON voltage will have a low voltage
coefficient (0.001%/V), low output impedance (≒15Ω), and a temperature coefficient typically less than 80ppm/℃.
The UTC 7106, with its negligible dissipation, suffers from none of these problems. In either case, an external
reference can easily be added, as shown in Fig.2
Analog COMMON is also used as the input low return during auto-zero and de-integrate. If IN LO is different from
analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the
converter. However, in some applications IN LO will be set at a fixed known voltage(power supply common for
instance).In this application, analog COMMON should be tied to the same point, thus removing the common mode
voltage from the converter. The same holds true for the reference voltage. If reference can be conveniently tied to
analog COMMON, it should be since this removes the common mode voltage from the reference system.
Within the IC, analog COMMON is tied to an N-Channel FET that can sink approximately 30mA of current to hold
the voltage 2.8V below the positive supply (when a load is trying to pull the common line positive). However, there is
only 10μA of source current, so COMMON may easily be tied to a more negative voltage thus overriding the internal
reference.

V+ V+

V V
REF HI 6.8k
UTC 7106 20k
REF LO 6.8V
ZENER
REF HI ICL8069
Iz
REF LO 1.2V
REFERENCE
UTC 7106
COMMON
V-
FIGURE 2 A. FIGURE 2B.

Fig.2 Using an External Reference

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7106 CMOS IC

„ DETAILED DESCRIPTION(Cont.)

TEST
The TEST pin serves two function. On the UTC 7106 it is coupled to the internally generated digital supply through
a 500Ω resistor. Thus it can be used as the negative supply for externally generated segment drivers such as
decimal points or any other presentation the user may want to include on the LCD display. Fig.3 and 4 show such an
application. No more than a 1mA load should be applied.
The second function is a “lamp test”. When TEST is pulled high (to V+) all segments will be turned on and the
display should read ”1888”. The TEST pin will sink about 15mA under these conditions.

CAUTION: In the lamp test mode, the segments have a constant DC voltage (no square-wave) . This may burn the
LCD display if maintained for extended periods.

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7106 CMOS IC

„ DETAILED DESCRIPTION(Cont.)
DIGITAL SECTION
Fig.5 show the digital section for the UTC 7106, respectively. In the UTC 7106, an internal digital ground is
generated from a 6V Zener diode and a large P-Channel source follower. This supply is made stiff to absorb the
relative large capacitive currents when the back plane(BP) voltage is switched. The BP frequency is the clock
frequency divided by 800. For three readings/sec, this is a 60Hz square wave with a nominal amplitude of 5V. The
segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase
when ON. In all cases negligible DC voltage exists across the segments.

a a a
a f b f b f b
g g g

b e c e c e c
d d d
BACKPLANE

21

LCD PHASE DRIVER

TYPICAL SEGMENT OUTPUT

V+ 7 7 7
0.5mA
SEGMENT SEGMENT SEGMENT ÷200
DECODE DECODE DECODE
SEGMENT
OUTPUT
LATCH
2mA

INTERNAL DIGITAL GROUND , , , ,

1000 s 100 s 10 s 1s
COUNTER COUNTER COUNTER COUNTER

TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
1
V+
CLOCK
LOGIC 6.2V
* ÷4 CONTROL
500Ω
TEST
INTERNAL 37
DIGITAL VTH=1V
GROUND

* THREE INVERTERS ONE INVERTER SHOWN FOR CLARITY V-

40 39 38 26

OSC 1 OSC 2 OSC 3

Fig.5 Digital Section

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7106 CMOS IC

„ DETAILED DESCRIPTION(Cont.)
SYSTEM TIMING
Fig.6 shows the clocking arrangement used in the UTC 7106. Two basic clocking arrangements can be used:
1. Fig.6A. An external oscillator connected to pin 40.
2. Fig.6B. An R-C oscillator using all three pins.
The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form
the three convert-cycle phases. These are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts)
and auto-zero(1000 ~ 3000 counts). For signals less than full scale. auto-zero gets the unused portion of reference
de-integrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input
voltage. For three readings/second, an oscillator frequency of 48kHz would be used.
To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 33 1/3kHz, etc. should be selected. For 50Hz
rejection, Oscillator frequencies of 200kHz, 100kHz, 66 2/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that
40kHz (2.5 readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz).

INTERNAL TO PART INTERNAL TO PART

÷4 CLOCK
÷4 CLOCK

40 39 38
40 39 38

R C

RC OSCILLATOR
TEST
FIGURE 6A FIGURE 6B

Fig.6 Clock Circuits

COMPONENT VALUE SELECTION

Integrating Resistor
Both the buffer amplifier and the integrator have a class A output stage with 100μA of quiescent current. They can
supply 4μA of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in
this very linear region over the input voltage range, but small enough that undue leakage requirements are not
placed on the PC board. For 2V full scale, 470kΩ is near optimum and similarly a 47kΩ for a 200mV scale.

Integrating Capacitor
The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup
will not saturate the integrator swing(approximately. 0.3V from either supply).In the UTC 7106, when the analog
COMMON is used as a reference, a nominaul+2V full scale integrator swing is fine. For three readings/second
(48kHz clock) nominal values for CINT are 0.22μF and 0.10μF, respectively. Of course, if different oscillator
frequencies are used, these values should be changed in inverse proportion to maintain the same output swing.
An additional requirement of the integrating capacitor is that it must have a low dielectric absorption to prevent
roll-over errors. While other types of capacitors are adequate for this application, polypropylene capacitors give
undetectable errors at reasonable cost.

Auto-Zero Capacitor
The size of the auto-zero capacitor has some influence on the noise of the system. For 200mV full scale where
noise is very important, a 0.47μF capacitor is recommended. On the 2V scale, a 0.047μF capacitor increases the
speed of recovery from overload and is adequate for noise on this scale.

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7106 CMOS IC

„ DETAILED DESCRIPTION(Cont.)
Reference Capacitor
A 0.1μF capacitor gives good results in most applications. However, where a large common mode voltage exists
(i.e., the REF LO pin is not at analog COMMON)and a 200mV scale is used, a larger value is required to prevent
roll-ovre error. Generally 1μF will hold the roll-over error to 0.5 count in this instance.

Oscillator Components
For all ranges of frequency a 91kΩ resistor is recommended and the capacitor is selected from the equation:
f= 0.45/RC for 48kHz Clock (3 Readings/sec), C=100pF.

Reference Voltage
The analog input required to generate full scale output (2000 counts) is: VIN=2VREF.Thus, for the 200mV and 2V
scale, VREF should equal 100mV and 1V, respectively. However, in many applications where the A/D is connected to
a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. For
instance, in a weighing system, the designer might like to have a full scale reading when the voltage from the
transducer is 0.662V. Instead of dividing the input down to 200mV, the designer should use the input voltage directly
and select VREF=0.341V. Suitable values for integrating resistor and capacitor would be 120kΩ and 0.22μF. This
makes the system slightly quieter and also avoids a divider network on the input.

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7106 CMOS IC

„ TYPICAL APPLICATIONS

The UTC 7106 may be used in a wide variety of configurations. The circuits which follow show some of the
possibilities, and serve to illustrate the exceptional versatility of these A/D converters.

TO PIN 1
OSC 1 40
91kΩ
OSC 2 39
OSC 3 38 SET VREF
TEST 37 100pF =100mV

REF HI 36
REF LO 35
1kΩ 22kΩ
CREF+ 34
0.1μF
CREF- 33
COMMON 32
1MΩ +
IN HI 31
0. 01μF IN
IN LO 30
0. 47μF -
A-Z 29 +
47kΩ 9V
BUFF 28
-
INT 27
0. 22μF
V- 26
G2 25
C3 24
TO DISPLAY
A3 23
G3 22
BP 21 TO BACKPLANE

Values shown are for 200mV full scale,3 readings/sec.,floating

supply voltage(9V battery).

Fig.7 Using The Internal Reference

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7106 CMOS IC

„ TYPICAL APPLICATIONS(Cont.)

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7106 CMOS IC

„ TYPICAL APPLICATIONS(Cont.)

TO PIN 1
OSC1 40
91kΩ
OSC2 39
OSC3 38 SCALE
TEST 37 100pF FACTOR
REF HI 36 ADJUST
REF LO 35 22kΩ
C REF+ 34 100kΩ 1MΩ
µ 100kΩ 220kΩ
CREF- 33 0.1 F
COMMON 32
ZERO
IN HI 31 ADJUST SILICON NPN
0.01µF
IN LO 30 MPS 3704 OR
0 . 47µ F SIMILAR
A-Z 29
47 kΩ 9V
BUFF 28
INT 27
V- 26 0 . 22µF

G2 25
C3 24 TO DISPLAY
A3 23
G3 22
BP 21 TO BACKPLANE

A sillicon diode- connected transistor has a temperature coefficient of about -2 mV/ .

Calibration is achieved by placing the sensing transistor in ice water and adjusting the
.
zeroing potentiometer for a 000.0 reading. The sensor should then be placed in boiling
water and the scale - factor potentiometer adjusted for a 100.0 reading

Fig.9 Used as A Digital Centigrade Thermometer

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7106 CMOS IC

„ TYPICAL APPLICATIONS(Cont.)

V+
1 V+ OSC1 40
2 D1 OSC2 39
TO 3 C1 OSC3 38
LOGIC
VDD 4 B1 TEST 37
5 A1 REF HI 36
6 F1 REF LO 35 TO
LOGIC
7 G1 CREF+ 34
GND
8 E1 CREF- 33
9 D2 COMMON 32
10 C2 IN HI 31
11 B2 IN LO 30
12 A2 A-Z 29
13 F2 BUFF 28
14 E2 INT 27
15 D3 V- 26 V-
16 B3 G2 25
17 F3 C3 24
O/RANGE
18 E3 A3 23
19 AB4 G3 22
20 POL BP 21
U/RANGE

CD4077

Fig.10 Circuit for Developing Underrange and Overrange from UTC 7106 Outputs

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7106 CMOS IC

„ TYPICAL APPLICATIONS(Cont.)

TO PIN 1
OSC 1 40
91kΩ
OSC 2 39 10μF SCALE FACTOR ADJUST
38 (VREF=100mV FOR AC TO RMS)
OSC 3
100pF CA3140
37 100kΩ
TEST 5μF +
REF HI 36 AC IN
-
REF LO 35 1N914
CREF 34 1kΩ 22kΩ 470kΩ
0.1μF
CREF 33 2.2MΩ
10kΩ
COMMON 32 1μF 10kΩ 1μF 1μF
IN HI 31 0.22μF
4.3kΩ
IN LO 30
0.47μF
A-Z 29 +
47kΩ
BUFF 28 10μF 9V 100pF
INT 27 - (FOR OPTIMUM BANDWIDTH)
0.22μF
V- 26
G2 25
C3 24
TO DISPLAY
A3 23
G3 22
BP 21 TO BACKPLANE

Test is used as a common-mode reference level to ensure compatiblity with most op amps.

Fig. 11 AC to DC Converter with UTC 7106

UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
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