EE537 Circuit Simulation Lab

Experiment 6(b)

Name: Ahmad Raza Ansari

ID Number: 2024EEM1016 October 17, 2024

AIM: Design a differential amplifier with resistive load, tail current source of ab ∗ (10) µA,
where a and b are the last two digits of your entry number. The ICMR should be 1.2 V, f3dB < 1
MHz and maximize the voltage gain and minimize the common mode gain. Use a load capacitor at
the output to bandlimit the amplifier. Bias the tail current source by using the available reference
current of IREF = 10 µA.

After some calculations, I got the aspect ratio of this circuit and sketched it in cadence as shown
in Figure 1. I took care the current in the circuit passes through should be equal to 160 µA I show
the calculation below that I did for making this circuit.

Figure 1: Design of differential amplifier with resistive load

Calculations for drawing the above circuit.

The equation 1 is the main for finding the aspect ratio of MOSFET and resistance value all these
things start from this equation.
I SS
V GS1 + (V GS3 − V TH3 ) ≤ V in,cm ≤ min(V DD − RD + V TH , V DD ) (1)
2
I SS
V DD − RD + V TH = 1.8
2
Given Values :
VT H = 0.5V.
ISS = 160µA
After substitution, we get RD = 6.25 KΩ.

1
1 Show the plots verifying obtained swing, ICMR, differential
gain, and common mode gain.
We can look at the circuit as shown in Figure 2. I have got DC operating point after hand
calculation all the transistors are in saturation and the current is also matching the required value.

Figure 2: Design of differential amplifier with resistive load

Hand Calculation
We are going to calculate the aspect ratio for all the transistors. ICMR formula as shown in 2.

ICM R = V inCM(MAX) − V inCM(MIN) (2)

We also know that

ICM R = 1.2V
VinCM (M AX) = 1.8V
VinCM (M IN ) = VGS1 + (VGS3 − VT H3 )
Now we can get the equation after substituting this in equation 2.

V GS1 + (V GS3 − V TH ) = 0.6V (3)

I substitute the value in equation 3 that is

VGS1 = 0.55V

VGS3 − VT H = 0.05V
We know the current trough M3 is 160 µA. and also we know that M3 is in saturation.

µn Cox W (VGS3 − VT H )2
IDS3 =
2L

2
 We know the values of components:

µn Cox = 320µA/V 2

VGS3 − VT H = 0.05V
W 400
( )3 =
L 1
By Current mirror :
(W
L )3
ISS = IREF
(W
L )4

Since we know the value of IREF = 10µA , ISS = 160µA and ( W

L )3 =
400
1 after substituting this
value in current mirror equation we got
W 25
( )4 =
L 1
ISS
We know that current through M1 and M2 are same and that is 2 . Now we are equating
ID1 ,ID2 equal to ISS
2 .
µn Cox W (VGS1 − VT H )2
ID1,2 =
2L
From this, I got
W 213
( )1,2 =
L 1

Output
From the simulation, I got ICMR = 1.14 V simulation result as shown in figure 3. That is not
exactly equal to the theoretical value of the ICMR, which varies slightly.

Figure 3: ICMR from plot.

3
 Differential Gain:
The gain is typically configured to amplify the difference between the two input signals while reject-
ing any signals that are common to both inputs (common-mode signals). This property is known
as common-mode rejection. I got a differential gain of 19.1 dB as shown in figure 4.

Figure 4: Differential gain.

Common mode gain:

Common-mode gain (Acm ) is a measure of how much a differential amplifier amplifies signals that
are present simultaneously and equally on both inputs. Essentially, it quantifies the amplifier’s
response to common-mode signals, which can be noise or interference that affects both input ter-
minals’ common mode gain as shown in figure 5.

Figure 5: Common mode gain

4
2 Compare the PSD of input-referred noise with the PSD of noise
observed in the previous question. What is the effect of power
on PSD ? Also, calculate the integrated input-referred noise.
New PSD: The scale reaches approximately 2.7 V²/Hz for output noise, while input noise remains
relatively low and flat.
Previous PSD: The scale extends up to 900 V²/Hz, with both input and output noise having a
similar flat trend at high frequencies.
New PSD: There is a sharp decrease in output noise at lower frequencies, leveling off at higher
frequencies. Input noise remains constant across all frequencies.
Previous PSD: The output noise has a similar sharp drop at lower frequencies, but the values are
significantly larger compared to the new PSD. Input noise shows a similar trend as in the new PSD,
but is represented more clearly with a distinct curve as shown in figure 6.

(a) Previous PSD (b) New PSD

Figure 6: PSD

Effect of power on PSD ?

Higher power generally leads to higher PSD because it increases the energy content across the
frequency spectrum, either in the signal or the noise. Power-efficient systems try to keep power
low to minimize noise (and thus the PSD) while still delivering adequate signal strength. Increased
noise power, particularly due to thermal effects or bias conditions in devices, will manifest as a
higher PSD in the noise response of a system.
Integrated noise:
Integrated noise is the total noise power over a specific bandwidth, calculated by integrating the
Power Spectral Density (PSD) over the frequency range of interest. It gives the cumulative noise
contribution across all frequencies as shown in figure 7.

Figure 7: Integrated Noise

5
3 Design a differential amplifier with current mirror load, tail
current source of ab ∗ (10)µA, where a and b are last two digits of
your entry number. The ICMR should be 0.8 V, fugb ≤ 40MHz
and maximize the voltage gain and minimize the common mode
gain. The gm/Id ratio of input transistors should be less than
10. Bias the tail current source by using the available reference
current of IREF = 10µA.
I have drawn this circuit as given in the experiment as shown in figure 8. We can see in the figure
that I got the current for the DC operating point and that all transistors are in saturation too this
circuit is a combination of OTA and current mirror circuit.

Figure 8: Differential amplifier with current mirror load

Calculation
For calculating CL we use the given condition.

f ugb ≥ 40M Hz (4)

We know that
gm
fugb =
2πCL
Given values:

gm = 1.46A/V

C L = 5.8f F (5)
we got the CL after a calculation is 5.8 fF as shown in equation 5.

6
3.1 Show the plots verifying obtained swing, ICMR, differential gain, and com-
mon mode gain.
We know the theoretical ICMR of the circuit is 0.8V. I got the ICMR through a calculation is
1.41V. we first get AvDM and change it to dB after that I take a horizontal from a flat band below
3 dB mark the point on the graph and calculate ICMR as shown in 9.

ICM R = 1.37V − 0.19V

ICM R = 1.41V

Figure 9: ICMR of differential amplifier with current mirror load

Differential Gain:
I got a differential gain is 50.9 dB for this circuit as shown in Figure 10. In this circuit we are using
active load instead of resistor that’s the reason why gain is increased. Active loads can provide
better linearity over a wider range of input signals. This helps maintain gain consistency across
various operating conditions, contributing to a more reliable and predictable gain.

Figure 10: Differential gain with current mirror load

7
 Common mode gain :

Active Load Configuration: Commonly, active loads in differential amplifiers are implemented
using current mirrors or other transistor configurations. These setups typically have high output
impedance, which can affect how the amplifier responds to common-mode signals. The common-
mode gain of a differential amplifier with an active load as shown in figure 11 is typically small but
non-zero due to mismatches and other real-world effects. The design choices significantly impact
both the common-mode gain and the overall performance of the amplifier.

Figure 11: Common mode gain with current mirror load

3.2 What is the step input voltage at which this amplifier connected as a unity
gain voltage buffer starts to slew?
The slew rate (SR) is the maximum rate of change of the output voltage per unit of time, typically
specified in volts per microsecond. When the rate of change of the input voltage exceeds the slew
rate, the amplifier’s output won’t be able to follow the input, and the output will be slew at the
maximum rate determined by the slew rate. Op amps used in feedback circuits exhibit a large-
signal behavior called “slewing.” We first describe an interesting property of linear systems that
vanishes during slewing.
Slewing is an undesirable effect in high-speed circuits that process large signals. While the small-
signal the bandwidth of a circuit may suggest a fast time-domain response, the large signal speed
may be limited by the sew rates implied because the current available to charge and discharge the
dominant capacitor in the circuit is small. Moreover, since the input-output relationship during
slewing is nonlinear, the output of a slewing amplifier exhibits substantial distortion.

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3.3 Calculate the output pole, mirror pole, and mirror zero. Compare the
calculated and simulated values using pz analysis.
I am trying to drive the equation of pole and zero. Pole:
The output pole is determined by the output capacitance and the impedance seen at the output
node.
Rout ≈ (ro3 ||ro4 )
1
wout =
Rout CL

The mirror pole arises from the high-impedance node at Vm , where the current mirror is located.
This node typically has parasitic capacitance. The impedance at node Vm is largely determined by
the output resistance of M3 , ro3 since it mirrors the current from the differential pair. The parasitic
capacitance at this node, Cpar comes from the overlap and junction capacitances.
1
wm =
ro3 Cpar

Zero:
In current mirrors, zeros may arise due to feedforward paths in the circuit, typically at higher fre-
quencies. For instance, in this configuration, a mirror zero might occur due to the direct capacitive
coupling from the input to the output through the mirror transistors M3 , M4 .

Figure 12: Poles and Zero of differential amplifier with current mirror load