Scribd
Upload
19 views

2.2.2.a UniversalGatesNANDLogicDesign

2.2.2 Answers Digital Electronics

Uploaded by

Jalapeñojones79 M
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
19 views

2.2.2.a UniversalGatesNANDLogicDesign

2.2.2 Answers Digital Electronics

Uploaded by

Jalapeñojones79 M
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 6

Activity 2.2.

2 Universal Gates:
NAND Only Logic Design
Introduction
The block diagram shown below represents a voting booth monitoring system. For privacy
reasons, a voting booth can only be used if the booth on either side is unoccupied. The
monitoring system has four inputs and two outputs. Whenever a voting booth is occupied, the
corresponding input (A, B, C, & D) is a (1). The first output, Booth, is a (1) whenever a voting
booth is available. The second output, Alarm, is a (1) whenever the privacy rule is violated.

Booth Booth Booth Booth


A B C D

Booth
Voting Booth
Monitoring
System
Alarm

In this activity you will implement NAND only combinational logic circuits for the two outputs
Booth and Alarm. These NAND only designs will be compared with the original AOI
implementations in terms of efficiency and gate/IC utilization. In a future activity, these NAND
only designs will be compared to the circuits implemented using only NOR gates.

Equipment
 Circuit Design Software (CDS)
 Breadboard (DMS or DLB)
 #22 Gauge solid wire
 Integrated Circuits (74LS00)

© 2014 Project Lead The Way, Inc.


Digital Electronics Activity 2.2.2 Universal Gates: NAND Only Logic Design – Page 1
Procedure
For the sake of time, the truth table and K-Maps for the voting booth monitor systems have
been completed for you. Note, for the output Booth we took advantage of several don’t care
conditions.

A B C D Boot Alar
h m
0 0 0 0 1 0
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 X 1
0 1 0 0 1 0
0 1 0 1 0 0
0 1 1 0 X 1
0 1 1 1 X 1
1 0 0 0 1 0
1 0 0 1 0 0
1 0 1 0 0 0
1 0 1 1 X 1
1 1 0 0 X 1
1 1 0 1 X 1
1 1 1 0 X 1
1 1 1 1 X 1

© 2014 Project Lead The Way, Inc.


Digital Electronics Activity 2.2.2 Universal Gates: NAND Only Logic Design – Page 2
1. In the space provided, draw the AOI circuits that implement the simplified logic
expressions Booth and Alarm. Limit this implementation to only 2-input AND gates
(74LS08), 2-input OR gates (74LS32), and inverters (74LS04).

Booth – AOI

© 2014 Project Lead The Way, Inc.


Digital Electronics Activity 2.2.2 Universal Gates: NAND Only Logic Design – Page 3
Alarm – AOI

2. Re-implement these circuits assuming that only 2-input NAND gates (74LS00) are
available. Draw these circuits in the space provided.

Booth – NAND

© 2014 Project Lead The Way, Inc.


Digital Electronics Activity 2.2.2 Universal Gates: NAND Only Logic Design – Page 4
Alarm – NAND

3. Using the CDS, enter and test the two logic circuits that you designed. Use switches for
the inputs A, B, C, and D and a probe or LED circuit for the outputs Booth and Alarm.
Verify that the circuits are working as expected. Print a copy of the circuit and attach it
below. Note: Even though the two circuits work independently, they are part of one
design and should be simulated, tested, and prototyped together.

© 2014 Project Lead The Way, Inc.


Digital Electronics Activity 2.2.2 Universal Gates: NAND Only Logic Design – Page 5
Booth & Alarm – CDS

4. Using the DLB, build and test the NAND logic circuits that you designed and simulated.
Verify that the circuits are working as expected and the results match the results of the
simulation.

Conclusion
1. For your AOI implementations, how many ICs (i.e., 74LS04, 74LS08, and 74LS32
chips) were required to implement your circuits? Note: You’re not just counting the
number of gates used, but rather, the number of IC, in whole or part, that were
required.

2. For your NAND implementations, how many ICs (i.e., 74LS00 chips) were required to
implement your circuits? Again, we are counting ICs, not gates.

3. In terms of hardware efficiency, how does the NAND implementation compare to the
AOI implementation?

4. NAND gates are available with three inputs (74LS10) and four inputs (74LS20). Could
either of these chips have been used for this design? If so, how would it have affected
the efficiency of the design?

© 2014 Project Lead The Way, Inc.


Digital Electronics Activity 2.2.2 Universal Gates: NAND Only Logic Design – Page 6

You might also like