Data Sheet

AD4080
20-Bit, 40 MSPS, Differential SAR ADC

FEATURES FUNCTIONAL BLOCK DIAGRAM

► High performance
► Throughput: 40 MSPS, 46.25 ns conversion latency
► INL: ±4 ppm (typical), ±8 ppm (maximum)
► SNR/THD
► 93.6 dB (typical)/−110 dB (typical) at fIN = 1 kHz
► 93.5 dB (typical)/−104 dB (typical) at fIN = 1 MHz
► Noise spectral density: −167.6 dBFS/Hz
► 20-bit resolution, no missing codes
► Low power
► 79.3 mW typical at 40 MSPS with −0.5 dBFS sine-wave input Figure 1. AD4080 Functional Block Diagram
► Easy Drive, fully differential Input
► 6 V p-p differential input range GENERAL DESCRIPTION
► Continuous signal acquisition The AD4080 is a high-speed, low noise, low distortion, 20-bit, Easy
► Linearized, 5 μA/MSPS input current Drive, successive approximation register (SAR) analog-to-digital
► Integrated, low-drift reference buffer and decoupling converter (ADC). Maintaining high performance (signal-to-noise and
► Integrated VCM generation distortion (SINAD) ratio > 90 dBFS) at signal frequencies in excess
► Digital features and data interface of 1 MHz enables the AD4080 to service a wide variety of precision,
wide bandwidth data acquisition applications. Simplification of the
► Conversion result FIFO, 16K sample depth
input anti-alias filter design can be accomplished by applying over-
► Digital averaging filter with up to 210 decimation sampling along with the integrated digital filtering and decimation to
► SPI configuration reduce noise and lower the output data rate for applications that do
► Configurable data interface not require the lowest latency of the AD4080.
► Single lane, DDR, serial LVDS, 800 MBPS per lane
The AD4080 Easy Drive features reduce both signal chain com-
► Dual lane, DDR, serial LVDS, 400 MBPS per lane plexity and power consumption while enabling greater channel
► Single/quad lane SPI data interface density and flexibility in companion component selection. The prod-
► Package uct input structure was designed to minimize any input dependent
► 49-ball, 5 mm x 5 mm CSP_BGA, 0.65 mm pitch signal currents; therefore, reducing any converter induced settling
► Integrated supply decoupling capacitors
artifacts. The continuous acquisition architecture allows settling
across the entire conversion cycle, easing ADC driver settling and
► Operating temperature range: −40°C to +85°C bandwidth requirements as compared to other high-speed data
APPLICATIONS converters.
The AD4080 includes several elements that simplify data converter
► Digital imaging integration: a low drift reference buffer, low dropout (LDO) regula-
► Cell analysis tors to generate ADC core and digital interface supply rails, and a
► Spectroscopy 16K result data first-in first out (FIFO) that can greatly reduce the
► Automated test equipment load on the digital host. Additionally, critical supply and reference
► High speed data acquisition decoupling capacitors are integrated in the package to ensure
► Digital control loops, hardware in the loop optimum performance, simplify printed circuit board (PCB) layout,
and reduce the overall solution footprint.
► Power quality analysis
► Source measurement units
► Electron and x-ray microscopy
► Radar level measurement
► Nondestructive test
► Predictive maintenance and structural health
Rev. 0
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Data Sheet AD4080
TABLE OF CONTENTS

Features................................................................ 1 Software Reset.................................................26

Applications........................................................... 1 Applications Information...................................... 27
Functional Block Diagram......................................1 Typical Applications Diagrams......................... 27
General Description...............................................1 Analog Front End Design................................. 28
Specifications........................................................ 3 Reference Circuitry Design.............................. 29
Timing Specifications......................................... 6 Data Interface Clocking Solution...................... 29
Absolute Maximum Ratings...................................8 Power Solution................................................. 30
Thermal Resistance........................................... 8 Digital Interface....................................................31
Electrostatic Discharge (ESD) Ratings...............8 Overview.......................................................... 31
ESD Caution.......................................................8 SPI Configuration Interface.............................. 31
Pin Configuration and Function Descriptions........ 9 LVDS Data Interface.........................................43
Typical Performance Characteristics................... 12 SPI Data Interface............................................ 50
Terminology......................................................... 17 GPIO Pins........................................................ 51
Theory of Operation.............................................18 Digital Features................................................... 53
Product Overview............................................. 18 Overview.......................................................... 53
Converter Operation.........................................18 Event Detection................................................ 53
Transfer Function............................................. 19 Result FIFO...................................................... 55
Easy Drive Analog Inputs ................................ 19 Digital Filter...................................................... 64
Reference Buffer and Common-Mode Output..21 System Error Correction Coefficients............... 71
Power Supplies................................................ 21 Layout Guidelines................................................72
Internally Regulated Supply Configuration....... 22 Configuration Registers....................................... 73
Externally Generated Supply Configuration..... 22 Register Details................................................ 75
Power-On Reset (POR) Monitor.......................22 Outline Dimensions............................................. 95
Power Supply Sequence.................................. 23 Ordering Guide.................................................95
Power Saving Operating Modes.......................24 Evaluation Boards............................................ 95

REVISION HISTORY

3/2024—Revision 0: Initial Version

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Data Sheet AD4080
SPECIFICATIONS

VDD33 = 3.3 V ± 5%, VDDLDO = 1.5 V to 2.7 V, VDD11 = 1.1 V ± 5%, IOVDD = 1.1 V − 5% to 1.2 V + 5%, voltage reference input (VREFIN) =
3.0 V, sampling frequency (fS) = 40 MHz, and TA = TMIN to TMAX, unless otherwise noted.

Table 1. Specifications
Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 20 Bits
ANALOG INPUT
Absolute Operating Input Voltage Voltage at input, referred to GND −0.1 VDD33 + 0.1 V
Differential Input Voltage Range IN+ voltage − IN− voltage −VREFIN +VREFIN V
Common-Mode Input Range VREFIN/2 − 0.05 VREFIN/2 VREFIN/2 + 0.05 V
DC PERFORMANCE
No Missing Codes 20 Bits
Differential Nonlinearity (DNL) ±0.5 ±0.99 LSB
Integral Nonlinearity (INL) ±4 ±8 ppm
Transition Noise 6.9 LSB RMS
Gain Error TA = 25°C 0.01 ±0.025 %FS
Gain Error Drift 0.095 ppm/°C
Zero Error TA = 25°C 15 μV
Zero Error Drift TA = −40°C to +85°C 0.05 ppm/°C
Power Supply Rejection VDD33 = 3.3 V ± 5% −89 dB
VDD11 = 1.1 V ± 5% −68 dB
Low Frequency Noise Bandwidth = 0.1 Hz to 10 Hz 174 nV RMS
AC PERFORMANCE
Dynamic Range 94.6 dB
Noise Spectral Density (NSD) 167.6 dBFS/Hz
Total RMS Noise Bandwidth = 20 MHz 39.4 μV RMS
Signal-to-Noise Ratio (SNR) Voltage magnitude (VMAG) = −0.5 dBFS, input 92.7 93.6 dB
frequency (fIN) = 1 kHz
VMAG = −1 dBFS, fIN = 1 MHz 93.5 dB
Sinc5 + compensation filter, decimate by 8, VMAG = 101.7 102.5 dB
−0.5 dBFS, fIN = 1 kHz,
Total Harmonic Distortion (THD) VMAG = −0.5 dBFS, fIN = 1 kHz −110 −101.7 dB
VMAG = −1 dBFS, fIN = 1 MHz −104 dB
Signal-to-Noise-and-Distortion (SINAD) VMAG = −0.5 dBFS, fIN = 1 kHz 93.3 dB
VMAG = −0.5 dBFS, fIN = 1 MHz 93 dB
Spurious-Free Dynamic Range −112 dB
−3 dB Bandwidth Input at IN+ and IN−, no external filter 272 MHz
Intermodulation Distortion (IMD) Frequency A (fA) = 1.0 MHz, Frequency B (fB) =
800 kHz
Second-Order IMD (IMD2) −96.2 dB
Third-Order IMD (IMD3) −97.2 dB
Power Supply Rejection Ripple voltage = 50 mV p-p, f = 1 kHz
VDD33 −92.5 dB
VDD11 −81.2 dB
REFERENCE INPUT
VREFIN Range 2.995 3.0 3.005 V
VREFIN Current −0.3 +1 μA/MSPS
TA = 25°C −6.3 +26.9 μA
VREFIN Leakage Current Converter Idle −2 +2 μA

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Data Sheet AD4080
SPECIFICATIONS

Table 1. Specifications (Continued)

Parameter Test Conditions/Comments Min Typ Max Unit
COMMON-MODE OUTPUT (CMO)
Absolute Output Voltage VREFIN = 3.0 V 1.48 1.51 V
Noise Bandwidth = 7.4 MHz 71 μV RMS
Noise Spectral Density 26.1 nV/√Hz
LOW DROPOUT REGULATORS (VDD11, VIO11)
Input Voltage Range 1.4 2.7 V
Output Voltage TA = 25°C, VDDLDO = 1.8 V 1.1 V
Start-Up Time 10 μs
LOW VOLTAGE DIFFERENTIAL SIGNALING
(LVDS) INPUT AND OUTPUT (EIA-644)
Data Format Serial LVDS data output Twos complement
LVDS Inputs (CLK± and CNV±) IOVDD supply domain inputs.
Common-Mode Input Voltage, VICM Default setting 700 1400 mV
Differential Input Voltage, VIDIFF Default setting 100 600 mV
LVDS Outputs (DCO±, DA±, and DB±) IOVDD supply domain outputs, differential
termination, load resistance (RL) = 100 Ω
Common-Mode Output Voltage, VOCM LVDS_VOD = 001b 915 927 935 mV
LVDS_VOD = 010b (default) 840 851 860 mV
LVDS_VOD = 100b 695 706 715 mV
Differential Output Voltage, VODIFF LVDS_VOD = 000b 370 395 420 mV
LVDS_VOD = 010b (default) 500 530 560 mV
LVDS_VOD = 100b 740 785 830 mV
DIGITAL INPUTS (CNV, CS, SCLK, and SDI) VDD11 supply domain inputs
Input Voltage Tolerance 0 2.5
Logic Levels
Input Low Voltage, VIL 0 0.36 × VDD11
Input High Voltage, VIH 0.73 × VDD11 2.5
DIGITAL INPUTS (GPIOx, DCS, and DCLK) IOVDD supply domain inputs
Input Voltage Tolerance 0 1.26 V
Logic Levels
Input Low Voltage, VIL 0 0.36 × IOVDD V
Input High Voltage, VIH 0.73 × IOVDD IOVDD V
Input Current
Input Low Current, IIL −1 +1 μA
Input High Current, IIH −1 +1 μA
Input Pin Capacitance 4.5 pF
DIGITAL OUTPUTS (GPIOx) IOVDD supply domain outputs
Logic Levels
Output Low Voltage, VOL Sink current (ISINK) = 500 μA 0 0.15 V
Output High Voltage, VOH Source current (ISOURCE) = 500 μA IOVDD − 0.115 IOVDD V
DIGITAL OUTPUTS (SDOx) IOVDD supply domain outputs.
Data Format Configured as serial data output Twos complement
Logic Levels
VOL ISINK = 500 μA 0.15 V
VOH ISOURCE = 500 μA IOVDD − 0.115 IOVDD V

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Data Sheet AD4080
SPECIFICATIONS

Table 1. Specifications (Continued)

Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLIES
VDD33 3.135 3.30 3.465 V
VDDLDO 1.4 2.7 V
VDD11 Applied externally, LDO disabled 1.045 1.10 1.155 V
IOVDD Applied externally, LDO disabled 1.045 1.10 1.26 V
Operating Current LVDS_CNV_EN = 0
Static Converter and interface idle, FIFO disabled
VDD33 5.4 7 mA
VDDLDO VDD11 LDO disabled 0 0.02 mA
VDD11 15.3 23 mA
IOVDD 5.2 6 mA
VDDLDO VDD11 LDO enabled 21.5 26.5 mA
Dynamic DC input signal
VDD33 15.7 18 mA
VDDLDO VDD11 LDO disabled 0 0.02 mA
VDD11 23.2 32 mA
IOVDD 6 7.5 mA
VDDLDO VDD11 LDO enabled 29.8 35.5 mA
Dynamic −0.5 dBFS sine-wave input signal
VDD33 14.2 16 mA
VDDLDO VDD11 LDO disabled 0 0.02 mA
VDD11 23.2 32 mA
IOVDD 6.3 7.5 mA
VDDLDO VDD11 LDO enabled 30.2 35.5 mA
Standby Mode
VDD33 1.4 1.9 mA
VDDLDO VDD11 LDO disabled 0 0.02 mA
VDD11 12 5.5 mA
IOVDD 2.6 3.5 mA
VDDLDO VDD11 LDO enabled 1.8 5 mA
Sleep Mode
VDD33 0.6 0.9 mA
VDDLDO VDD11 LDO disabled 0 0.02 mA
VDD11 1.2 5.5 mA
IOVDD 2.6 3.5 mA
VDDLDO VDD11 LDO enabled 1.5 4.5 mA
Power Dissipation
Static VDD11 LDO disabled 40.4 58.4 mW
Dynamic DC input signal 83.9 108.8 mW
Dynamic −0.5 dBFS sine-wave input signal 79.3 101.9 mW
Standby Mode VDD11 LDO disabled 10.6 19.5 mW
Sleep Mode VDD11 LDO disabled 6.2 13.9 mW
TEMPERATURE RANGE
Specified Performance TMIN to TMAX −40 +85 °C

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Data Sheet AD4080
SPECIFICATIONS

TIMING SPECIFICATIONS
VDD33 = 3.3 V ± 5%, VDDLDO= 1.5 V to 2.7 V, VDD11 = 1.1 V ± 5%, IOVDD = 1.1 V − 5% to 1.2 V + 5%, VREFIN = 3.0 V, fS = 40 MHz, and TA
= TMIN to TMAX unless otherwise noted.

Table 2. Timing Specifications

Parameter Symbol Min Typ Max Unit
Sampling Frequency fS 1.25 40 MHz
Conversion Time tCONV 25 800 ns
Acquisition Phase tACQ tCYC ns
Conversion Cycle Period tCYC tCONV ns
LVDS Data Interface
Data Interface Clock Count N 10
Active Data Lane Count L 2
CNV± High Time tCNVH tCLK 5 × tCLK tCYC − tCNVL ns
CNV± Low Time tCNVL tCLK 5 × tCLK tCYC − tCNVH ns
CNV± Edge to CLK± Rising Edge Alignment tCCA 535 ps
CNV± to Dx± (MSB) Ready tMSB
Gain Error Correction Enabled 20.5 22.4 ns
Gain Error Correction Disabled 15.7 18 ns
CLK± Period tCLK 2.5 tCYC × L/N ns
CLK± Frequency fCLK 1/tCLK 400 MHz
CLK± to Dx± Delay tCLKD 2.1 ns
CLK± to DCO± Delay (Echo Clock Mode) tDCO 2 ns
DCO± to Dx± Delay (Echo Clock Mode) tDCOD 1 ns
Serial Peripheral Interface (SPI) Data Interface
Data Interface Clock Count, Single Conversion Result M 24
Active Data Lane Count C 1 4
Data Interface Chip Select Falling Edge (DCS) to SDOB Data Valid tDEN 5 6 ns
Data Interface Clock Period (DCLK) tDCK 20 ns
Data Interface Clock Low Pulse Width (DCLK) tDCKL tDCK × 0.45 ns
Data Interface Clock High Pulse Width (DCLK) tDCLKH tDCK × 0.45 ns
Data Interface Clock Falling Edge to Data Remains Valid Delay tDHSDO 5 ns
Data Interface Clock Falling Edge to Data Valid Delay tDDSDO 9.6 ns
DCLK Rising to Data Interface Chip Select Falling tDCKEN 0 ns
Data Interface Chip Select High to DCLK Disabled tDCLKDIS 0 ns
Data Interface Chip Select High Between Frames tDCSMIN (tDCKEN + tDCLKDIS) + 0.5 × ns
tDCLK
Serial Configuration Interface
SCLK Period tSCK 20 ns
SCLK Low Pulse Width tSCKL tSCK × 0.45 ns
SCLK High Pulse Width tSCKH tSCK × 0.45 ns
SCLK Falling Edge to Data Remains Valid Delay tHSDO 0.7 ns
SCLK Falling Edge to Data Valid Delay tDSDO 14.5 ns
CS Falling Edge to SCLK tCSSCK 0 ns
Last SCLK to CS Rising tSCKCS 0 ns
SDI Valid Setup Time Before SCLK Rising Edge tSSDI 1 ns
SDI Valid Hold Time After SCLK Rising Edge tHSDI 0 ns
SCLK Rising to Data Interface Chip Select Falling tSCKEN 0 ns

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Data Sheet AD4080
SPECIFICATIONS

Table 2. Timing Specifications (Continued)

Parameter Symbol Min Typ Max Unit
Data Interface Chip Select High to SCLK Disabled tSCKDIS 0 ns
Data Interface Chip Select High to SDO Disabled tCSDIS 10.3 ns
Data Interface Chip Select High Between Frames tCSMIN (tSCKEN + tSCKDIS) + 0.5 × tSCK ns
Digital Filter
FILT_SYNC Rising Edge to CNV Rising Edge tSYNC MAX 14 ns
CNV Rising Edge to FILT_SYNC Falling Edge tSYNC MIN 5 5 ns
Event Detection
Input Threshold Crossed to ALERT Asserted tEVT 2 × tCYC 3 × tCYC

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Data Sheet AD4080
ABSOLUTE MAXIMUM RATINGS

Table 3. Absolute Maximum Ratings THERMAL RESISTANCE

Parameter Rating
Thermal performance is directly linked to PCB design and operating
Analog Inputs environment. Careful attention to PCB thermal design is required.
IN+, AUXIN+, IN−, and AUXIN− to GND −0.3 V to +3.6 V
Analog Output θJA is the natural convection junction to ambient thermal resistance
CMO −0.3 V to +3.6 V measured in a one cubic foot sealed enclosure. θJC is the junction
Supply Voltage to case top thermal resistance.
REFIN and VDD33 to GND −0.3 V to +3.6 V Table 4. Thermal Resistance
VDDLDO to GND −0.3 V to +2.75 V Package Type θJA θJC Unit
VDD11 to GND −0.3 V to +1.26 V BC-49-8 66.6 53.1 °C/W
IOVDD to GND −0.3 V to +1.26 V
Digital Inputs and Outputs ELECTROSTATIC DISCHARGE (ESD) RATINGS
Inputs (CNV± and CLK±) to GND −0.3 V to +2.75 V The following ESD information is provided for handling of ESD-sen-
LVDS OUTPUT (DCO±, DA±, and DB±) to GND −0.3 V to +1.26 V sitive devices in and ESD-protected area only.
CS, SCLK, and SDI to GND −0.3 V to +2.75 V
GPIO0, GPIO1, GPIO2, and GPIO3 to GND −0.3 V to +1.26 V Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Temperature Field induced charged-device model (FICDM) per ANSI/ESDA/JE-
Storage Range −55°C to +150°C DEC JS-002.
Operating Range −40°C to +85°C
Maximum Reflow (Package) as per JEDEC J- 260°C ESD Ratings for the AD4080
STD-020
Table 5. AD4080, 49-Ball CSP_BGA
Stresses at or above those listed under Absolute Maximum Ratings ESD Model Withstand Threshold (V) Class
may cause permanent damage to the product. This is a stress HBM 1000 1B
rating only; functional operation of the product at these or any other FICDM 750 2B
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operat- ESD CAUTION
ing conditions for extended periods may affect product reliability. ESD (electrostatic discharge) sensitive device. Charged devi-
ces and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.

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Data Sheet AD4080
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1 Description
A1, A2, A3 VDD11 P 1.1 V ADC Core Supplies. These supply pins are internally decoupled by four, 470 nF
capacitors to GND.
When power is supplied to VDDLDO (B3), an internal LDO voltage regulator produces
the 1.1 V required at these pins. The voltage regulator is automatically powered on
when VDDLDO is greater than 1.4 V.
If VDDLDO is left disconnected, the required 1.1 V must be supplied to these pins
from an external source.
A4, A5 CNV+, CNV− DI Convert Start Inputs. This pin pair serves as the conversion control input; a conversion
is initiated on the rising edge of the convert signal.
These inputs are by default configured in complementary metal-oxide semiconductor
(CMOS) mode, in which CNV− must be tied to IOGND and the convert signal is
applied to CNV+. In the LVDS data interface mode, the convert start input can be
optionally configured in LVDS mode, in which case, the convert signal is applied
differentially to CNV+ and CNV− and an external 100 Ω termination resistor must be
placed across these pins. See the ADC Conversion Control section for further details.
A6 IOVDD P 1.1 V Digital Interface Supply Rail. This supply is internally decoupled by a 220 nF
capacitor to IOGND.
When power is supplied to VDDLDO (B3), an internal LDO voltage regulator produces
the 1.1 V required at this pin. The voltage regulator is automatically powered on when
VDDLDO is greater than 1.5 V.
If VDDLDO is left disconnected, the required 1.1 V must be supplied to this pin from
an external source (typically the host controller interface supply).
A7 CLK−/DCS DI Data Interface Clock Input (CLK−)/Data Interface Chip Select (DCS) Multifunction Pin.
In LVDS data interface mode (default), this pin serves as half of the differential data
clock input, and an external 100 Ω termination resistor must be present between it and
the CLK+ pin.

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Data Sheet AD4080
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 6. Pin Function Descriptions (Continued)

Pin No. Mnemonic Type1 Description
In SPI data interface mode, this pin functions as a chip select input (data interface chip
select).
B1, B2, C1, C2, F5, REFGND P Reference Grounds. Connect any external reference decoupling capacitors across
F6, G5 REFIN and REFGND. REFGND must be tied with a low impedance path to GND.
B3 VDDLDO P LDO Supply Rail Input.
This supply rail is internally decoupled by a 220 nF capacitor to GND. The two internal,
1.1 V, LDO voltage regulators can be supplied from a source connected to this input
in the 1.5 V to 2.7 V range. If this pin is left open, the internal regulators automatically
power off and both VDD11and IOVDD must be connected with an external voltage
source within their allowed specification limits.
If VDDLDO is connected to a voltage source, neither VDD11 nor IOVDD should be
connected to any external voltage source.
B4, B5 DCO−, DCO+ DO LVDS Echo Clock Outputs.
In LVDS data interface mode (default), this pin pair outputs a buffered and delayed
version of CLK+ and CLK−. Data outputs from LVDS Data Lane DA+ and Data Lane
DA− (and Data Lane DB+ and Data Lane DB− if active) are clocked out in alignment
with both rising and falling edges of DCO+ and DCO−. In SPI data interface mode (or
if the echo clock mode is disabled while in LVDS data interface mode), these pins can
be left unconnected.
B6 IOGND P Digital Interface Supply Ground Reference. This pin must be connected to the same
ground plane as all other GND pins.
All pins specified as type DI, DO, or DI/O must use this ground reference.
B7 CLK+/DCLK DI Data Interface Clock Input Multifunction Pin.
In LVDS data interface mode (default), this pin serves as half of the differential data
clock input, and an external 100 Ω termination resistor must be present between it and
the CLK− pin.
In SPI data interface mode, the single-ended data clock signal must be applied to this
pin.
C3 to C5, D3 to D5, GND P Grounds. All ground pins must be connected to a PCB GND plane.
E3 to E5
C6 DB+/SDOC DO Data Interface Output Multifunction Pin.
In LVDS data interface mode (default), this output pin along with DB− serves as the
optional, secondary LVDS Data Lane B. If unused, leave unconnected.
In SPI data interface mode, this pin functions as Serial Data Output C (SDOC), which
is active in a four-lane configuration only. Result data is shifted out of this pin on the
falling edge of the data interface clock (DCLK).
This pin must left unconnected if not being used.
C7 DA+/SDOA DO Data Interface Output Multifunction Pin.
In LVDS data interface mode (default), this output pin along with DA− serves as the
primary LVDS Data Lane A.
In SPI data interface mode, this pin functions as Serial Data Output A (SDOA), which
is active in a four-lane configuration only. Result data is shifted out of this pin on the
falling edge of the data interface clock (DCLK).
This pin must left unconnected if not being used.
D1 IN+ AI Positive Analog Differential Input.
D2 AUXIN+ AI Positive Auxiliary Analog Differential Input.
D6 DB−/SDOD DO Data Interface Output Multifunction Pin.
In LVDS data interface mode (default), this output pin along with DB+ serves as the
optional, secondary LVDS Data Lane B. If unused, leave unconnected.
In SPI data interface mode, this pin functions as Serial Data Output D (SDOD), which
is active in a four-lane configuration only. Result data is shifted out of this pin on the

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Data Sheet AD4080
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 6. Pin Function Descriptions (Continued)

Pin No. Mnemonic Type1 Description
falling edge of the data interface clock (DCLK). Note that this pin does not go into a
high impedance state when used in four-lane SPI mode when CS is inactive.
This pin must be left unconnected if not being used.
D7 DA−/SDOB DO Data Interface Output
In LVDS data interface mode (default), this output pin along with DA+ serves as the
primary LVDS Data Lane A. If unused, leave unconnected.
In SPI data interface mode, this pin functions as Serial Data Output B (SDOB). This is
the only active serial data output in single lane mode. Result data is shifted out of this
pin on the falling edge of the data interface clock (DCLK).
E1 IN− AI Negative Analog Differential Input.
E2 AUXIN− AI Negative Auxiliary Analog Differential Input.
E6 GPIO1 DI/O General-Purpose Input and Output 1 Pin.
E7 SCLK DI Configuration Interface Serial Data Clock. This clock input is used to shift data into and
out of the device configuration memory.
F1 GPIO2 DI/O General-Purpose Input and Output 2 Pin.
F2 GPIO3 DI/O General-Purpose Input and Output 3 Pin.
F3, G3 VDD33 P 3.3 V Supply Rail Inputs. These supply pins are internally decoupled by a 470 nF
capacitor to GND.
F4, G4 REFIN AI 3.0 V Reference Voltage Inputs.
F7 SDI DI Serial Data Input. Configuration data is shifted into this input on the rising edge of the
serial data clock, SCLK.
G1 CS DI Configuration Interface Chip Select Input (Active Low). The CS input frames serial
data transfers over the configuration SPI.
G2 CMO AO Common-Mode Voltage (VCM) Output.
G6 DNC DNC Do Not Connect.
G7 GPIO0 DI/O General-Purpose Input and Output 0 Pin.
1 AI is analog input, AO is analog output, DI is digital input; DI/O is digital input and output, DO is digital output, and P is power.

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Data Sheet AD4080
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 3. FFT 40 MSPS, fIN = 1 kHz, −0.5 dBFS Figure 6. THD vs. Input Signal Frequency (Amplitude = −0.5 dBFS, −1 dBFS,
−3 dBFS, −6 dBFS, −10 dBFS, and −12 dBFS)

Figure 4. FFT 40 MSPS, fIN = 1 MHz, −1.0 dBFS

Figure 7. Small Signal −3 dB Bandwidth at 40 MSPS

Figure 5. SNR vs. Input Signal Frequency (Amplitude = −0.5 dBFS, −1 dBFS,
−3 dBFS, −6 dBFS, −10 dBFS, and −12 dBFS) Figure 8. Sinc5 + Compensation Filter, Pass-Band Flatness

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Data Sheet AD4080
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 9. Sinc1 Filter Response, fS = 40 MHz (DEC x Means Decimate By) Figure 12. SNR vs. Total Decimation Rate, Sinc1

Figure 10. Sinc5 Filter Response, fS = 40 MHz Figure 13. SNR vs. Total Decimation Rate, Sinc5

Figure 11. Sinc5 + Compensation Filter Response, fS = 40 MHz Figure 14. SNR vs. Total Decimation Rate, Sinc5 + Compensation

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Data Sheet AD4080
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 15. INL vs. Code for Various Temperatures, 40 MSPS Figure 18. Histogram of Codes, Sinc5, Decimate 2×, Decimate 4× ...Decimate
×

Figure 16. Low Frequency Noise, Inputs Shorted

Figure 19. Histogram of Codes, Sinc5 + Compensation, Decimate 2×,
Decimate 4× … Decimate 512×

Figure 17. Histogram of Codes, Sinc1, Decimate 2×, Decimate 4× … Decimate

1024×
Figure 20. Offset Voltage Histogram

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 21. Offset Drift vs. Temperature Figure 24. CMO Voltage vs. Temperature

Figure 22. Gain Error vs. Temperature Figure 25. CMO Voltage Variation vs. Load Resistance

Figure 23. PSRR vs. Frequency Figure 26. Dynamic REFIN Current vs. Temperature

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 27. Total Power vs. Sampling Frequency

Figure 28. Total Power at 40 MSPS vs. Temperature

Figure 29. Total Power vs. Temperature in Sleep and Standby Modes

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Data Sheet AD4080
TERMINOLOGY

Integral Nonlinearity Error (INL) Intermodulation Distortion

INL refers to the deviation of each output code from a line drawn With inputs consisting of sine waves at two frequencies, fA and
between points at negative full scale and positive full scale. The fB, any active device with nonlinearities creates distortion products
negative full-scale reference is defined by an input level equivalent at sum and difference frequencies of m × fA and n × fB, where
to ½ LSB prior to the first code transition. The positive full-scale m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are
reference is defined as an input level that is 1½ LSB beyond the those for which neither m nor n are equal to 0. For example,
last code transition. The deviation is measured from the center of the second-order terms include (fA + fB) and (fA − fB), and the
each code relative to the straight line. third-order terms include (2fA + fB), (2fA − fB), (fA + 2fB), and (fA −
2fB).
Differential Nonlinearity Error (DNL)
The AD4080 is tested where two input frequencies near the top
In an ideal ADC, code transitions occur at 1 LSB intervals. DNL is a end of the input bandwidth are used. In this case, the second-order
measure of the maximum deviation of any code from the ideal code terms are usually distanced in frequency from the original sine
width. DNL is specified in terms of resolution for which no missing waves, and the third-order terms are usually at a frequency close to
codes are guaranteed. the input frequencies. As a result, the second-order and third-order
Zero Error terms are specified separately. The calculation of the intermodula-
tion distortion is as per the THD specification, where it is the ratio
Zero error is the difference between the ideal midscale voltage, 0 V, of the RMS sum of the individual distortion products to the RMS
and the applied voltage producing the midscale output code, 0 LSB. amplitude of the sum of the fundamentals, expressed in decibels.
Gain Error Power Supply Rejection Ratio (PSRR)
Gain error is specified as the difference in the slope of the ADC PSRR is a measure of the sensitivity of the ADC to variations in the
transfer characteristic vs. that of an ideal converter. In an ideal data specified power supply rail vs. frequency. PSRR is computed as the
converter, the first code transition (100 … 00 to 100 … 01) occurs ratio of the observed change in the output code in RMS volts to the
½ LSB more than the nominal negative full-scale input (−2.999997 RMS magnitude of the perturbing signal coupled to the supply. The
V for a ±3.0 V range at 20 bits) and the last code transition (011 resulting ratio is reported in decibels (dB).
… 10 to 011 … 11) occurs 1½ LSB less than the nominal positive
full-scale input (+2.999991 V for a ±3.0 V range at 20 bits).
Signal-to-Noise Ratio (SNR)
SNR is the computed ratio of the fundamental signal amplitude
measured in RMS volts and the root sum of squares of all other
spectral components in the Nyquist bandwidth (f < fS/2) excluding
harmonics and DC components. The computed value of SNR is
converted into a logarithmic scale and expressed in decibels (dB).
Signal-to-Noise-and-Distortion (SINAD) Ratio
SINAD is the computed ratio of the fundamental signal amplitude
measured in RMS volts and the root sum of squares of all other
spectral components in the Nyquist bandwidth (f < fS/2) including
harmonic components but excluding the DC component. The com-
puted value of SINAD is converted into a logarithmic scale and
expressed in decibels (dB).
Total Harmonic Distortion (THD)
THD is the ratio of RMS sum of the amplitudes of the first five
harmonic components to the RMS amplitude of a full-scale input
signal expressed in decibels (dB).
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio between the RMS amplitude of the input signal
and the peak spurious signal amplitude, expressed in decibels (dB).

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Data Sheet AD4080
THEORY OF OPERATION

PRODUCT OVERVIEW on the analog input pins, followed by a conversion phase, initiated
by a conversion start signal. During the conversion phase the
The AD4080 is a high-speed, low noise, low distortion, 20-bit, Easy sampled analog input voltage is converted to a digital conversion
Drive, SAR ADC. The device is capable of conversion rates up result. In a single ADC, this is typically performed by converting
to 40 MSPS, with 46.25 ns result output latency. The parametric the voltage from one sampling circuit. In the case of the AD4080,
performance, bandwidth, and throughput make this product ideal for Figure 30 details the unique feature of this converter, whereby the
a variety of high-speed, data acquisition applications. Innovations in analog input is connected to two sampling circuits, and the input
the AD4080 product design enable both complexity reduction and is sampled by each one in sequence. To a user, this requires
component flexibility in the design of data acquisition signal chains. no additional control or configuration, and as such, is completely
The converter architecture enables continuous acquisition of the in- transparent in usage.
put signal throughout the entire conversion period, tCONV, reducing
the input signal conditioning bandwidth required to settle to the
specified resolution.
The design incorporates circuitry to reduce the nonlinear input
current associated with the charge kickback typical of a switched
capacitor SAR input. Figure 30. Simplified Representation of the AD4080 SAR ADC
Conversion result access occurs via either a multilane LVDS port
operating at clock rates up to 400 MHz or via a multioutput SPI The AD4080 converter seamlessly sequences back and forth from
operating at clock rates up to 50 MHz. one sampler to the other, meaning that one sampler is in acquisition
mode while the voltage sampled on the other is being converted.
The LVDS interface is compatible with differential signaling stand- Figure 31 shows that the AD4080 timing is contrasted against
ards between 1.2 V and 2.5 V. To maximize throughput the previous a conventional SAR ADC, where it switches between sequential
conversion results can be read through the entirety of the conver- conversion and the acquisition phase leads to a reduced amount
sion period as long as the CNV+ edge and CLK+ rising edges are of time for the input signal acquisition and settling. As sampling
aligned. The LVDS interface is described in detail in the LVDS Data rates increase (and therefore cycle times reduce), it is important
Interface Configuration section. to maintain longer acquisition times to enable settling, particularly
The single or quad lane SPI data interface is also available for to the higher levels of precision offered by the AD4080. Further
CMOS level interfacing. When configured, this interface is used details on the benefits of reducing driver and noise bandwidths are
to access conversion results stored in the on-chip FIFO. FIFO described in the Easy Drive Analog Inputs section.
operation is explained in the Result FIFO section.
CONVERTER OPERATION
A conventional SAR ADC typically operates in two phases; an
acquisition phase, whereby the analog input voltage is acquired

Figure 31. Conversion Cycle Compared to Conventional SAR

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THEORY OF OPERATION

TRANSFER FUNCTION
The AD4080 digitizes the full-scale difference voltage of 2 × VREFIN
into 220 levels, resulting in an LSB size of 5.72 μV with VREFIN = 3.0
V. Note that 1 LSB at 20 bits is approximately 0.95 ppm.
Table 7 summarizes the mapping of input voltages to differential
output codes.

Figure 33. Equivalent Analog Input Circuit Model

In this model, the input sampling network was simplified to consist

of two ideal switches, RS and CS, for the ADC in acquisition mode.
The typical values for CS is 23.5 pF and RS is 26 Ω.
The parasitic capacitance related to the pin connection, CPIN, is
modeled as a shunt capacitor between the pin and device ground
terminal (GND). The capacitance includes parasitic capacitance
formed from the physical interface, routing in the package substrate
and the device input protection circuits. The CPIN value is typically
Figure 32. ADC Ideal Transfer Function for the Differential Output Codes
4.5 pF. The input protection circuit for the AD4080 is modeled as
(FSR Is Full-Scale Range) diode clamps to the GND and VDD33 supply rails.
The external low-pass filters (LPFs) constructed from RFILTIN and
Table 7. Input Voltage to Output Code Mapping
CFILTIN and RFILTAUX and CFILTAUX are band-limiting filters for the
Analog Input Voltage
primary and auxiliary paths, respectively.
Difference (IN+ − IN−, Digital Output Code (Twos
Description Volts) Complement, Hex) The combination of RFILTIN and CFILTIN are often referred to as
FS − 1 LSB +VREFIN × (1 − 1/219) 0x7FFFF anti-aliasing filters because these filters do introduce a single-pole
Midscale + 1 LSB +VREFIN/219 0x00001 filter in the analog input signal path. However, the function of CFILTIN
Midscale 0 0x00000 is more complex and must be carefully considered. Conversion
Midscale − 1 LSB −VREFIN/219 0xFFFFF through a SAR involves sampling the voltage from an internal ca-
−FS + 1 LSB −VREFIN × (1 − 1/219) 0x80001 pacitor, represented by CS in the Figure 33, which typically occurs
−FS −VREFIN 0x80000
in two phases in time ϕ1 and ϕ2 . During the first phase, the ϕ1
switches are closed, the ϕ2 switches are opened, and the sampling
EASY DRIVE ANALOG INPUTS capacitors (CS) are charged to the analog input voltages present at
IN+ and IN−. During the second phase, the ϕ1 switches are opened,
The AD4080 signal input consists of a fully differential input pair the ϕ2 are closed, and the ADC converts the voltage onto CS.
(IN+ and IN−), each connected to the input sampling network
(series resistance (RS) and sampling capacitance (CS)) and a pair Another short time phase exists, where the CS charge is reset after
of auxiliary inputs (AUXIN+ and AUXIN−) that provide a reference the conversion is complete. This process repeats for each new
to the sampling network linearization circuits. An equivalent circuit ADC conversion. The transfer of charge from the ADC analog input
model of the analog input is presented in Figure 33. pins to CS, due to the closing of the switches in each conversion
cycle, creates a demand at the analog input pin. It is important to
ensure that the voltage presented at the input pin is undisturbed by
the internal ADC activity so that the voltage can be converted with
the highest accuracy. Each new conversion presents a disturbance,
or kick, at the input. The faster the ADC conversion rate is, the
more frequent the occurrence of these kicks. An ADC driver is used
to ensure that the input voltage, disturbed by the kick at each sam-
pling instance, is fully settled to the required ADC resolution prior
to the next sample being acquired. The ADC driver amplifier must
have a wide enough output bandwidth to settle the voltage in time
for each sample, which creates a signal chain design constraint to

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THEORY OF OPERATION

ensure that there is enough time to settle to the required voltage To design the external input filter, it is usual to calculate how
accuracy (or ADC resolution). For this reason, a fast ADC requires many time constants (K) are needed for the required resolution.
a wide bandwidth driver. For high resolution ADC converters, low To calculate the time constant from the natural log of the required
signal chain noise is required to obtain high resolution. A wider setting resolution, for example, if settling to within 1 LSB of 20 bits
bandwidth can result in more noise coming through the signal chain (n = 20) of resolution is desired, use the following equation:
to the ADC, which can present a significant signal chain design
challenge for a conventional SAR ADC. However, the AD4080 in- K = ln(2n ∕ 1 bit) = 13.86 time constants (1)
cludes some unique Easy Drive features that simplify these aspects When considering a conventional ADC, as described in the Con-
of signal chain design. verter Operation section, where the acquisition time is only 60% of
One such AD4080 feature is continuous signal acquisition. Due the ADC conversion cycle, there is less time available for settling.
to its unique design, that the tAQC is equal to the tCYC of the For such an ADC sampling at 40 MSPS, the driver must settle
ADC, resulting in the AD4080 being in signal acquisition mode within 25 ns × 0.6 or 15 ns, and settling of the input voltage within 1
for the full duration of each ADC conversion. The input voltage LSB also requires a time constant tau (τ) of 15 ns ÷ K = 1.082 ns or
has 100% of the tCYC conversion time to settle the input voltage a bandwidth of 1/(2 × π × τ) = 147 MHz.
before the next conversion, whereas a conventional ADC may need However, with the Easy Drive features of the AD4080, the result
to settle in 60% of this time. More settling time results in less is an acquisition time of 100% of the conversion cycle, which
bandwidth required by the driver, which generally, bears a lower indicates only 13.86 time constants to settle within 1 LSB of 20 bits
power requirement. In addition, because the external filters (RFILTIN resolution. However, additionally, the low analog input current of
and CFILTIN) must be designed with enough bandwidth for the driver the AD4080 and the internal methods that reduce any kick back to
to settle the input voltage, the additional settling time results in a the driver (as charge transfers from the analog input to the internal
lower cut-off. Because of this lower cut-off, more of the signal chain sampling capacitors at the sampling instance) reduce the required
noise can be filtered at the inputs with these external filters. number of time constants by 9.5%. Therefore, for the 20-bit settling
Another Easy Drive feature is its highly linearized analog input example, the required number of time constants (K) reduces from
current. With this feature, the AD4080 presents a less challenging 13.86 to 12.55 without impact on settling or distortion.
load to a driver amplifier and reduces any potential distortion from These Easy Drive features significantly reduce the required driver
a driver that can occur when presented with a nonlinear input bandwidth required to settle. For example, at 40 MSPS, settling of
current. Figure 34 shows the typical input currents into both the the input voltage within 1 LSB requires a time constant tau (τ) of
differential signal pair (IN+ and IN−) and auxiliary inputs (AUXIN+ 25 ns ÷ K = 1.992 ns, or a bandwidth of 1/(2 × π × τ) = 80 MHz.
and AUXIN−). This significant reduction in the required bandwidth allows use of
lower power, lower bandwidth drivers and the design of a lower
bandwidth input filter to remove more driver or signal chain noise.
Table 8 suggests some filter values for use with the AD4080 in
some example use case conditions.
Another Easy Drive feature, as can be seen in the Figure 33, is the
auxiliary signal input path. This path feeds the analog input signal
to an internal linearization block, and this block feeds a correction
signal to the sampled voltage. Recommended values are given
in Table 8. The filter on the auxiliary inputs is set for the same
bandwidth as the analog input, and RFILTAUX must be set at 4 ×
RFILTIN. The recommended filter configuration is to use a differential
CFILTIN capacitor; therefore, calculate the components as τ = RFILTIN
× 2 × CFILTIN.
Note that the minimum RFILTIN must be 15 Ω, and that RFILTAUX can
Figure 34. Typical Input Current vs. Differential Input Voltage be set from a minimum of 5 Ω up to 4 × RFILTIN .
Table 8. Recommended Input Filter Configurations
fS (MSPS) Target Accuracy (Bit) Required Bandwidth (MHz) RFILTIN (Ω) CFILTIN (pF) RFILTAUX (Ω) CFILTAUX (pF)
40 20 80 25 39 100 10
40 18 72 25 47 100 10
30 20 60 25 47 100 10

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REFERENCE BUFFER AND COMMON-MODE charging time for the preceding noise limiting filter does not impact
OUTPUT the start-up time required for the application. In general, consider
CMO buffering for the following situations:
The AD4080 integrates a charge reservoir capacitor (CREF) and a
low-drift reference buffer at the reference input pin (REFIN), elimi- ► The VDD33 power rail of the AD4080 is frequently cycled.
nating the need for dedicated external components and enabling ► Short start-up settling times are required.
multiple AD4080 devices to share a single voltage reference. ► If the external load on CMO exceeds 30 μA (RL < 45 kΩ). See
The integrated capacitor (CREF) has a capacitance of 9.4 μF ± 20%, Figure 25 for the typical load regulation information.
and it is constructed from commercially available, multilayer, high POWER SUPPLIES
dielectric (X6S), ceramic capacitors. CREF serves as the primary
charge reservoir for the data converter. Integrated, in-package com- The power requirements for the AD4080 are distributed across a
ponents, such as CREF, minimize the overall solution area, mitigate minimum of three supply domains including a 3.3 V analog circuit
potential performance errors introduced by factors like component domain (VDD33), a 1.1 V core supply (VDD11), and a 1.1 V
selection, placement and routing challenges, and in general, reduce domain for the digital interface (IOVDD). An optional fourth supply
the engineering effort to first design success. rail (VDDLDO) can be used to supply power to two integrated
voltage regulator used to internally power the 1.1 V core (VDD11)
Additional external capacitance (CRSV) can be placed across the and interface (IOVDD) rails. Each of these two regulators can be
REFIN and REFGND pins for improved charge capacity and noise independently turned off by software. For all details and design
rejection as required. As with all precision circuits, the placement considerations when using the internal voltage regulators, see the
of the external reference capacitors must be as close to the device Internally Regulated Supply Configuration section. On the other
pins as possible on the same side of the PCB. The routing between hand, for applications that will not use internal regulators see
the capacitor and device pins must minimize the series impedance the Externally Generated Supply Configuration section for further
in each routing path. details.
Power for the VDD33 supply rail must be supplied from an external
source and must only be applied once power is supplied to the 1.1
V supply rails as described in the Power Supply Sequence section.

Figure 35. REFIN and CMO Internal Equivalent Circuit and Typical
Application

The AD4080 internally generates a common-mode reference volt-

age of one-half of VREFIN, which is output through the CMO pin. The
absolute error in the CMO output voltage is guaranteed to be less
than ±20 mV. The CMO output is used to set the common-mode
Figure 36. Typical Regulator Start-Up Transient, Converter Idle
output voltage of the analog front-end stage driving the AD4080
inputs, ensuring the AD4080 common-mode input requirement is All supply domains are internally decoupled using multilayer, high
satisfied. The CMO output must be filtered with a RC LPF to limit dielectric, ceramic capacitors (X6S), eliminating the need of exter-
the total output noise as illustrated in Figure 35 (see RCMF and nal decoupling capacitors. However, care must be taken to under-
CCMF). stand the bulk decoupling requirements for other components in the
The output is generated using a resistive divider connected to the design which share the same supply. Integrated supply decoupling
reference buffer output. The resulting output impedance at the CMO capacitors in the AD4080 are listed Table 6 as well as in Table 9.
pin is typically 700 Ω. Due to the limited drive capability at the Table 9. Integrated Supply Decoupling Summary
CMO pin, the external load must be carefully considered to avoid
Supply Pin Nominal Value (μF) Tolerance (%) Return Path
excessive start-up times or absolute errors. The CMO output may
be directly connected to a high impedance common-mode input VDD33 0.47 ±10 GND
of a fully differential amplifier driving the AD4080, assuming the VDDLDO 0.22 ±10 GND

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THEORY OF OPERATION

Table 9. Integrated Supply Decoupling Summary (Continued) supply has been reestablished. More details on the POR circuitry
Supply Pin Nominal Value (μF) Tolerance (%) Return Path can be found in the Power-On Reset (POR) Monitor section. The
VDD11 1.88 (4× 0.47) ±10 GND VDD33 rail is supplied with an external 3.3 V supply. The VDD33
IOVDD 0.22 ±10 IOGND supply can be removed to further reduce power in the Power
Saving Operating Modes, only analog circuity is in held in reset,
INTERNALLY REGULATED SUPPLY and the register content remains unaffected. Refer to Table 1 for the
CONFIGURATION applicable input voltage tolerance for each supply rail.
The AD4080 includes two internal LDO regulators, one to generate As illustrated in the example of Figure 38, external voltage sources
the 1.1 V VDD11 supply rail and another to internally generate the are applied to VDD11 and IOVDD pins.
1.1V IOVDD supply rail. Upon power on or reset of the AD4080
registers, both regulators automatically power up when an external
voltage source in the range of 1.4 V to 2.7 V is applied to the
VDDLDO pin. The regulators are designed to supply the internal
load requirement of the AD4080; therefore, no external loading is
permitted. Noted that, as described in the Power Saving Operating
Modes section, IOVDD is disabled in both power saving modes.
The required connectivity when using the internal regulators is
illustrated in Figure 37. As shown in Figure 37, the VDD11 pins Figure 38. Externally Sourced Supply Configuration
(A1, A2, and A3) must be shorted together. It is recommended that
a thick trace or polygon on the device side of the PCB be used POWER-ON RESET (POR) MONITOR
to implement this connection in the physical design to minimize
The AD4080 power supply monitoring circuits inhibit the converter
routing impedance. The VDD33 rail is supplied with an external
functions and reset the configuration memory when supply con-
3.3 V supply. This supply can be removed when using power
ditions are outside the specified operating limits. This function
saving modes. When this supply is removed, only analog circuity
ensures each device is in a deterministic state after power-up.
is held in reset, and the configuration register content remains
The power-on function is constructed from two independent voltage
unaffected. Refer to the Table 1 section for the applicable input
monitors, the first measuring the core 1.1 V supply and a second
voltage tolerance for each supply rail.
measuring the voltage at the reference input (REFIN). Each monitor
has its own comparator output that is used to decouple the analog
and digital block resets as shown in Figure 39.

Figure 37. Internally Regulated (1.1 V) Supply Configuration

The internally regulated configuration is ideal for use in area con-

strained applications where the ability to eliminate external regula-
tors is advantageous. However, noted that, in this configuration, the
internal supply regulation introduces additional power dissipation.
Figure 39. Simplified Diagram of POR Circuit
EXTERNALLY GENERATED SUPPLY
CONFIGURATION The core VDD (1.1 V) supply monitor compares the VDD11 supply
voltage against a preset threshold of 0.93 V. If the supply voltage
In system using externally generated supplies VDDLDO must be falls to less than this threshold, a reset signal, POR_D, asserts.
left unconnected. With VDDLDO unconnected both the internal The digital logic reset signal, DIG_RESET, is defined as the logical
LDO powering VDD11 and the internal LDO powering IOVDDD are combination of the POR_D signal and (logical AND) the compliment
automatically disabled. VDD11 must be connected to an externally of the SPI software reset function. When either the POR_D signal
generated 1.1V supply rail and IOVDD should be connected to an (VDD11 < 0.93 V) or the SW RESET signal is asserted, the internal
externally generated 1.1V to 1.2V supply rail. It should be noted digital circuitry is held in reset. When cleared, the contents of the
that if VDD11 is not present the part will be held in a POR state configuration registers are restored to the factory default settings.
and all AD4080 registers reset to their default state the after the

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THEORY OF OPERATION

The reference monitor compares the input voltage at the reference specified supply tolerance to avoid undesired behavior. Therefore, if
input pin, REFIN, against a preset threshold of 2.7 V. As illustrated the selected voltage reference does not provide an enable pin, it is
in Figure 39, power for the reference monitor circuit is supplied from strongly recommended to design the reference circuit to power up
the VDD33 supply. For correct operation of the monitor circuit, the after VDD33.
VDD33 supply must be applied to the AD4080 within the specified
tolerance of 3.3 V ± 5% before the reference source is enabled. The configuration SPI inputs, CS, SCLK, and SDI, are protected
Assuming the device is operating within the specified supply condi- with clamps to the VDD33 supply rail to allow the inputs to swing
tions, a reference voltage less than 2.7 V results in the assertion more than IOVDD. As a consequence of this architectural decision,
of an internal reset signal, POR_A. The POR_A signal and (logical it is necessary to drive the SPI inputs to ground or to otherwise
AND) the DIG_RESET signal are combined to produce a reset leave the inputs floating until VDD33 is greater than IOVDD − 0.3
(ANA_RESET) for the analog circuit blocks including the ADC core, V. Alternatively, the VDD33 source can be connected to the device
ADC timer, reference buffer, etc. If this reset signal is asserted, the using a series power switch, like the ADP199, configured so that
analog blocks are placed in an inactive state, and the converter the switch is open when the source is less than IOVDD − 0.3 V,
functionality is disabled. This event is indicated with a value of 1 in eliminating the parasitic current path through the digital inputs to
the POR_ANA_FLAG bit from the Device Status Register (Address VDD33.
0x14). The state of the event detection is persistent until a Logic 1 Table 10. Recommended Supply Sequence
is written to the POR_ANA_FLAG bit to clear the detection state. 1.1 V Supplies (IOVDD and VDD11) Source Supply Sequence
POWER SUPPLY SEQUENCE Internally Generated 1. VDDLDO
2. VDD33
Table 10 specifies the recommended supply sequences for both
3. Digital inputs
internal and external generation of 1.1 V supply rails (IOVDD and
VDD11). Both methods are shown in Figure 40 and Figure 41, 4. Input drive, reference
where highlighted in blue are the supplies that must be provided Externally Generated 1. IOVDD, VDD11
to the AD4080, including the REFIN voltage. In both cases, the 2. VDD33
AD4080 requires that the supplies are applied in ascending voltage 3. Digital inputs
order. The design must also ensure that voltage is applied at the 4. Input drive, reference
analog inputs (IN+ and IN−) and reference input (REFIN) concur-
rently with or immediately following the VDD33 supply. As described To power down the application circuit, the power-up sequence
in the Power-On Reset (POR) Monitor section, the voltage at the specified in Table 10 should be reversed.
reference input pin must only be applied once VDD33 is within the

Figure 40. Power Supply Sequence, Internally Generated IOVDD, VDD11

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THEORY OF OPERATION

Figure 41. Power Supply Sequence, Externally Generated IOVDD, VDD11

POWER SAVING OPERATING MODES normal mode takes longer. Both standby and sleep mode can be
particularly useful when used with the result FIFO (see the Result
The operating mode of AD4080 is controlled by the OPERAT- FIFO section), whereby previously stored conversion data can be
ING_MODES bits in the Device Configuration Register (Address accessed from the FIFO while it is still in the selected power saving
0x02). On power up and after reset, the default is normal mode mode.
(OPERATING_MODES = 00). Table 11 describes all operating
modes, and Figure 42 depicts the allowed transitions between To reduce power consumption in both standby and sleep mode,
these modes. Note that direct transitions between the two power the internal IOVDD LDO regulator is powered down. If the user
saving modes (standby mode and sleep mode) are not permitted. is not externally supplying IOVDD, all IOVDD domain inputs and
outputs are disabled (all GPIOx and all LVDS data interface (see
It is important to stop all conversion and data interface clocking the LVDS Data Interface section) and SPI data interface (see the
before configuring the power mode. SPI Data Interface section) signals are disabled). In this specific
When in either standby mode or sleep mode, the VDD33 supply condition, it is still possible to write to the AD4080 SPI configuration
can be removed to reduce power consumption. This supply must to issue a command to return to normal mode by writing to the
be re-established prior to issuing the SPI configuration interface OPERATING_MODES bits in the device configuration register (see
command to exit either power saving mode. the Device Configuration Register section) or to issue a software
reset (see the Software Reset section). As GPIOx is disabled, it is
not possible to perform any read activity on the SPI configuration
interface bus.
When IOVDD is externally supplied, and the device is put into
standby or sleep mode, the LVDS data interface is disabled; howev-
er, all GPIOx, SPI data interface, and SPI configuration interface
pins remain enabled and unaffected. While power is supplied exter-
nally to IOVDD within its specified range, previously acquired data
Figure 42. Operating Mode Transitions stored in the result FIFO can be access in either standby or sleep
mode.
Transitioning from normal mode to either of the two power saving
modes is achieved by writing the required value to the OPERAT- Table 11 also indicates the wake-up times associated with each of
ING_MODES bits in the Device Configuration Register. Waking the modes. Wake-up time from sleep mode is significantly higher
up (that is, transitioning back to normal mode) is achieved in a than that of standby mode because time must be allowed for
similar way because the SPI configuration interface operation is the internal reference and common-mode buffers to re-enable and
not affected by any of the power saving modes (see the SPI Config- to replenish charge to the internal capacitors. When returning to
uration Interface section). Standby mode can be selected to save normal mode, the specified wake-up time must be satisfied before
power, in the case where the user wants to quickly return to normal applying the first conversion start pulse. This specified time is the
conversions. Sleep mode is a lower power state where returning to time it takes from when the SPI command to exit the selected
power saving mode is written to the device configuration register

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Data Sheet AD4080
THEORY OF OPERATION

(see the Device Configuration Register section) to update the

OPERATING_MODES bits.
Table 11. Power Saving Operating Modes
Operating OPERATING_MODES Wake-Up Time (Maximum Time to
Mode Bits Value Description Effect Normal Mode)
Normal 0b00 Normal operating mode Normal operation. Not applicable
Standby 0b01 Standby operating mode The internal IOVDD LDO regulator is disabled. 100 μs
If IOVDD is not externally supplied, all GPIOx and all
LVDS data interface and SPI data interface signals
are disabled. For the SPI configuration interface only.
writes to the device configuration register (see the
Device Configuration Register section) and Interface
Configuration A register (see the Interface Configuration
A Register section) are allowed.
If IOVDD is externally supplied, all GPIOx and SPI data
interface signals are enabled. The SPI configuration
interface is fully enabled. Because the SPI data
interface remains enabled, the user can access data
in the result FIFO (see the Result FIFO section).
The ADC core is powered down. The analog circuitry
remains in reset (ANA_RESET remains asserted), and
no ADC conversions can be performed.
The VDD33 supply can be removed to reduce power.
When in use, the internal VDD11 LDO regulator remains
on.
The internal reference buffer is enabled.
Common-mode output buffer is enabled.
The LVDS interface is disabled.
Sleep 0b10 Low power operating mode The internal IOVDD LDO regulator is disabled. 100 ms
If IOVDD is not externally supplied, all GPIOx and all
LVDS data interface and SPI data interface signals
are disabled. For the SPI configuration interface only,
writes to the device configuration register (see the
Device Configuration Register section) and Interface
Configuration A register (see the Interface Configuration
A Register section) are allowed.
If IOVDD is externally supplied, all GPIOx and SPI data
interface signals are enabled. The SPI configuration
interface is fully enabled. Because the SPI data
interface remains enabled, the user can access data
in the result FIFO (see the Result FIFO section).
The ADC core is powered down. The analog circuitry
remains in reset (ANA_RESET remains asserted), and
no ADC conversions can be performed.
The VDD33 supply can be removed to reduce power.
The internal reference buffer is disabled
When enabled, the internal VDD11 LDO regulator
remains on.
The common-mode output buffer is disabled.
The LVDS interface is disabled.
The SPI data interface remains enabled to access data
in the result FIFO (see the Result FIFO section).

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Data Sheet AD4080
THEORY OF OPERATION

SOFTWARE RESET
This reset method must only be used once the AD4080 is in an idle
state, where conversions are not being clocked, and any existing
conversion is completed.
A software reset is achieved by issuing the following two writes to
the Interface Configuration A register (see the Interface Configura-
tion A Register section, Address 0x00):
1. Set SW_RESET and SW_RESETX bits to 1 by writing 0x81 to
the register.
2. Then, issue another write command that sets either or both of
those bits to 0.
This action returns any previously configured registers to their
default settings, except for the ADDR_ASCENSION bit from the
Interface Configuration A register, which keeps its previous value.
The contents of the FIFO, if any, are also not affected by the
software reset. The ADDR_ASCENSION bit and FIFO data only
return to their default settings after a hardware reset or a full
power-up happens.

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Data Sheet AD4080
APPLICATIONS INFORMATION

TYPICAL APPLICATIONS DIAGRAMS

Figure 43. AD4080 Typical Applications Diagram, Fully Differential Amplifier

Figure 44. AD4080 Typical Applications Diagram, Single Op-Amp Drivers

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Data Sheet AD4080
APPLICATIONS INFORMATION

ANALOG FRONT END DESIGN bandwidth and signal bandwidth increase, so too does the noise
bandwidth. In addition, as these speeds increase, maintaining pre-
Driver Amplifier Choice cision in a driving amplifier becomes a greater challenge. These
challenges are often met by increased power in the driver; however,
As described in the Easy Drive Analog Inputs section, theAD4080 Analog Devices, Inc., offers a wide choice of power efficient driver
has a number of unique features that opens this ADC up to being amplifiers that can be found on the Differential Amplifiers and
used with a wide range of driver amplifier solutions. Because the ADC Drivers web page. Also, due to the Easy Drive features of
AD4080 offers exceptionally low noise, and excellent levels of the AD4080, where the settling bandwidth is relaxed considerably,
precision at sampling rates up to 40 MSPS with remarkably efficient products such as the ADA4945-1 fully differential amplifier (FDA)
power consumption, this presents signal chain choices on which make an excellent low power companion product. Table 12 offers
application parameters to prioritize. As is often the case, there some other suggested products for consideration.
can be some competing parameters to consider. Wider bandwidth
amplifiers are required to drive faster ADCs because the settling
Table 12. Driver Amplifier Selection Table
Quiescent Input Voltage −3 dB Bandwidth
Part Number Category Current (IQ) Noise (VN) (Gain = 1) THD at 1 MHz Application Considerations
ADA4945-1 FDA 4 mA 1.8 nV/√Hz 145 MHz −90 dB Lowest power
ADA4932-1 FDA 9.6 mA 3.6 nV/√Hz 560 MHz −110 dB Low power, wider bandwidth, improved distortion
at higher signal frequencies
ADA4927-1 FDA 20 mA 1.3 nV/√Hz 2300 MHz −112 dB Low noise, lower distortion at higher signal fre-
quencies
AD8139 Single op amp 24.5 mA1 2.25 nV/√Hz 410 MHz −120 dB Lowest distortion at higher signal frequencies
ADA4899-1 Single op amp 28.6 mA1 1.414 nV/√Hz 600 MHz −117 dB Lowest distortion at higher signal frequencies
ADA4930-1 FDA 35 mA 1.15 nV/√Hz 1350 MHz −110 dB Lowest noise

1 Combined quiescent current of two amplifiers.

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Data Sheet AD4080
APPLICATIONS INFORMATION

REFERENCE CIRCUITRY DESIGN

The AD4080 requires a low noise, high precision and stability,
and low temperature drift external reference of 3 V. This reference
defines a differential input range for the ADC of ±VREFIN. The refer-
ence must be within ±5 mV of +3 V. Recommended references are
LTC6655, LT6657, or ADR4530. For best performance, however,
use the LTC6655 external reference. Table 13 details the typical
parameters of the previously mentioned references, comparing
absolute accuracy, noise, temperature drift, load regulation, and
power consumption. For more detailed specifications, refer to the
data sheet of the given product.
Table 13. Comparison of the Main Parameters of the LTC6655, LT6657, and
ADR4530 References
Parameter LTC6655 LT6657 ADR4530B Figure 45. AD4080 General External Reference Design Functional Diagram
Accuracy 0.025% 0.1% 0.02%
DATA INTERFACE CLOCKING SOLUTION
Temperature Coefficient 2 1.5 2
(ppm/ºC) When designing the LVDS data interface (see the LVDS Data Inter-
0.1 to 10 Hz Noise (ppm p-p) 0.25 0.5 0.53 face section), the user must ensure the clocking solution adheres
Maximum Load (mA) ±5 ±10 ±10 to the timing specifications of the AD4080 (see Table 2). When
Load Regulation (ppm/mA) 3 0.7 30
configured for LVDS mode data interface, the user must ensure
that timing specifications stay within the maximum conversion to
Maximum Supply (V) 13.2 40 15
clock alignment time of ±535 ps (tCCA). In addition, ensure that
Shutdown Yes Yes No a low jitter conversion (CNV) clock is provided such that there
Supply Current, IS (mA) 5 1.2 0.7 is no unwanted impact to SNR performance. This jitter is signal
frequency dependent; therefore, the level of jitter tolerable in a
There is no need for the external reference capacitor because given system is dependent on the application use case. The Analog
the AD4080 embeds one internally, 9.4 μF, (see Figure 45). The Devices Technical Article Maximum SNR vs Clock Jitter provides
REFIN reference input pin is internally buffered, which substantial- further guidance on this topic.
ly reduces ADC conversion transients and isolates the external
reference from these transients. Therefore, no external amplifier is For example, a recommended clocking solution for where the
required to buffer the external reference. For the reference input ca- AD4080 is configured to use the LVDS data interface with a single
pacitance (C REF IN) and reference output capacitance (C REF OUT) lane enabled and using echo clock mode. In this example, a 25
values, refer to the given external reference IC data sheet recom- MHz oscillator is selected with low phase noise and jitter. The
mendations. As a layout recommendation, the external reference following MT-008 tutorial serves as an aid to convert between
chip must be placed as close as possible to the AD4080 and its phase noise and RMS phase jitter, often quoted interchangeably
REFIN pinto minimize the series impedance of the track connecting in crystal oscillator product data sheets. The ADF4350 wideband
the REFIN pin to the external reference output. It is recommended synthesizer with an integrated voltage-controlled oscillator (VCO)
to minimize the exposure of this track to noisy signals, especially serves as versatile means of generating a 400 MHz clock system
digital ones. clock, while maintaining low jitter and offering flexibility and control
to reconfigure this frequency depending on the application needs.
This clock then feeds the AD9508 clock fanout buffer with output
dividers that can be configured for the desired LVDS level signaling.
In the example shown in Figure 46, one output channel is set to
divide by 1 to output the LVDS clock, while another output channel
is configured to divide by 10 to output the AD4080 conversion
clock. This 1:10 ratio of CNV:CLK frequencies ensures 20 bits of
data can be read out in on the double data rate (DDR), single lane,
LVDS data interface. For a dual lane configuration, such as shown
in Figure 47, this ratio is adjust to 1:5.
The example shows that echo clock mode is used and aids data
alignment for the host controller (in the case a field-programmable
gate array (FPGA)). In self clock mode, where DCO+ and DCO−

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Data Sheet AD4080
APPLICATIONS INFORMATION

are not available for alignment, the ADC Result Latency and LVDS POWER SOLUTION
Interface Alignment section describes how the INTF_CHK_EN bit
(Address 0x15, Bit 4) can be enabled to help align the host control- With such low noise and up to a 40 MHz sampling rate, it is
ler to data and to mitigate against any system propagation delays. important that careful consideration is taken for the power solution
of applications to ensure that the low noise supplies provided to the
AD4080 do not become a source of performance or accuracy deg-
radation. To aid ease of use and to help reduce external required
components, two internal LDO regulators are integrated within the
AD4080. Further details on these regulators can be found in the
Internally Regulated Supply Configuration section. Also, note that
the internal supply decoupling capacitors are included for all supply
Figure 46. Single Lane, LVDS Data Interface Clocking Example rails, whether generated internally or externally, reducing external
component count, simplifying use, and offering huge benefits to
PCB layout, routing, and design density.
For externally generated supply rails, excellent choice LDO regula-
tors are the LT3045 or ADP150, which both offer ultra-low noise
and excellent power supply rejection. For high efficiency, step-down
switching regulators, the LT8604C is a good choice; however, great
Figure 47. Dual Lane, LVDS Data Interface Clocking Example care must be taken in the design of the switching regulator circuity
because switching frequencies are likely to be within the application
In cases where the SPI data interface (see the SPI Data Interface signal bandwidth, and although the AD4080 has high AC power
section) is used to access conversion results from the result FIFO supply rejection on its supplies, appropriate consideration must be
(see the Result FIFO section) again, it is important that the CNV given to the supply rails.
source jitter is carefully considered to achieve the required perform-
ance. In the case shown in the SPI data interface clocking example
(see Figure 48) , an oscillator directly provides the conversion
clock, and the data is asynchronously clocked from the FIFO by
a microcontroller unit (MCU). Optionally, as shown in Figure 48,
the general-purpose input and output pins can be configured to
control the result FIFO operation (see the GPIO Pins section and
the Result FIFO section).

Figure 48. SPI Data Interface Clocking Example

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Data Sheet AD4080
DIGITAL INTERFACE

OVERVIEW Common to both the LVDS and SPI data interfaces are the follow-
ing flexible features, which reduce the burden on the chosen digital
The AD4080 digital interface consists of a 4-wire SPI for device host:
configuration, four general-purpose input and output (GPIO) pins,
a conversion data access interface with selectable output format ► Multilane data transfer: enables sustained data throughput at
(LVDS or SPI data interface), and a conversion start input (CNV+ reduced interface clock speeds.
and CNV−) that can be configures for LVDS or CMOS level signal- ► Test pattern generation: facilitates interface integrity checks.
ing.
Additionally, for the LVDS only, there is the option to set a configu-
Register Interface rable output drive.
By default, the LVDS interface is selected on power up and after a
The AD4080 configuration registers are accessed through the
reset. As can be seen in Figure 49, for LVDS, the data path of the
SPI configuration interface (see the SPI Configuration Interface
ADC results is routed though the offset and gain correction block
section).
where there is the option to:
ADC Conversion Control ► Continuously read, directly, the raw ADC conversion results.
The ADC acquires a sample and initiates a conversion operation on ► Continuously read the ADC results processed by a user-selected
the rising edge of the convert start signal, applied at the CNV+ and digital filter (see the Digital Filter section for details).
CNV− pins. There are two possible configurations for the electrical ► Read up to 16k unfiltered results from the FIFO.
signaling at the convert start input pins: CMOS or LVDS. ► Read up to 16k digitally filtered results from the FIFO.

CMOS is the default mode on power up and after reset. CMOS

requires that the CNV− pin be tied to the digital interface ground
(IOGND). In this mode, the convert signal must be a CMOS logic
signal referenced to IOGND and applied at CNV+, with logic levels
according to the digital inputs (CNV, GPIOx, DCS, and DCLK)
parameters in Table 1.
To switch to LVDS mode, the LVDS_CNV_EN bit of the ADC Data
Interface Configuration B register (see the ADC Data Interface Con- Figure 49. LVDS Data Interface Options
figuration B Register section, Address 0x16) must be set to 1. In
this mode, an external 100 Ω termination resistor must be installed If configured for the SPI data interface, as can be seen in Figure 50,
between the CNV+ and CNV− pins, as close to the AD4080 as the available data paths are as follows:
possible. In LVDS mode, the CNV+ and CNV− pins must be driven
► Read up to 16k unfiltered results from the FIFO.
differentially with an LVDS driver conforming to the levels specified
in the LVDS I/O (EIA-644) parameters in Table 1. Care must be ► Read up to 16k digitally filtered results from the FIFO.
taken to closely match the CNV+ and CNV− differential signal pair
routing and to use controlled impedance to ensure signal integrity.

ADC Conversion Data Interface

Two signaling format options are available to access conversion
results:
► LVDS level signaling (LVDS data Interface)
Figure 50. SPI Data Interface Data Path Options
► CMOS level signaling (SPI data interface)

The choice of interface is usually determined by the requirements Additional features specific to the selected interface format are also
and constraints of the application at hand. For example, if contin- available and are described in the LVDS Data Interface section and
uous fast data acquisition is required, then the LVDS signaling the SPI Data Interface section.
interface is typically the preferred option. If the application requires SPI CONFIGURATION INTERFACE
only noncontinuous bursts of data acquisitions, then either the
LVDS or the SPI data interfaces can be used. The capabilities of All serial transactions between the system host and the AD4080
the digital interface host can also determine which interface option configuration registers are executed using the configuration SPI.
is chosen. Each serial transaction consists of at least one instruction phase
during which the desired memory operation, that is, read or write,

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Data Sheet AD4080
DIGITAL INTERFACE

and the starting address for the transaction are transmitted to the SPI Register Interface
AD4080. The instruction phase is immediately followed by a data
transaction phase during which one or more bytes of information The configuration register interface is an SPI that enables both
is exchanged between the host and the AD4080. This content is device configuration and system status monitoring. This interface
framed by a continuous assertion of the interface chip select ( CS ) is configured for 4-wire, full-duplex operation. Dedicated interface
as illustrated in the generic timing presented in Figure 51 and pins for the interface chip select (CS), serial clock (SCLK), and
Figure 52. serial data input (SDI) are intended for direct connection to the host
controller. By default, at power-up or after a software reset, the
configuration interface SDO function is enabled and assigned to the
GPIO0 pin.
The configuration interface timing convention implemented in this
design is consistent with SPI Mode 3, clock polarity (CPOL) =
1, clock phrase (CPHA) = 1. As such, the serial clock (SCLK) is
expected to idle high and the state of the data pins, SDI and SDO,
are updated on the falling (leading) edge of the clock such that
these pin can be sampled on the subsequent rising (trailing) edge.
See the ADI Analog Dialogue, Introduction to SPI Interface article
for more details regarding the SPI and SPI modes.
The memory access controller associated with this interface sup-
Figure 51. Generic SPI Configuration Frame, CRC Disabled
ports a number of user-programmable options accessible through
the interface configuration memory space (Address 0x00 to Ad-
dress 0x11). The available options for the AD4080 are listed and
described in Table 14.

Figure 52. Generic SPI Configuration Write Operation, CRC Enabled

Table 14. Configuration Memory Controller Options Summary
Interface Option Description
Software Reset (SW_RESET, Resets the internal configuration memory to the default state (except for ADDR_ASCENSION bit). Data FIFO is unaffected. Only use this
SW_RESETX) reset method once the ADC is in an idle state, where conversions are not clocked, and any existing conversion is completed. See the
Software Reset section for details.
Address Ascension Selecting this option changes the behavior of the memory controller address counter from decrementing (default) to incrementing. This
(ADDR_ASCENSION) change affects multibyte transfers, for example, when accessing a multibyte register as a single entity or when streaming mode is enabled.
The selection impacts the starting address for multibyte register accesses in strict register access mode. See the Address Ascension
Selection section for details.
Short Instruction Selecting this option reduces the length of the address field in the instruction word from 15 bits to 7 bits.
(SHORT_INSTRUCTION)
Single Instruction Selecting this option changes from the default streaming mode to single instruction mode, which requires the host controller to transmit an
(SINGLE_INST) instruction for each register access within a given SPI frame. The size of an entity is dependent on the strict register access setting and
whether or not the register is multibyte. This feature allows random access to the memory space during configuration. See the Instruction
Mode Selection section for details.
Strict Register Access Selecting this option instructs the memory controller to treat a multibyte register as a single entity, generating a fault when a partial access
(STRICT_REGISTER_ACCESS) is attempted. See the Strict Access Selection and Multibyte Registers section for details.
CRC Enable (CRC_ENABLE, Selecting this option enables a cyclic redundancy check (CRC) to verify the integrity of data sent to and received from the host. See the
CRC_ENABLEB) Configuration Cyclical Redundancy Check (CRC) section for details.
Status Data Transmission Selecting this options enables the transmission of status data through the SDO line during the instruction phase of the data frame. See th
(SEND_STATUS) eStatus Data Transmission section for details.

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Data Sheet AD4080
DIGITAL INTERFACE

Table 14. Configuration Memory Controller Options Summary (Continued)

Interface Option Description
Loop Count (LOOP_COUNT) Sets the data byte count before looping to the start address. When streaming data, a nonzero value sets the number of data bytes written
before the address loops back to the start address. A maximum of 255 bytes can be written using this approach. A value of 0x00 disables
the loop back so that addressing wraps around at the upper and lower limits of the memory. After writing this register, the loop value applies
only to the following SPI instruction and auto clears upon the end of that instruction.

Instruction Phase from the host for a given entity are inconsistent, the register update
terminates and all subsequent data in the given frame is treated
An instruction phase immediately follows the assertion of the CS as invalid as well. The checksum computation for the interface
pin (Logic 0) and is terminated by transmission of a complete CRC function is described in detail in the Configuration Cyclical
instruction packet or deassertion of CS. The instruction packet Redundancy Check (CRC) section.
starts with a single command bit indicating the operation type (Logic
1 for read, and Logic 0 for write), which is then followed by the start Note that, during the data phase of a write operation, the SDO
address for the operation. By default, the address is 15-bit long, output is driven to Logic 0 when the product is not reporting the
but the data interface has an optional short instruction mode, in latest CRC checksum to ensure a valid data state is presented to
which, it is reduced to 7 bits. The short instruction mode is enabled the host controllers SDI pin.
by setting the SHORT_INSTRUCTION bit = 1 in the Interface
Configuration B register (see the Interface Configuration B Register Read Access
section, Address 0x01).
The SPI enables read access to the configuration registers to
validate previous configuration writes, read the device identification,
Data Phase
or verify the interface status.
Each instruction phase is immediately followed by an associated When CS is forced low, a new serial instruction phase begins.
data phase, during which data is either shifted out of the serial The first bit sent in the instruction phase is the command bit, and
data output (SDO) on the falling edge of SCLK (read access) or when it is forced high (Logic 1) this indicates a read operation.
is shifted into the device configuration memory through SDI on The command bit is followed by an address that, for the read
the rising edge of SCLK (write access). The minimum size of the operation, indicates the start address for the register space to be
data payload is defined as a single byte; however, it can include accessed. As previously described in the Instruction Phase section,
multiple bytes depending on the depth of the register addressed the address has a default length of 15 bits, but the address can be
and the interface configuration settings for the SINGLE_INST and optionally shortened to 7 bits.
STRICT_REGISTER_ACCESS bits (Register 0x01, Bit 7, and Reg-
ister 0x10, Bit 5, respectively. During the subsequent data phase, content from the addressed
register space is shifted out, MSB first, on the SDO line on the
Write Access falling edge of SCLK. The number of bytes transmitted in any
one data frame is determined by the interface configuration set-
When CS is forced low, a new serial instruction phase begins. ting selections for the SHORT_INSTRUCTION and STRICT_REG-
The first bit sent in the instruction phase is the command bit, and ISTER_ACCESS options as demonstrated in the examples shown
when it is forced low (Logic 0) this indicates a write operation. The in the Instruction Mode Selection section and the Strict Access
command bit is followed by an address that, for the write operation, Selection and Multibyte Registers section.
indicates where the information received in the subsequent data
phase will be stored. As previously described in the Instruction Instruction Mode Selection
Phase section, the address has a default length of 15 bits, but the
address can be optionally shortened to 7 bits. The configuration interface memory controller defaults to streaming
mode upon power up (SINGLE_INST = 0). In streaming mode, mul-
Following the instruction phase, an integer number of bytes contain- tiple, contiguous registers are accessed in a single SPI frame, start-
ing the data payload for one or more registers in the configuration ing at the address specified in the instruction phase. In streaming
memory are transmitted to the AD4080. The size of the payload mode, only one instruction phase is permitted per SPI frame, requir-
in this data phase is bounded by the selected SINGLE_INST and ing a new SPI frame be initiated for changing access commands
STRICT_REGISTER_ACCESS interface options as described in or otherwise access a noncontiguous address in the register space.
the Strict Access Selection and Multibyte Registers section. Each For each byte transferred during the subsequent data phase, the
data byte is loaded into the addressed register as it is received, internal address counter is automatically updated according to the
assuming the interface CRC is disabled. If the CRC is enabled, setting of the ADDR_ASCENSION bit in the Interface Configuration
however, the addressed data register is only loaded if the internally A register (see the Interface Configuration A Register section), in
computed checksum matches the CRC value received from the the way specified by Table 15.
host. In the event that the computed CRC and received checksum

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Data Sheet AD4080
DIGITAL INTERFACE

Table 15. Address Ascension Selection is followed by either a payload consisting of data for the byte-wide
ADDR_ASCENSION Bit Address Controller Behavior register (DATA), least significant (LSBYTE), and most significant
Value (STRICT_REGISTER_ACCESS = 1) bytes (MSBYTE) of the multibyte register, or, in the case of a
0 (Default) Decrement Address. Multibyte registers are accessed read access, padding bits. As a convention, it is recommended to
by addressing the most significant byte address. pass Logic 1 to SDI during a read access to avoid accidentally
1 Increment Address. Multibyte registers are accessed addressing address zero for write access.
by addressing the least significant byte address
In single instruction mode (SINGLE_INST = 1), the memory access
Figure 53 illustrates the generic SPI frame formatting for a serial controller requires an instruction phase to transmit for each register
transaction using the default interface configuration. In this exam- accessed in a given SPI frame as illustrated in Figure 54. This
ple, a portion of the configuration register space consisting of mode is useful when access to nonadjacent sections of the register
a byte-wide register and a multibyte register is accessed. The space is required in a given SPI frame. Note that, the same access
address for the byte-wide register resides in the most significant flexibility can be achieved in stream mode by initiating a new SPI
address (ADDRESS) and the most significant byte of the multibyte frame for each unique register access.
register resides in the least significant address of the register The single instruction mode is selected by setting SINGLE_INST
segment. By default, the ADDR_ASCENSION property is set to = 1 in the Interface Configuration B register (see the Interface
descending, indicating that the address for the most significant Configuration B Register section, Address 0x01).
register is passed to the host controller during the instruction
phase. Depending on the selected operation, the instruction word

Figure 53. Interface Access Example, Default Interface Configuration, Streaming Mode (ADDR_ASCENSION = 0)

Figure 54. Interface Access Example, Single Instruction Mode (SINGLE_INST = 1), All Other Interface Options Default

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Data Sheet AD4080
DIGITAL INTERFACE

Address Ascension Selection section. The length of each register, in bytes, is captured in Table
31 in addition to other characteristic information.
The address ascension selection (ADDR_ASCENSION) bit, as de-
scribed in previous sections, determines how the internal interface The function of the STRICT_REGISTER_ACCESS bit is to indicate
address pointer is updated for each byte of data transmitted to the to the interface controller that all bytes of a multibyte register must
AD4080 in streaming mode (SINGLE_INST = 0). If using single be accessed in the current frame for valid communication to have
instruction mode (SINGLE_INST = 1), each register is directly occurred. In the event a multibyte register is only partially accessed,
addressed through its own instruction phase as illustrated in Figure an interface fault is generated in the Interface Status A register
54, and thus, the address pointer is not updated. Regardless of (see the Interface Status A Register section, Address 0x11), and
the setting for SINGLE_INST, the ADDR_ASCENSION bit directly the partial content update is discarded. The intent of this restriction
impacts the formatting of the SPI frame in terms of selection of is to ensure that corresponding configuration quantities are updated
the instruction phase starting address and byte order of the data in a manner that produces the desired device operation. The
phase payload. This impact is described in greater detail in the access restriction function is enabled by default (STRICT_REGIS-
Strict Access Selection and Multibyte Registers section as much TER_ACCESS = 1) and can be disabled by clearing the access bit
of the data formatting is dependent on this interface configuration (STRICT_REGISTER_ACCESS = 0) in the Interface Configuration
selection. The ADDR_ASCENSION selection bit is located in the C register (see the Interface Configuration C Register section,
Interface Configuration A register (see the Interface Configuration A Address 0x10). With register access restriction disabled, each byte
Register section, Address 0x00). of the configuration memory can be independently addressed;
however, it is then incumbent on the software to correctly configure
As summarized in Table 15, the ADDR_ASCENSION bit is cleared any multibyte registers in the device memory to achieve the desired
by default, resulting in the address pointer decrementing by one behavior.
for each data byte transmitted. In this decrement configuration
(ADDR_ASCENSION = 0), the address pointer decrements from The decision to enable or disable the register access restriction
the starting address indicated in the instruction phase by one for has implications with regards to the correct construction of the
each data phase byte received until the counter reaches Address SPI frames containing one or more multibyte register accesses.
0x0000. If additional bytes are received, the pointer automatically When STRICT_REGISTER_ACCESS is disabled, each byte of a
rolls over to the maximum address value, 0x7FFF; the rollover multibyte register is treated as a singular element. Furthermore,
behavior is fixed, and therefore, independent of the SHORT_IN- the interface does not indicate a fault if all bytes of the register
STRUCTION value or the physical address space occupied by the are not programmed, or if the bytes are programmed in a random
user configurable registers. It is important to understand this behav- order, and therefore, it is incumbent on the host to ensure that the
ior to avoid generating interface errors associated with attempting content of those registers are updated in a manner that produces
to access one or more invalid register addresses. Limit register the desired function in the device.
access to the register address space associated with the device When STRICT_REGISTER_ACCESS is enabled, specific access
configuration as described in the Configuration Registers section. rules are enforced to ensure consistency between the data and the
Alternatively, the ADDR_ASCENSION bit can be set (ADDR_AS- expected behavior of the device. To understand how these rules
CENSION = 1), resulting in the address pointer incrementing by apply to multibyte registers in the configuration memory, it is impor-
one, starting at the address identified in the instruction word, for tant to understand how the memory is organized. By convention,
each data phase byte received at the AD4080 in a given SPI multibyte registers are arranged in the configuration memory such
frame. In a manner similar to the descending case, the address that the most significant byte of the register is stored in the most
counter continues to increment for each data byte received until significant address of the assigned register space as illustrated in
the maximum address value, 0x7FFFF, is reached, after which the Figure 55. As a result, the byte order of the register content trans-
pointer rolls over to 0x0000. mitted in the data phase is dependent on the ADDR_ASCENSION
selection.
Strict Access Selection and Multibyte
Registers
Several locations in the AD4080 configuration memory have been
assigned as multibyte registers to support the storage require-
ments. For example, the offset correct register (see the Offset
Correction Register section, Address 0x25) and gain correction
register (see the Gain Correction Register section, Address 0x27)
are multibyte registers because the resolution of the correction
coefficients they contain exceeds a single byte. For a complete
listing of multibyte registers, refer to the Configuration Registers

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Data Sheet AD4080
DIGITAL INTERFACE

by the remaining byte(s) in that register in ascending order. Con-

versely, if ADDR_ASCENSION = 1, the least significant byte of the
multibyte register is accessed first followed by most significant byte.
As an extension of this concept, when STRICT_REGISTER_AC-
CESS = 1, any SPI frame that accesses a multibyte register as
the first entity in the data transfer must correctly set the starting
address in the instruction word to correspond to the ADDR_AS-
CENSION selection. In the case that the address counter automat-
ically decrements (ADDR_ASCENSION = 0), the starting address
is assigned to the register address for the least significant byte of
that multibyte register, and conversely, if configured to increment
automatically, the starting address must be set to the register
address for the most significant byte. As a result of the change
to ADDR_ASCENSION from automatic address decrement (0) to
Figure 55. Generic Byte Wide Memory, Multibyte Register Example automatic increment (1), Figure 53 and Figure 54 will change as
illustrated in Figure 56 and Figure 57 to accommodate the changes
As indicated in Figure 56, the address counter, by default, automat- in data phase byte order and instruction phase multibyte register
ically decrements (ADDR_ASCENSION = 0) such that the most start address.
significant byte of the multibyte register is accessed first, followed

Figure 56. Single Instruction Format, ADDR_ASCENSION = 0 (Descend), STRICT_REGISTER_ACCESS = 1 (Enabled)

Figure 57. Single Instruction Format, ADDR_ASCENSION = 1 (Increment), STRICT_REGISTER_ACCESS = 1 (Enabled)

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Status Data Transmission phase data over the SDI. This feature is controlled through the
SEND_STATUS bit in the Interface Configuration C register (see
The Interface Status A register (see the Interface Status A Reg- the Interface Configuration C Register section, Address 0x10), and
ister section, Address 0x11) and device status register (see the it is disabled by default. To enable this bit, set SEND_STATUS = 1.
Device Status Register section, Address 0x14) contain status data The status data that is sent is taken from the Interface Status A reg-
pertaining to the communications interface and the device itself, ister and from the device status register, but the content is different
respectively. This data enables troubleshooting of device configura- depending on the setting of the SHORT_INSTRUCTION bit in the
tion during development and also provides continuous coverage of Interface Configuration B register (see the Interface Configuration
potential communication issues between the host and the interface B Register section. (Note that the length of the instruction phase
once deployed. The SPI controller can access the data through also depends on this setting). See Table 16 and Table 17 for a
regular register read operations. However, the AD4080 can be con- description of the status data sent in each case, where the status
figured to autonomously transmit status data through the SDO line data is sent MSB first.
every time while the SPI controller is sending the SPI instruction
Table 16. Device Status Data Sent Through the SDO in Long Instruction Mode (SHORT_INSTRUCTION = 0)
Bit Name Description
15 Not applicable Bit 15 is always 0.
14 Not applicable Bit 14 is always 0.
13 FIFO_FULL Device Status Register Bit 7: FIFO Full Status Flag.
0: FIFO Not Full.
1: FIFO Full.
12 FIFO_READ_DONE Device Status Register Bit 6: FIFO Read Done Flag.
0: FIFO Read Not Done.
1: FIFO Read Done.
11 HI_STATUS Device Status Register Bit 5: High Threshold Detection Status Flag.
0: High Threshold Event Not Detected.
1: High Threshold Event Detected.
10 LO_STATUS Device Status Register Bit 4: Low Threshold Detection Status Flag.
0: Low Threshold Event Not Detected.
1: Low Threshold Event Detected.
9 ADC_CNV_ERR Device Status Register Bit 2: ADC Conversion Error Flag.
0: ADC Conversion OK.
1: ADC Conversion Error. A. Conversion period is lower than minimum value for speed grade. B. DSP error.
8 ROM_CRC_ERR Device Status Register Bit 1: Read Only Memory (ROM) CRC and/or Error Correction Code (ECC) Failure Flag.
0: ROM CRC Check OK.
1: ROM CRC and/or ECC Failure.
7 POR_ANA_FLAG Device Status Register Bit 3: POR Analog Status. Allows user to detect when an analog POR event has occurred. An analog POR
is triggered at power-up or when the logic supply drops to less than some threshold value, when the ADC reference drops to less
than some threshold value, or when the user issues a software reset.
0: Analog POR Flag Cleared.
1: Analog POR Event Detected.
6 POR_FLAG Device Status Register Bit 0: POR Status. Allows user to detect when a POR event has occurred. A POR is triggered at power-up
or when the logic supply drops to less than some threshold value or when the user issues a software reset.
0: POR Flag Cleared.
1: POR Event Detected.
5 NOT_READY_ERR Interface Status A Register Bit 7: Device Not Ready for Transaction. This bit is set if the user attempts to execute an SPI
transaction before the completion of digital initialization.
4 CLOCK_COUNT_ERR Interface Status A Register Bit 4: Clock Count Error. This bit is set when an incorrect number of clocks is detected in a transaction.

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Table 16. Device Status Data Sent Through the SDO in Long Instruction Mode (SHORT_INSTRUCTION = 0) (Continued)
Bit Name Description
3 CRC_ERR Interface Status A Register Bit 3: CRC Error. This bit is set when the SPI controller does not send a CRC value or when the CRC
value calculated by the device does not match the value received from the SPI controller.
2 WR_TO_RD_ONLY_REG_ERR Interface Status A Register Bit 2: Write to Read Only Register Error. Write to Read Only Register Attempted. This bit is set when
the user attempts a write to a register that is read-only.
1 REGISTER_PARTIAL_ Interface Status A Register Bit 1: Register Partial Access Error. This bit is set when a fewer than expected number of bytes are
ACCESS_ERR read from or written to in a multibyte register access. This bit is only valid when strict register access is enabled.
0 ADDRESS_INVALID_ERR Interface Status A Register Bit 0: Invalid Address Error. Attempt to read or write nonexistent register address. This bit is set when
the user tries to access register addresses outside the allowed memory map space.

Table 17. Device Status Data Sent Through the SDO in Short Instruction Mode (SHORT_INSTRUCTION = 1)
Bit Name Description
7 Not applicable Bit 7 is always 0.
6 POR_FLAG Device Status Register Bit 0: POR Status. Allows user to detect when a POR event has occurred. A POR is triggered at power-up
or when the logic supply drops to less than some threshold value or when the user issues a software reset.
0: POR Flag Cleared.
1: POR Event Detected.
5 NOT_READY_ERR Interface Status A Register Bit 7: Device Not Ready For Transaction Error. This bit is set if the user attempts to execute an SPI
transaction before the completion of digital initialization.
4 CLOCK_COUNT_ERR Interface Status A Register Bit 4: Clock Count Error. This bit is set when an incorrect number of clocks is detected in a transaction.
3 CRC_ERR Interface Status A Register Bit 3: CRC Error. This bit is set when the SPI controller does not send a CRC, or when the CRC value
calculated by the device does not match the value sent by the SPI controller.
2 WR_TO_RD_ONLY_REG_ERR Interface Status A Register Bit 2: Write To Read-only Register Error. This bit is set when the user attempts a write to a register that
is read only.
1 REGISTER_PARTIAL_ Interface Status A Register Bit 1: Register Partial Access Error. This bit is set when a fewer than expected number of bytes are
ACCESS_ERR read from or written to in a multibyte register access. This bit is only valid when strict register access is enabled.
0 ADDRESS_INVALID_ERR Interface Status A Register Bit 0: Invalid Address Error. This bit is set when the user tries to read from or write to a register
address outside the allowed memory map space.

Configuration Cyclical Redundancy Check controller is required to initiate a new SPI frame to retry configura-
(CRC) tion of the effected memory locations. In the event the CRC_ERR
is detected during a data read, the host controller must discard
The AD4080 includes optional configuration error detection based the received data and retry the data read in a new SPI frame.
on an 8-bit cyclical redundancy check algorithm. When enabled, an Clear the CRC_ERR flag before any attempt to initiate a repeated
8-bit checksum is inserted into the serial data output stream (SDO) read or write to the configuration memory to allow detection of any
during the data phase after each complete register transaction. De- subsequent errors. The error flag is cleared by writing code 0x08 to
pending on the register access type,that is, read or write, the host the Interface Status A register to set the CRC_ERR bit to a Logic 1.
is expected to conditionally provide a corresponding checksum to It is recommended that an immediate read of the Interface Status A
the SDI immediately following each register access. The interface register follows any attempt to clear the fault to validate the attempt
controller uses the host supplied checksum to determine if a CRC was successful.
error has occurred.
The configuration CRC function is disabled by default and can
A mismatch in the checksum values computed by the host and the be enabled through two complementary bit fields, CRC_ENABLE
AD4080 interface results in setting the CRC_ERR flag (CRC_ERR and CRC_ENABLEB, in the Interface Configuration C register (see
= 1) in the Interface Status A register (see the Interface Status the Interface Configuration C Register section, Address 0x10). To
A Register section, Address 0x11). During a write access, a CRC enable the CRC function, set the CRC_ENABLE bits to 1 and the
error invalidates the most recent register data as well as any sub- CRC_ENABLEB bits to 10. Each of the complementary CRC bit
sequent register data writes if in streaming mode (SINGLE_INST fields is 2-bit wide, and any combination other than that specified
= 0), which prevents loading any potentially corrupted data into results in the function remaining disabled. It is important to note
the configuration memory. In response to a CRC event, the host that once the CRC function is enabled, a valid checksum from

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the host controller is required for all subsequent serial transactions if STRICT_REGISTER_ACCESS = 1, a valid CRC is appended to
according to the conditions described in Table 18. If used, enable the data stream after all bytes of the addressed register are sent.
and validate the CRC function before writing to any of the device If STRICT_REGISTER_ACCESS is cleared (0), each byte transmit-
configuration registers. To validate the CRC function is enabled, ted must be followed by a valid checksum using the computation
follow the CRC configuration write with a SPI frame consisting of a rules that are described as follows.
read of both the Interface Configuration C register and the Interface
Status A register using a valid checksum for the read transaction. If For read access, the computation and transmission of a valid
enabled, the register contents for the CRC_ENABLE and CRC_EN- checksum from the host is required to validate the command and
ABLEB bits must be 1 and 10, respectively, and the CRC_ERR bit starting address only. In streaming mode (SINGLE_INST = 0),
in the Interface Status A register remains cleared (Logic 0). Once a CRC checksum is sent from the host controller after the first
confirmed, proceed with programming the remaining configuration register data payload only. Fill all subsequent register accesses
registers. in streaming mode with padding data. The AD4080 continues to
produce valid checksum values after each register read to allow
Table 18. Host Controller (SDI) Conditional Checksum Requirement validation in the host using the preceding data. As a new instruction
Summary phase is required for each register accessed in single instruction
Command SINGLE_INST Bit Value Check Sum Requirement mode, a valid host CRC checksum is required for each register
Write Streaming (0) or single After each data register payload accessed.
instruction (1)
In single instruction mode (SINGLE_INST = 1), the polynomial
Read Streaming (0) After the first register data payload is computed for each register using the default seed value of
following the instruction phase
0xA5, the instruction phase data, and depending on the access
Single instruction (1) After each data register payload command, the desired register or padding data. In streaming mode
The following CRC-8 polynomial is implemented in the AD4080 to (SINGLE_INST = 0), the checksum computation for the first register
compute the checksum for each register transaction: in the data stream is computed as if single instruction mode were
selected. Each subsequent register access checksum computation
x8 + x2 + x + 1 is seeded with the starting address for the current register and the
Each serial transaction is processed through this polynomial to corresponding data. Note that the starting address for multibyte reg-
generate the checksum on a per register basis. The data and seed isters changes with the ADDR_ASCENSION selection, assuming
values used for each checksum calculation are a function of the ac- the register access restriction is enabled (STRICT_REGISTER_AC-
cess command (read/write); ADDR_ASCENSION, STRICT_REG- CESS = 1). As previously described, the memory convention dic-
ISTER_ACCESS, and SINGLE_INST settings; and the location of tates that if ADDR_ASCENSION is set to 0, the address for the
the register data in the data stream as summarized in Table 19. least significant byte of the multibyte register serves as the starting
address. Conversely, if the ADDR_ASCENSION bit is set to 1, the
All register write access operations, regardless of SINGLE_INST address of the most significant byte of the multibyte register is
setting, require a valid CRC checksum to be sent from the host used.
following the data payload for each register. For multibyte registers,
Table 19. Configuration CRC Checksum Source Data Summary vs. SINGLE_INST and SPI Command
Single Instruction Mode (SINGLE_INST = 1) or
Checksum Streaming Mode First CRC Streaming Mode (SINGLE_INST = 0) after first CRC
Command Source Data Source Seed Data Source Seed
Write Controller Instruction and data 0xA5 Register data Current start address
AD4080 Instruction and data Register data Current start address
Read Controller Instruction and padding data 0xA5 Not required, send padding data
AD4080 Instruction and register content Register data Current start address

Figure 58. Streaming Mode Configuration with CRC Enabled, ADDR_ASCENSION = 1

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Figure 59. Single Instruction Mode Configuration with CRC Enabled, ADDR_ASCENSION = 1

Figure 60. Streaming Mode Configuration with CRC Enabled, STRICT_REGISTER_ACCESS = 0 (Disabled) , ADDR_ASCENSION = 0

Configuration SPI Frame

Figure 64. Long Instruction Mode, Data Status Enabled, CRC Enabled

Figure 61. Short Instruction Mode, Data Status Enabled, CRC not Enabled

Figure 62. Short Instruction Mode, Data Status Enabled, CRC Enabled

Figure 63. Long Instruction Mode, Data Status Enabled, CRC not Enabled

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Configuration SPI Timing

Write Data Frame

Figure 65. Configuration SPI Timing, Data Write Frame, 16-Bit Instruction Mode (Default)

Figure 66. Configuration SPI Timing, Data Write Frame, 8-Bit Instruction Mode, Single 8-Bit Register

Figure 67. Configuration SPI Timing, Data Write Frame, 8-Bit Instruction Mode, Streaming Mode, Multibyte Register

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Read Data Frame

Figure 68. Configuration SPI Timing, Data Read Frame, 16-Bit Instruction Mode (Default)

Figure 69. Configuration SPI Timing, Data Read Frame, 8-Bit Instruction Mode

Figure 70. Configuration SPI Timing, Data Read Frame, 8-Bit Instruction Mode, Steaming Mode, Multibyte Register

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Figure 71. Configuration SPI Timing, Data Read Frame, Continuous SCLK

LVDS DATA INTERFACE LVDS Active Data Lane Count

The LVDS interface can be configured to output the result data
LVDS Data Interface Configuration on either one or two data lanes, which is controlled by the
SPI_LVDS_LANES bit in the ADC Data Interface Configuration
The LVDS interface consists of up to five pairs of differential A register (see the ADC Data Interface Configuration A Register
signals. The data clock input pair (CLK+ and CLK−), echoed data section, Address 0x15). By default, this bit is set to 0 (one lane
clock output pair (DCO+ and DCO−), two data output lanes (DA+ active), and setting SPI_LVDS_LANES = 1 uses two data lanes.
and DA− , DB+ and DB− ), and optionally, the conversion clock can Note that this bit is also used to configure the number of active data
be configured as either an LVDS pair (CNV+ and CNV−) or as a lanes for the SPI.
CMOS using CNV+, where for this case, CNV− is connected to
GND. This user selection is configured using the LVDS_CNV_EN In single lane operation, Data Lane DA+ and Data Lane DA− is
bit in the ADC Data Interface Configuration B register (see the ADC enabled as the primary data output, and the conversion result is
Data Interface Configuration B Register section, Address 0x16). shifted out serially, MSB first, using 10 interface clocks applied to
The data lanes use a DDR scheme, and each scheme can support CLK+ and CLK− inputs per conversion. The result data is shifted
a throughput of up to 800 (Mbps). By default, LVDS is selected as out of the device on each edge of the echo clock outputs, DCO+
the primary data interface for accessing conversion results. and DCO−. The result MSB (D19) and all odd numbered data bits
are output on the falling edge of the interface clock. Conversely,
To achieve maximum throughput, it is necessary that while a con- the even numbered data bits are output on the rising edge of the
version is performed the result of the previous conversion is read. interface clock.
For this reason, it is critical that both the rising and falling edges
of CNV+ and CNV− are closely time aligned to the rising edge of In dual lane configuration, the result data is shifted out in parallel,
CLK+ and CLK−. To avoid introducing noise into the conversion 2 bits per clock edge, MSBs first. As a result, only five interface
result, the CLK+ and CLK− edge placement must be aligned to clocks are required per conversion. As the data access period is
within ±535 ps (tCCA) of the interface clock (CLK±), as specified in equivalent to the conversion period, the interface clock frequency
Table 2. is reduced by a factor of two relative to the single lane case. As a
consequence of the increased interface clock period, see the ADC
The data interface is highly configurable allowing the customization Result Latency and LVDS Interface Alignment section for the timing
of the output stream to meet a wide range of applications. Configu- and latency implications on both the single lane and dual lane count
ration options include the number of active lanes (1, 2), self clocked configurations.
and echo clock modes, interface test functions, and data encoding.
LVDS interface mode is used in applications where continuous
conversion at rates exceeding 1 MHz is required.
Transmission of the result data occurs MSB first and is output after
the amount of time specified in detail in the ADC Result Latency
and LVDS Interface Alignment section.

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Echo Clock Mode DB− data lane is enabled. The conversion clock (CNV+ and CNV−)
and data clock (CLK+ and CLK−) can be shared amongst multiple
In LVDS data interface mode, the DCO+ and DCO− pin pair AD4080 devices as long as care is taken to fanout the clock
is an echo clock output that provides a buffered and delayed network, such that the edge placement requirement is satisfied.
version of CLK+ and CLK− pin pair, facilitating data clocking to
the host controller data clocking. This feature is controlled by the In echo clock mode, data from enabled lanes is clocked out in
LVDS_SELF_CLK_MODE bit in the ADC Data Interface Configura- sync to both rising and falling edges of DCO+ and DCO− in a
tion B register (see the ADC Data Interface Configuration B Regis- DDR scheme. Figure 72 and Figure 73 illustrate the relevant LVDS
ter section, Address 0x16). By default, echo clock mode is active interface timing with respect to the DCO+ and DCO− echo clock for
(LVDS_SELF_CLK_MODE = 0). Setting LVDS_SELF_CLK_MODE single lane and dual lane configurations, respectively. Calculation
= 1 disables the DCO+ and DCO− output driver, putting the device of tMSB_READ is described in the ADC Result Latency and LVDS
in self clock mode (see the Self Clock Mode section) . Interface Alignment section.
When echo clock mode is active, the interface requires a minimum Consider matching the data clock (DCO+ and DCO−) and data
of three LVDS pairs (CLK+ and CLK−, DCO+ and DCO−, and DA+ lane (DA+ and DA−, DB+ and DB−) lane routing from the ADC to
and DA−) to be connected between the host controller and the the host processor for the physical layout to minimize timing skew,
AD4080. A maximum of five LVDS pairs are required if the CNV+ which may affect data recovery in the host. For additional routing
and CNV− pin pair is configured as an LVDS input and the DB+ and suggestions, see the Layout Guidelines section.

Figure 72. Continuous Conversion Timing, LVDS Data Interface, Single Data Lane, Echo Clock Mode

Figure 73. Continuous Conversion Timing, LVDS Data Interface, Dual Data Lane, Echo Clock Mode

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Self Clock Mode number of LVDS pairs required to interface with the host controller.
In this mode, the DCO+ and DCO− pins can be left disconnected;
In LVDS data interface mode, it is possible to disable the DCO+ therefore, in single-lane configurations, a minimum of two LVDS
and DCO− echo clock output (see the Echo Clock Mode section) pairs (CLK+ and CLK−, DA+ and DA−) are required to connect to
by setting LVDS_SELF_CLK_MODE = 1 in the ADC Data Interface each AD4080 instance. The interface connectivity can further be
Configuration B register (see the ADC Data Interface Configuration simplified by sharing the interface clock (CLK+ and CLK−) between
B Register section, Address 0x16). This setting puts the device multiple AD4080 instances.
in self clock mode disabling the DCO+ and DCO− output driver,
with the benefit of saving interface power as well as reducing the

Figure 74. Continuous Conversion Timing, LVDS Data Interface, Single Data Lane, Self Clock Mode

Figure 75. Continuous Conversion Timing, LVDS Data Interface, Dual Data Lane, Self Clock Mode

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LVDS Manchester Encoding Mode transfer of this result data is under the control of the LVDS of
CLK+ and CLK−, there is an additional (1.5 × tCLK) that must
This mode is accessed via the ADC_DATA_INTF_CONFIG_B reg- be allowed to guarantee a fully completed result is transferred to
ister (Address 0x16), which produces Manchester encoding of the the interface for read back. The user must calculate the correct
result data in compliance with IEEE 802.3. This mode can be required LVDS_CNV_CLK_CNT value and configure the ADC Data
used in isolated data applications where the converter supplies can Interface Configuration B register (see the ADC Data Interface
be floated and the data outputs capacitively coupled to the host Configuration B Register section) according to the conversion rate
controller. By ensuring that the mean output of each data lane is and tCLK used.
0, the receiver side common-mode voltage is not disturbed by the
result pattern. For minimum latency, the correct LVDS_CNV_CLK_CNT value to
use for a particular conversion rate is calculated as (tMSB/tCLK +
Manchester encoding is available in dual lane LVDS mode only so 1.5). This number is rounded down to the nearest integer value.
that the maximum data throughput is achievable with the maximum
400 MHz LVDS clock rate. The maximum tMSB time is specified as 22.4 ns with gain error
correction enabled (see the Gain Error Correction section). For a
Figure 76 shows an example how this isolation can be implement- 40 MSPS conversion rate in single lane LVDS with a 400 MHz
ed. Note that the LVDS 100 Ω termination resistor prior to the LVDS clock, this is calculated as 22.4 ns/2.5 ns + 1.5, yielding a
isolation capacitors is required. setting of 10 for the LVDS_CNV_CLK_CNT. Conversion latency is
then determined as time, aligned to the falling edge of the CLK
signal, described as tMSB_READ or latency in the timing diagram,
which can be calculated as (LVDS_CNV_CLK_CNT + 0.5) × tCLK.
For the given example, the single lane latency is calculated as (10 +
0.5) × 2.5 ns + tCYC = 46.25 ns latency.
Taking a dual lane example, the same formula is used, again taking
a 40 MSPS example, again with gain error correction enabled,
the LVDS clock runs at 200 MHz and yields (22.4 ns/5 ns) +
1.5, resulting in an LVDS_CNV_CLK_CNT of 5, and a total result
latency of (5 + 0.5) × 5 ns + tCYC = 52.5 ns latency.
Both of these examples are calculated to achieve the minimum
latency, and it is possible to use a higher LVDS_CNV_CLK_CNT
value, whereby latency is increased by tCLK for each +1 unit in-
crease in the LVDS_CNV_CLK_CNT value.
Figure 76. Isolated LVDS
Figure 77 and Figure 78 serve as aids to describe the placement
ADC Result Latency and LVDS Interface of the ADC result data onto the LVDS interface controlled by the
Alignment LVDS_CNV_CLK_CNT. Figure 77 shows that a new result is inter-
nally completed after (tCYC + tMSB), and this result is now available
WhenAD4080 is configured for LVDS interface mode, each conver- to the interface, signified here also by a notional tMSB_AVAILABLE
sion result is placed into the LVDS interface output shift register(s). (introduced only for the purposes of the Figure 77 explanation).
The LVDS_CNV_CLK_CNT bits in the ADC Data Interface Config- As this example represents a 40 MSPS conversion rate, Figure 77
uration B register (see the ADC Data Interface Configuration B shows that the LVDS_CNV_CLK_CNT setting of 10 is the earliest
Register section, Address 0x16) is used to configure the point the conversion result can be loaded to the LVDS interface. One
in time when the conversion result data is loaded into the LVDS additional full tCLK cycle is required (a complete cycle being CLK+
interface output shift register(s). The total time from the rising falling edge to next CLK+ falling edge) is required to move the MSB
edge of a convert pulse to when the MSB of that conversion to the output. This cycle is highlighted within Figure 77 also with a
request is internally available to transfer to the output register is notional tMSB_READ indicator for illustrative purposes only.
defined as (tCYC + tMSB), both specified in Table 2. Because the

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Figure 77. Single Lane LVDS, Echo Clock Mode, LVDS_CNV_CLK_CNT Position Example

Figure 78. Dual Lane LVDS, Echo Clock Mode, LVDS_CNV_CLK_CNT Position Example

Table 20. Valid LVDS_CNV_CLK_CNT Settings The maximum tMSB of 22.4 ns, that is with the gain error correction
Clock Count Number enabled (see the Gain Error Correction section), is used for all
LVDS_CNV_CLK_CNT
calculations in Table 21. On power-up, the value of the gain error
Settings Single Lane Mode Dual Lane Mode
correction is 0x200, disabling the correction and allowing for a lower
0b0000 3 3 latency result. In this case, tMSB is 18 ns and a latency of 46.25 ns
0b0001 4 4 can be achieved.
0b0010 5 5 Using this example, the same formula is used, again taking a single
0b0011 6 1 lane 40 MSPS example, the LVDS clock runs at 400 MHz and
0b0100 7 2 yields (18 ns/2.5 ns) + 1.5, resulting in an LVDS_CNV_CLK_CNT of
0b0101 8 Selection not valid 8 and a total result latency of (8 + 0.5) × 2.5 ns + tCYC = 46.25 ns
0b0110 9 Selection not valid latency.
0b0111 10 Selection not valid To aid alignment of this valid result data position with the digital host
0b1000 1 Selection not valid of the user, the ADC Data Interface Configuration A register (see
0b1001 2 Selection not valid the ADC Data Interface Configuration A Register section, Address
0x15) contains access to the interface check feature enabled by
As a overview guide, Table 21 indicates the minimum required setting the INTF_CHK_EN bit. When this bit is set, the ADC results
LVDS_CNV_CLK_CNT settings for various conversion rates. are no longer output on the interface, and the output is replaced
with a fixed pattern 20b1010 1100 0101 1101 0110 (0xA C5D6).

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This feature allows the user to align and test the data interface to between the AD4080 and its digital host controller. Note that this
their digital host. When the INTF_CHK_EN bit is unset, the normal feature was specifically designed to help output LVDS data with the
conversion results are output to the LVDS interface immediately. LVDS clock of the digital host by using static data, and the feature
This method is useful for alignment, particularly for self clock mode does not indicate if the LVDS_CNV_CLK_CNT setting is used.
cases where unknown PCB propagation delays may be present
Table 21. LVDS_CNV_CLK_CNT Settings for Various Sample Rates
Sample Rate (MSPS) LVDS Lanes fCLK (MHz) tCLK (ns) (tMSB/tCLK) + 1.5 LVDS_CNV_CLK_CNT Setting
40 1 400 2.500 10.46 10
35 1 350 2.857 9.34 9
30 1 300 3.333 8.22 8
25 1 250 4.000 7.1 7
20 1 200 5.000 5.98 6
15 1 150 6.666 4.86 4
40 2 200 5.000 5.98 5

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LVDS Data Transfer Latency ► LVDS clock period, tCLK

► Number of active LVDS lanes, NLANES
Where the user is concerned in knowing the overall latency from
when an individual ADC conversion is initiated to the time when ► Number of bits to be read, NBITS
the LSB has reached the host controller, it is important to consider Calculate the latency as follows:
the data transfer latency. The total latency observed is the sum of
NBITS
the ADC latency and the data transfer latency, in this case, the Data Transfer Latency = × tCLK
NLANES
LVDS_CNV_CLK_CNT is set to achieve minimum ADC latency.
Additional clock cycles more than the minimum required incur For applications that require extremely low latencies, note that as
additional LVDS clock cycles of latency to the overall latency, as is the data is transferred MSB to LSB in both single and dual lane
shown in Figure 79. modes, and that there is no requirement to fully read a result from
The data transfer latency on the LVDS interface depends on the the interface, the data transfer latency can be reduced for lower
following parameters: resolution results (that is, NBITS can be chosen to be smaller than
the maximum 20 bits available).

Figure 79. LVDS Data Transfer Latency

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LVDS Output Differential Drive interface and can be left at their power-on defaults or another con-
venient value. Because the driver is disabled, the DCO+ and DCO−
The AD4080 supports selection of the LVDS output differential output pins can, therefore, be left disconnected in the hardware
voltage from one of three predetermined differential amplitudes design as these pins are unused.
of ±185 mV p-p, ±240 mV p-p, and ±325 mV p-p assuming a
termination resistance of 100 Ω across the differential pair. The As detailed in Table 22, the following LVDS pins are reconfigured as
output common-mode voltage of the LVDS drive is adjusted for CMOS input or outputs to realize the SPI data interface.
each selection automatically to ensure that the peak output voltage Table 22. LVDS/SPI Data Interface Pins Crossreference
remains within the IOVDD rail. The current default selection sets
LVDS Pin CMOS Pin Function
the differential amplitude at ±240 mV p-p. The output differential
voltage can be modified by writing to the LVDS_VOD bits of the CLK+ DCLK Data interface clock input
ADC Data Interface Configuration C register (see the ADC Data CLK− DCS Data interface chip select input
Interface Configuration C Register section, Address 0x17). DA+ SDOA Serial Data Output A
DA− SDOB Serial Data Output B
Data Interface Test Functions DB+ SDOC Serial Data Output C
DB− SDOD Serial Data Output D
Regardless of the selected output configuration, the AD4080 is
equipped with self test functions that enable verification of the As with LVDS configuration mode, SPI configuration selection al-
integrity of the data interface physical layer, including device pads, lows control of the number of active lanes. For SPI data interface
PCB interconnect, and the host interface connections. An interface configuration, the user has the option to configure single lane SPI
check function is available setting a fixed, 20-bit data pattern mode or quad lane SPI.
to output. Selection of this test function is made by writing to the
INTF_CHK_EN bit in the Data Interface Configuration A register SPI Active Data Lane Count
(see the ADC Data Interface Configuration A Register section,
Address 0x15). The SPI can be configured to output the result data on either one
or four data lanes, which is controlled by the SPI_LVDS_LANES
By enabling the built-in test function, access to conversion results bit in the ADC Interface Configuration A register (see the ADC
is suspended; therefore, only use this function at either power-up or Data Interface Configuration A Register section, Address 0x15). By
during an idle period when conversion results are not required for default, this bit is set to 0 (one lane active), and can be set to
normal system function. 1 to use four data lanes. Note that this bit also sets the number
Refer to the ADC Result Latency and LVDS Interface Alignment of active data lanes for the LVDS interface. The data order and
section for further information. pin assignment to the serial data output (SDOx) pins is detailed in
Table 23, and shown in Figure 86.
SPI DATA INTERFACE
Table 23. SPI Data Lane(s) Data Order and Pin Assignment
Output Data Order
SPI Data Interface Configuration One Active SPI Lane Four Active SPI Lanes
Serial Data Output Pin (SPI_LVDS_LANES = 0) (SPI_LVDS_LANES = 1)
For applications that do not require the interface bandwidth of the
LVDS interface, such as when using asynchronous capture into the SDOA Not applicable SDO 3
result FIFO, the data interface can be reconfigured into a single SDOB SDO 0 SDO 2
or quad lane, SPI data interface. In this configuration, the AD4080 SDOC Not applicable SDO 1
outputs data on either one or four CMOS data lanes simultaneously SDOD Not applicable SDO 0
at serial clock rates up to 50 MHz. The result data is shifted out
serially on the falling edge of the interface clock (DCLK). In SPI Data Interface CRC
configuration, the AD4080 results can be read at interface rates up
to 200 MHz when using four SPI lanes. To ensure the integrity of the result data, a CRC is appended
to the FIFO results. This CRC is always enabled and appended.
To select the SPI configuration, program the DATA_INTF_MODE The computation of the result checksum is independent of that of
bit of the Data Interface Configuration A register (see the ADC the configuration interface. The result is 24 bits in length and is
Data Interface Configuration A Register section, Address 0x15) with appended to each data result record acquired from the FIFO.
Binary Sequence 1’b1. Once configured for SPI mode, the AD4080
LVDS drivers are automatically disabled, including the echo clock Sign Extension
output (DCO+ and DCO−), preventing contention between LVDS
and CMOS functions. As a result, the LVDS_SELF_CLK_MODE When accessing the FIFO data with the SPI data interface, the
and LVDS_VOD settings no longer effect the operation of the data 20-bit resolution of the AD4080 is not a convenient length for
interfacing with microcontroller or microprocessor hosts. To make
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data access and storage simpler, the ADC result is sign extended to The desired function for each GPIO is defined by writing to the
24 bits. In this way, the data format aligns better with their selected GPIO Configuration A through GPIO Configuration C registers
host. (Address 0x19 through Address 0x1B), see the GPIO Configuration
A Register section through the GPIO Configuration C Register
GPIO PINS section. The configuration for each GPIO includes an output enable
The AD4080 GPIO pins are intended to simplify the development of bit, an output data bit, and a function selection. The output data
synchronous data acquisition applications by facilitating a simplified bit determines the logical state of the output when the GPO data
state control interface between the host processor, the data con- option is selected; otherwise, the output state is determined by
verter, and other related signal chain components. When configured the selected function, assuming the output is enabled. By default,
as an output, these GPIO pins can be assigned as an indicator of GPIO0 is enabled as an output, and the configuration SPI SDO
device status, a digital control for a related signal chain component, function is selected. All other GPIO outputs are disabled.
or a serial data lane for device configuration. In input mode, the Table 25 provides a brief description of the available AD4080 GPIO
GPIO pins allow pin programming of converter features such as functions. Each of the GPIO pins can be configured for any of the
digital filter synchronization (reset) and an external event trigger. following functions.
Table 24. GPIO Registers Overview
Register Bits Contents
GPIO_CONFIG_A GPIO_0_EN, Enable bits for each GPIO.
GPIO_1_EN, 0: Configures the GPIO as an input.
GPIO_2_EN, 1: Configures the GPIO as an output.
GPIO_3_EN
GPIO_CONFIG_A GPIO_0_DATA, The corresponding GPIO_x_SEL bit for each GPIO can be set to 0111b to read or write data to that GPIO.
GPIO_1_DATA, In this mode, GPIO_x_EN selects whether each of these data bits is read only or write only, depending on whether the GPIO is
GPIO_2_DATA, configured as an input or an output.
GPIO_3_DATA
When configured as an output, these bits are write only, the user can set the bits to a logic level that they need to output on the
GPIO.
When configured as an input, these bits are read only, the user can read the bits to determine the logic level input to on the GPIO.
If the corresponding GPIO_x_SEL is not set to 0111b, the GPIO_x_DATA is not valid as the GPIO is overridden with the selected
GPIO function
GPIO_CONFIG_B GPIO_0_SEL, Selection for the function mode of GPIO0 and GPIO1.
GPIO_1_SEL
GPIO_CONFIG_C GPIO_2_SEL, Selection for the function mode of GPIO2 and GPIO3.
GPIO_3_SEL

Table 25. GPIO_x_SEL Function Descriptions

GPIO_x_SEL Function Description
0000b Configuration SPI Configuration Serial Data Output. This configures the selected GPIO to be the SDO for the configuration SPI.
SDO
0001b FIFO full FIFO Memory Full Indication Output. This configures the selected GPIO to function as a FIFO full indicator. The FIFO full indicator
is set when the conversion result corresponding to the specified count in the FIFO watermark registers (see the FIFO Watermark
Register section, Address 0x1D and Address 0x1E)is loaded into the data FIFO. The FIFO full status bit is cleared by reading data
from the FIFO, and it is cleared when the first conversion result is moved from the FIFO to the data interface output shift register.
0010b FIFO read done FIFO Memory Read Completed Output. This configures the selected GPIO to function as a FIFO read done indicator. The FIFO read
done indicator is cleared by default when the FIFO is first enabled, and each time the last conversion result is moved from the FIFO
into the data interface output shift register. The FIFO read done is cleared when the MSB of the last FIFO result is read on the selected
data interface.
0011b Filter result ready Filter Result Ready Output. When the digital filter is enabled, this configures the selected GPIO to function as an indicator that new
data is available to read on the interface. This active low indication allows synchronization between the host and the AD4080 when
utilizing the integrated digital filter to oversample and decimate an incoming signal. The signal is driven low at the end of each filter
decimation period and is driven high again before the next decimated output is ready.

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Table 25. GPIO_x_SEL Function Descriptions (Continued)

GPIO_x_SEL Function Description
0100b HI_DTCT High Threshold Event Output. With threshold detection enabled, this configures the selected GPIO to indicate when the high level
threshold is crossed. The output is active high.
0101b LO_DTCT Low Threshold Output. With threshold detection enabled, this configures the selected GPIO to indicate when the low level threshold is
crossed. The output is active high.
0110b ALERT Status Alert (Active Low) Output. This configures the selected GPIO to function as the status alert for threshold event detection.
0111b GPIO data General-Purpose Output Mode. In this mode, the state of the corresponding GPIO_x_DATA bit in the GPIO Configuration A register
(see the GPIO Configuration A Register section, Address 0x19) is applied to the configured output.
1000b FILTER_SYNC Filter Synchronization Input (Active Low). This configures the selected GPIO to function as a synchronization signal for the digital filter.
When held low, this input holds the digital filter in reset.
1001b EXT_EVENT External Event Trigger Input. Event triggers when a logic high is detected on the configured GPIO input. This event can be used to
trigger the FIFO.

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OVERVIEW is crossed or monitor a GPIO configured as an input. An internally

generated event can then be used to set a flag in the configuration
The AD4080 includes several useful digital features that offer great memory or routed to a configured GPIO output to be used to alert
solution benefits to many applications. These features can be a host controller that a threshold condition is breached. It is also
individually enabled by the user, when required. A brief overview possible for a user to route an external signal to the AD4080 to be
follows for these features, in depth explanation and definition of used as an external trigger. An internally or externally generated
these features are found in the following sections. event can also be used to trigger the integrated result FIFO (see
► Event Detection: This feature allows the detection when the the Result FIFO section). The mechanism for this is explained
analog input has crossed user-configured thresholds. Such de- in the Event Detection for FIFO section. The threshold detection
tections can be flagged in the configuration registers, output to a compares a converted voltage code to a user-configured code
GPIO, or used to trigger the result FIFO. because this is done in a sample by sample basis, and events
► Result FIFO: This feature allows the acquisition of records of immediately trigger, level hysteresis setting is also configurable to
up to 16,384 conversion results into the on-chip memory. These prevent unwanted triggering.
acquisitions can be read back to the host controller via LVDS
or the SPI data interface. The results stored in the FIFO can
be either unprocessed ADC results or those that have been
processed through the digital filter feature.
► Digital Filter: This feature offers three different digital filter config-
urations, each with a wide range of decimation rates, allowing
oversampling benefits and the close control of the signal band-
width.
► System Error Correction Coefficients: Although the AD4080 of-
fers excellent factory calibrated precision with minimal offset and Figure 80. Internally Generated Event Detection Signal Path
gain errors, this feature allows the user to correct for signal chain
that may be present within their application. The Figure 80 serves as an aid with detailing the configuration and
operation of the event detection of the AD4080.
EVENT DETECTION
The AD4080 includes an event detection feature, whereby the user
can either indicate when a particular analog input threshold level
Table 26. Event Detection
INT_EVENT_EN Bit
(Address 0x1C) Mode Trigger Source Comment
0 External event GPIO_x_SEL = 4b1001, that is, configured for Event triggers when a logic high is detected on the
EXT_EVENT selected GPIO input.
1 Internal event ADC Results threshold detection is enabled. HI_THRESHOLD (Address 0x21 and Address 0x22) and
LO_THRESHOLD (Address 0x23 and Address 0x24) set
the upper and lower ADC result (or the digital filter result)
code threshold for the event to be triggered.

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Event Detection Timing configuration register (Address 0x1C) to allow HI_DTCT and
LO_DTCT to propagate to the ALERT signal. Any enabled GPIO
When event detection is enabled in the general configuration regis- set to output a status alert, that is, with GPIO_x_SEL set to
ter (see the General Configuration Register section), the HI_DTCT 0b0110, routes the ALERT signal to the GPIO to indicate when
and LO_DTCT signals indicate the occurrence of an internally an event occurs. A GPIO configured in this mode is normally
generated event. These signals can be routed internally through the high, with a logic low indicating that an event has occurred. As
following paths: indicated in the Figure 82 section, this GPIO remains low only
► HI_DTCT and LO_DTCT are directly accessible via an enabled while the threshold level is crossed, and it returns to logic high as
GPIO with GPIO_x_SEL set to 0b100 or 0b101, respectively, a soon as the threshold bound is no longer crossed, and the timing
threshold event can be monitored externally by a digital host via in Figure 81 is satisfied.
the GPIO. Logic 1 on a configured GPIO indicates detection of Event detection is synchronous to the rising edge of the CNV+. A
an event. latency of two conversion clock cycles exists from the first CNV+
► HI_DTCT and LO_DTCT can each be routed by setting the edge where the analog input crosses a threshold to a detected
HI_ROUTE and LO_ROUTE bits to 1, respectively, in the general event that is flagged in the device status register and to any GPIO
configuration register (Address 0x1C) to allow HI_DTCT and configured to route ALERT. As is evident in Figure 80, where both
LO_DTCT to propagate to the LO_STATUS and HI_STATUS bits the HI_DTCT flag and ALERT routed to a GPIO are shown, the
in the device status register (see the Device Status Register behavior, once the threshold level is no longer crossed, is different.
section, Address 0x14). These status bits can be monitored by When a CNV+ rising edge occurs where the analog input no
the digital host via the configuration SPI. Logic 1 on a configured longer crosses the set threshold, ALERT de-asserts two conversion
GPIO indicates the detection of an event. Each of these two cycles later, on the rising edge of CNV. Any HI_DTCT or LO_DTCT
bits are independently cleared when a 1 is written to these bits. already set is not cleared at this point. These signals are only
Power cycling or device reset also result in the bits clearing. cleared by writing 1 to the relevant bits in the device status register
► HI_DTCT and LO_DTCT can each be routed by setting the (Address 0x14) or where a device reset occurred.
HI_ROUTE and LO_ROUTE bits to 1, respectively, in the general

Figure 81. Event Detection Timing

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Threshold Detect Levels as well as making these available as HI_STATUS and LO_STATUS
flags in the device status register (Address 0x14).
The threshold detection of the AD4080 includes a hysteresis set-
ting. By configuring this setting, the user can ensure that unwanted
threshold triggering can be avoided. Figure 82 shows how this can
be achieved. A single hysteresis setting is configured, that is then
applied to both the HI_THRESHOLD and LO_THRESHOLD bits.
The high and low detection flags remain set until the hysteresis
thresholds are crossed.
Figure 83. FIFO Event Detection Logic

Event Detection ADC Data Result

The ADC data result, as shown in Figure 80, is dependent of the
selected data path. As is evident in Figure 94, where the digital filter
(see the Digital Filter section) is enabled, the output of the selected
filter refers to the ADC data result that is checked by the threshold
detection for event detection.
Figure 82. Threshold Detect Levels RESULT FIFO
A single port data FIFO was integrated into the AD4080 for applica-
Enabling Event Detection
tions where a reduced data interface transmission load is required
By default, after power on or reset, HI_ROUTE and LO_ROUTE and where asynchronous data capture and access is appropriate.
are set to Logic 0, masking the threshold level detection from This FIFO can serve to reduce the requirements for the digital host
generating any event alert. When enabled, the gated versions of controller and can, for example, enable the AD4080 to be deployed
these signals, HI_DTCT_GATED and LO_DTCT_GATED, are logic in systems using an MCU digital host. The data FIFO allows for a
NOR'd to generate the ALERT signal. If a user requires the use record of up to 16,384 data results to be captured per acquisition
of the HI_DTCT, LO_DTCT, or ALERT signals to flag an event burst without result loss due to data overflow. As a single port
occurrence externally, back to a digital host, the GPIO_x_SEL memory, simultaneous data interface read and ADC conversion
registers can be used to route any, or multiple, of these signals to result write operations are not permitted to the FIFO.
the GPIO pins. To allow synchronization of FIFO access between the host control-
ler and ADC, status flags are included to indicate if the memory
Event Detection for FIFO is full (FIFO_FULL) or if no new data available in the FIFO
Event detection can also be used to arm the on-chip FIFO. The (FIFO_READ_DONE), that is, there is no new data since the last
event detection for the FIFO can be triggered using either internal trigger was set, or the last FIFO data read back of a result record
or external events as detailed in the Table 26 section. has already been completed. When N = WATERMARK is reached,
that is, when the conversion result corresponding to the specified
To use the ALERT signal to trigger the FIFO, the HI_ROUTE count in the FIFO_WATERMARK register is loaded into the data
and/or the LO_ROUTE bits must be configured as required, and FIFO, memory is set as full, and the FIFO_FULL bit gets asserted
the INT_EVENT_EN bit must be set to 1, to use a combined in device status register (see the Device Status Register section,
ALERT output to trigger the FIFO. Alternately, when configured Address 0x4). The status bits can be accessed by reading directly
with the INT_EVENT_EN bit set to 0, a GPIO EXT_EVENT input from the device status register (Address 0x14) via the configuration
must be configured, and this input triggers the FIFO when a Logic SPI, appending the status to the data SPI frame, or by assigning
1 is presented on the GPIO. Because this event was generated the desired status flags to a GPIO pin by setting the required
externally, there is no ALERT signal generated. GPIO_x_SEL bit. Further details on these GPIO can be found in
The HI_THRESHOLD (Address 021 and Address 022) and the GPIO Pins section. The user can also select between various
LO_THRESHOLD (Address 0x23 and Address 0x 24) bits can modes of initiating the burst acquisition, which will be described
be used to configure the ADC output code thresholds for the further in the FIFO Mode Selection and Configuration section.
internal event detection. These bits can each be masked using
the HI_ROUTE and LO_ROUTE bits in the general configuration
register (Address 0x1C). Setting these bits logic high, routes the
bits to be used for the ALERT flag (that can be monitored using
a preconfigured GPIO), it is also enabled as a FIFO event trigger

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FIFO Mode Selection and Configuration the FIFO is disabled (FIFO_MODE = 00). The modes are designed
to fit the use case requirements of different applications., Table 27
There are four distinct modes in which the data FIFO of the AD4080 provides details about each FIFO mode and their applicable use
can be configured. The active mode is selected by setting the cases.
FIFO_MODE bits in the general configuration register (see the
General Configuration Register section, Address 0x1C). By default,
Table 27. FIFO Configuration Modes (FIFO_MODE)
FIFO_MODE Bit
Value FIFO Mode Description Use Case
00 FIFO disabled FIFO is not used. This value also resets and rearms the event Continuous convert mode, and FIFO is not in use.
trigger.
01 Immediate trigger mode In this mode, the data capture is initiated immediately after User is interested in burst acquisition(s) of [N
receipt of the first valid converter result and continues until [N = = WATERMARK] results, initiated by setting this
WATERMARK] results are loaded into the FIFO memory. FIFO_MODE, Bits[1:0] value.
Upon read back from the FIFO, FIFO_READ_DONE indicates
when [N = WATERMARK] results are read from the FIFO.
10 Event trigger capture, read The data capture into the FIFO memory is initiated by the User is interested in burst acquisition(s) of [N =
latest WATERMARK user-selected event method. The result counter initiates by WATERMARK] results, initiated by an event. Only result
the event, and data captures to the FIFO stop once [N = data after the event is of interest.
WATERMARK] results are captured.
Upon read back from the FIFO, FIFO_READ_DONE indicates
when [N = WATERMARK] results have been read from the
FIFO.
11 Event trigger capture mode, The data capture immediately initiates after the receipt of the User is interested in burst acquisition(s) of [N =
read all FIFO first valid converter result. WATERMARK] results initiated by an event. The full
The FIFO continuously fills until an event is detected. If no FIFO contents are read in this mode. In this mode, the
event is detected before the FIFO fills (that is, 16,384 results user can read [N = WATERMARK] results after the event
are written to memory), the memory continues to fill with the and (16,384 − [N = WATERMARK]) before the event.
oldest results discarded on a first in, first out basis. Only WATERMARK values that are multiples of four are
valid in this mode.
Upon receipt of the selected event method, a result counter
counts up to [N = WATERMARK]. Data capture stops once the
WATERMARK is reached. In this mode, once the FIFO is filled,
the position in the FIFO memory at which the event occurred
gets automatically stored in the FIFO_WATERMARK register.
The value read back from FIFO_WATERMARK allows the user
to distinguish which of the stored results captured before the
event from those that were captured after the event. Further
details can be seen in the example given in the Event Trigger
Capture Mode, Read All FIFO section.
Upon read back from the FIFO, FIFO_READ_DONE indicates
when 16,384 results are read from the FIFO. The full memory
read back contains [N = WATERMARK] results after the event.
If N in this case is less than 16,384, the remaining contents of
the FIFO contain the conversion results prior to the event.

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FIFO Event Detection clock. To enable the data FIFO in the general configuration register
(see the General Configuration Register section, Address 0x1C),
The FIFO is configured for capture in event detection mode the FIFO_MODE bits must be set to immediate trigger mode (01).
(FIFO_MODE = 10 or FIFO_MODE = 11, the following event detec- In this mode, the FIFO stores the results of the most recent
tion options (see the Table 26 section) are available. FIFO_WATERMARK samples and then automatically disables cap-
The general configuration register (Address 0x1C) contains the in- ture into the memory. The results can then be accessed through the
ternal event enable bit (INT_EVENT_EN) which determines wheth- SPI data interface or LVDS interface.
er the AD4080 FIFO is to respond to an external or internal event When the FIFO is enabled, each conversion result is loaded into
trigger. The default state of this bit on power on and reset is the internal memory on the rising edge of the convert start signal,
INT_EVENT_EN = 0, which is configured for an external event. CNV. Internal timing dictates that FIFO_WATERMARK + three con-
version clocks are required to write FIFO_WATERMARK sample
Asynchronous Data Capture results into the FIFO memory. See Figure 85 and Figure 86 for
To use the FIFO for asynchronous capture, first write to the FIFO additional information.
watermark register (see the FIFO Watermark Register section, The Figure 84 timing diagram shows an example where FIFO_WA-
Address 0x1D) with the number of conversions to be captured in TERMARK is set to 1000, and the first ADC results after the
each burst; any integer between 1 and 16,384 can be entered. event occurred is captured by the FIFO after the third CNV. After
If using GPIO to pass the FIFO status bits to the host controller, N = 1000, that is, it has reached the FIFO_WATERMARK value,
program those selections into the GPIO configuration registers prior FIFO_FULL is asserted, and data stops being captured into the
to initiating the capture. Refer to the GPIO Pins sections for further FIFO.
detail on GPIO configuration.
The final steps in initiating an asynchronous capture into the data
FIFO include enabling the FIFO and then starting the conversion

Figure 84. FIFO Data Capture Example, WATERMARK = 1000

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Asynchronous Read Access followed by a transfer of M bytes of conversion data; where M

equals the product of the total number of results specified in the
Access to the FIFO data is made through either a LVDS configura- FIFO_WATERMARK register (Address 0x1D and Address 0x1E)
tion (single lane only) or the multioutput SPI configuration of the and the integer length in bytes (for SPI data interface) of a sin-
data interface after the capture has completed. As a result, access gle conversion result. Note that the number of active data lanes
is asynchronous to the capture process, and there are no specific reduces the access period by a factor of 2 for each doubling of the
timing restrictions between the conversion and interface clocks. number of active lanes.
Synchronization between the data FIFO and the data interface
clock domain requires each read access to begin with a header

Figure 85. Asynchronous Capture Read Timing, Data FIFO Enabled, Single Data Lane

Figure 86. Asynchronous Capture Read Timing, Data FIFO Enabled, Quad Data Lane Configuration

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Figure 87. Asynchronous Capture Read Timing, Data FIFO Enabled, LVDS Configuration

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FIFO Timing Considerations on the next rising edge of CNV. The FIFO then advances to the
writing state after two further CNV clock edges and begins filling
Immediate Trigger Mode the FIFO until WATERMARK results are loaded and FIFO_FULL is
generated.
Figure 89 illustrates the timing relationship between the command
to arm the FIFO for data write access and the point at which Upon completion of reading the FIFO data, a rearming event for
the FIFO is armed. Figure 89 shows an example of where sin- immediate mode capture involves disabling the FIFO by writing 00
gle lane SPI data access is configured and FIFO_FULL and to FIFO_MODE then re-enabling by writing 01 to the FIFO mode
FIFO_READ_DONE are output to GPIO. Because a capture has to arm the FIFO for a new capture. As is the case with the initial
not yet been initiated, FIFO_FULL and FIFO_READ_DONE are arming, the FIFO advances to the idle state upon receipt of the first
driven low. A free running CNV clock is shown in this example. rising edge of CNV after the configure instruction to arm the FIFO is
Upon receipt of the update to the general configuration register issued. The sequence and timing is the same as for the initial FIFO
(Address 0x1C), the FIFO controller advances to an idle state arming. See Figure 89.

Figure 88. Immediate Trigger ModeArming

Figure 89. Immediate Trigger Mode Rearming

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Event Triggered Capture, Read Latest As in all cases of arming the FIFO, the first rising edge after
WATERMARK a FIFO_MODE write command arms the FIFO for data capture;
however, no data is written to the FIFO until an event of the
Event triggered (read latest) mode is used where there is interest selected method occurs.
only in the ADC data after an event occurs. This event can be
an internally generated event, where the AD4080 is running contin- Rearming the trigger involves a similar process to the immediate
uously, and the threshold detection is enabled to trigger an event mode rearming. The FIFO is firstly disabled by writing 00 to the
as soon as an ADC input threshold is crossed. Or, the user can FIFO_MODE bits before, and then rearmed by again enabling the
be independently monitoring the system or ADC input for an event, required capture mode.
and an external event trigger is user-issued via a configured GPIO.

Figure 90. Event Triggered Capture, Read Latest WATERMARK Arming

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Event Trigger Capture Mode, Read All FIFO

Event triggered mode can be used where ADC results immediately
prior to the event, as well as those after, are of interest to the user.
Once armed, the FIFO continuously fills with new ADC results,
storing up to, at most, 16,384 of the most recent results, wrapping
around and overwriting the oldest results in FIFO memory once
16,384 captures are made.
Once a trigger event occurs, the FIFO continues to capture WA-
TERMARK number of results after the event. Only multiples of four
are valid values to set the FIFO_WATERMARK register when using
this mode. After an even has occurred, and the WATERMARK
Figure 92. FIFO Event Capture Mode Read All FIFO Mode Example, Locating
number of results have been captured in the FIFO, no further Event Position in FIFO
new results are captured until the FIFO is rearmed. Once the
FIFO has stopped capturing, the FIFO_WATERMARK register is
automatically loaded with a value that represents the location in
the FIFO where the event occurred, as shown in Figure 91 and
Figure 92. The user must read back all 16384 FIFO results and
the value read back from FIFO_WATERMARK allows the user to
determine where in the FIFO result data that the even occurred and
also to distinguish between results that occurred before the event
and those which occurred after the event as shown in the Figure 92
diagram.

Figure 91. Event Capture Mode Read All FIFO Mode Example, FIFO Filling

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Figure 93. Event Trigger Capture Mode, Read All FIFO Rearming

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DIGITAL FILTER Benefits of Digital Filtering

The AD4080 includes the option of enabling an integrated digital The ADC result path can be configured to use the integrated digital
filter for applications where noise rejection by bandwidth limiting is filter feature. The filter configuration register (see the Filter Configu-
desired. As shown in Figure 94 and detailed as follows, there are ration Register section, Address 0x29) contains the FILTER_SEL
four paths available by which to route digital data: no digital filtering, bits that allow the user to bypass (default register setting) the
a sinc1 filter, a sinc5 filter, or a sinc5 compensated filter. digital filter or select from one of three filter options. Each filter has
unique bandwidth profile properties, which allows high flexibility in
Further details on each of these filters is described in the following allowing selection to be made depending on the end application
sections. To ensure the first filter result produces the correct data, requirements. Table 28 shows the −3 dB bandwidths achievable for
when a user makes a change to the filter selection, a reset must each user-selectable filter type. The SINC_DEC_RATE bits controls
be issued via the GPIO pin configured for filter synchronization the bandwidth and the data decimation factor.
(FILTER_SYNC).
These filters allow the user to programmatically control the noise
bandwidth of their signal chain and also can offer benefits by
reducing the amount filtering required in the analog front end, while
offering dynamic range improvement without the need for addition-
al components. The digital filter response sections have addition
details on the different filter profiles that include the following:
Figure 94. Digital Filter Selection Options ► Sinc1 has a wider bandwidth but is not optimized for pass-band
flatness.
► Sinc5 has a flatter pass-band response; however, with a reduced
bandwidth.
► Sinc5 + compensation is a filter highly optimized to give excellent
pass-band flatness with a ripple within ±0.1 dB.
Table 28. Filter Bandwidth
Filter Type SINC_DEC_RATE Decimation −3 dB Bandwidth
Sinc1 0000 2 0.25 × fS
Sinc1 0001 4 0.114 × fS
Sinc1 0010 8 0.56 × fS
Sinc1 0011 16 0.28 × fS
Sinc1 0100 32 0.14 × fS
Sinc1 0101 64 0.07 × fS
Sinc1 0110 128 0.035 × fS
Sinc1 0111 256 0.017 × fs
Sinc1 1000 512 0.09 × fS
Sinc1 1001 1024 0.004 × fS
Sinc5 0000 2 0.117 × fS
Sinc5 0001 4 0.525 × fS
Sinc5 0010 8 0.0256 × fS
Sinc5 0011 16 0.0127 × fS
Sinc5 0100 32 0.064 × fS
Sinc5 0101 64 0.032 × fS
Sinc5 0110 128 0.016 × fS
Sinc5 0111 256 0.008 × fS
Sinc5 + Compensation 0000 4 0.1015 × fS
Sinc5 + Compensation 0001 8 0.0506 × fS
Sinc5 + Compensation 0010 16 0.0253 × fS
Sinc5 + Compensation 0011 32 0.0127 × fS

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Data Sheet AD4080
DIGITAL FEATURES

Table 28. Filter Bandwidth (Continued)

Filter Type SINC_DEC_RATE Decimation −3 dB Bandwidth
Sinc5 + Compensation 0100 64 0.0063 × fS
Sinc5 + Compensation 0101 128 0.0032 × fS
Sinc5 + Compensation 0110 256 0.0016 × fS
Sinc5 + Compensation 0111 512 0.0008 × fS

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Data Sheet AD4080
DIGITAL FEATURES

Filter Decimation Configuration The decimation factor is set via the SINC_DEC_RATE bits in the
filter configuration register (see Table 62 for the encoding).
Configuration of the digital filter is done through the filter configura-
tion register (see the Filter Configuration Register section, Address The readiness of new filter data can be indicated to the host
0x29). The FILTER_SEL bits select the active filtering path (that controller via a GPIO pin by setting one of GPIO_x_SEL bits in
is, what filters are active), with each path having different allowed either GPIO Configuration B register (see the GPIO Configuration B
decimation rates (see Table 29). Register section, Address 0x1A) or GPIO Configuration C register
(see the GPIO Configuration C Register section, Address 0x1B) to
Table 29. Digital Filters Decimation Options According to FILTER_SEL Bits
Value
0011 (filter result ready (active low)). Until new data is available
to the interface, the data from the previous result remains in the
FILTER_SEL
output shift register. The user must ensure that the same LVDS
Bits Value Active Filter Allowed Decimation Rates
clock rate is maintained, and the user can either reread or disregard
0b00 No filtering (default) No decimation the repeated result data, which is shown in Figure 95, where a
0b01 SINC1 filter 2, 4, 8, 16, 32, 64, 128, 256, decimate by 4 example is used.
512, 1024
0b10 SINC5 filter 2, 4, 8, 16, 32, 64, 128, 256
0b11 SINC5 + compensation filter 4, 8, 16, 32, 64, 128, 256, 512

Figure 95. Digital Filter Decimate by 4 Frame Overview

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Data Sheet AD4080
DIGITAL FEATURES

Filter Reset Conditions Filter Synchronization

Direct LVDS Set GPIO_x_SEL to FILTER_SYNC to configure this input providing

synchronization to the controller of the user, which can be used
When accessing the filtered data directly via the LVDS interface, to synchronize the filters across multiple AD4080 devices. The
the AD4080 resets the filter by the following two methods: FILTER_SYNC signal is an active low input, and this signal must
be held low for a minimum of one conversion cycle to reset and
► By configuring the filter, by issuing a write to the filter configu-
synchronize the digital filter. Refer to Figure 96 for the timing
ration register, Bits[7:0] (see the Filter Configuration Register
requirements for a filter reset.
section, Address 0x29).
► By asserting a GPIO that’ is configured for FILTER_SYNC opera-
tion.

With FIFO
When the FIFO is enabled, the user must use a GPIO configured
as FILTER_SYNC to reset the filter for each FIFO acquisition.

Figure 96. Filter Reset Timing

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Data Sheet AD4080
DIGITAL FEATURES

Filter Result Ready Indicator a decimate by 2 setting, where three results (that is, WATERMARK
= 3) are configured to be stored in the FIFO. When using the
Setting the GPIO_x_SEL bits to 0011 configures the GPIO to output integrated digital filters with the FIFO, the filter must be reset prior
the FILTER_RESULT_RDY signal, which is an active low logic to each FIFO acquisition record. This reset must be given on the
signal that indicates to the host controller when each new filter first CNV rising edge, where the FILTER_SYNC signal must be
result is complete. When LVDS is used to directly read out the filter brought low at least 15 ns prior to the CNV edge and then released
results, this indicator can alert the user when each new filtered at least 5 ns before the next rising edge. The first ADC result
conversion result is available to read via the interface. is ready tMSB after the second CNV rising edge. This first ADC
result is latched into the filter on the third CNV rising edge. The
Filter Interface Timing Considerations fourth CNV rising edge latches the second ADC result into the
Continuous access to filtered data results is available only through digital filter. On the fifth rising edge, the first decimate by 2 result
the LVDS data interface. SPI data interface access to filtered is complete, which is indicated by the FILTER_READY signal going
results is only made via the FIFO. The timing considerations, in this active on the fifth rising edge. This first filtered result is loaded into
case, are described in the Filter Interface Timing Considerations the FIFO on the sixth CNV rising edge. Because this example uses
when Using the FIFO section. For use with the LVDS data interface, WATERMARK = 3, when three filtered (that is, six core ADC results,
it is recommended to use a GPIO, configured with the appropriate decimated by 2) results are loaded to the FIFO, the WATERMARK
GPIO_x_SEL (0011) to output the filter result ready (active low) is reached, and FIFO_FULL is asserted to indicate to the user that
signal, as is shown in the example Figure 95 timing diagram. a FIFO record is available to read via the configured data interface
(that is, the LVDS data lane(s) of the SPI data lane(s)). To initiate a
Filter Interface Timing Considerations when subsequent FIFO record acquisition of the filtered ADC results, the
Using the FIFO user must start the whole sequence over, beginning again with the
reset of the digital filter by bringing the FILTER_SYNC signal low on
Figure 97 serves as an example to illustrate the sequence of events the first rising edge of CNV.
in this mode of operation. This example illustrates a sinc1 filter with

Figure 97. Description of Filter Timing with FIFO

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Data Sheet AD4080
DIGITAL FEATURES

Digital Filter Conversion Pulses Digital Filter Response

The total number of CNV pulses required for a single filter deci- Sinc1 Filter
mated result (sinc1 settling clocks) can be calculated using the
following formula:
Settling CNV PulsesSINC1 = 2 + D + 1
Note that each of the three filter types has a unique formula to
determine the number of clocks required.
For the sinc5 settling clocks, the equation is as follows:
Settling CNV PulsesSINC5 = 2 + 5 × D + 4
For the sinc5 with compensation settling clocks, the equation is as
follows:
Settling CNV PulsesSINC5 + COMP =
2 + 35×D+10
Where D equals the decimation rate 2, 4, 8 … Figure 98. Sinc1 Filter Response, Decimate by 2

Digital Filtering Settling Time

The settling time for the selected filter is the number of settling
clocks times tCONV, as follows:
Filter Settling Time =
(Settling CNV PulsesFILTERTYPE × tCONV

Digital Filtering Settling Time when Using FIFO

When using the FIFO with filtered data, it is important to note
that each new FIFO record of results must begin by issuing a
FILTER_SYNC signal on the first CNV to reset and initialize the
filter and to prevent unflushed data from being contained in the first
FIFO record result.
Figure 99. Sinc1 Filter Response, Decimate by 4
The minimum total number of conversion pulses required to fill a full
FIFO record can be calculated as follows:
Total Required CNVs = D×WATERMARK +
Settling CNV PulsesFILTERTYPE
Where D equals the decimation rate 2, 4, 8 …

Figure 100. Sinc1 Filter Response, Decimate by 8

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Data Sheet AD4080
DIGITAL FEATURES

Figure 101. Sinc1 Filter Response, All Decimation Rates Figure 104. Sinc5 + Compensation Filter Response, Decimate by 2, Pass-
Band Ripple
Sinc5 Filter

Figure 105. Sinc5 + Compensation Filter Response

Figure 102. Sinc5 Filter Response, All Decimation Rates

Filter Sinc5 + Compensation Filter

Figure 103. Sinc5 + Compensation Filter Response, Decimate by 2

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Data Sheet AD4080
DIGITAL FEATURES

SYSTEM ERROR CORRECTION Gain Error Correction

COEFFICIENTS
The AD4080 is a high precision ADC with factory calibrated, gain
Systematic gain and offset errors exist in all practical data acquis- error correction. To allow a user to correct for any signal chain
ition circuits, and thus, the need for correction is essential to gain error within their application, the GAIN register (see the Gain
maximize the precision of the measurement channel. While these Correction Register, Address 0x27 and Address 0x28) can be used.
quantities can be corrected for in the host processor, implementa- The GAIN bit field is a 10-bit value that allows a nominal gain error
tion can be inefficient and consume more power than if integrated correction of ±1.5594% of full scale. The 10-bit register is coded in
within the data converter. To minimize these challenges for the end a straight binary data format, where the default value after power
user, the AD4080 has integrated both gain and offset correction on on, or software reset, is 0x200. This value represents no gain error
a per sample basis. correction being applied to the ADC results.
To describe the available error corrections, consider that the trans- With the GAIN register first set to the default 0x200 value, the user
fer function of an ideal ADC can be described by the straight line can perform a two-point voltage measurement, preferably close
equation. to positive and negative full-scale inputs, and use the slope or
gain equation in the System Error Correction Coefficients section
y = mx + c (2) to determine their system gain error. This system error can then
This equation can be applied to the ADC transfer function where: be adjusted with a resolution of 1.5594%/512 = 0.00305%. The
y is the corrected ADC result. required correction calculated can be input to the GAIN register.
m is the gain or slope of the line.
x is the uncorrected ADC result.
c is the offset.
The gain or slop of the line can be described as follows:
m = (y2 − y1)/(x2 − x1)
where the following are in volts:
y2 is the input voltage at close to the positive full-scale input.
y1 is the input voltage at close to the negative full-scale input.
x2 is the converted voltage with the y2 voltage applied at the input.
x1 is the converted voltage with the y1 voltage applied at the input.
The ideal slope or gain is m = 1 V/V
The system error correction coefficients in the Offset Error Correc-
tion and Gain Error Correction sections detail how signal chain
errors in offset (c) and gain (m) can be corrected using the configu-
ration registers of the AD4080.

Offset Error Correction

The AD4080 is factory calibrated to give low zero error. To account
for system offset errors that may be present in a users application
signal chain, an offset error correction function was included, which
allows users to correct for system offsets in their application by
applying a code to the OFFSET bit field in the offset Register at
Address 0x24 and Address 0x25, Bits[11:0]. This bit field is a 12-bit
value in a twos compliment data format.
The bit field is a 12-bit value in a twos compliment data format and
OFFSET LSB represents the value of the ADC LSB as defined in
the Transfer Function section. The range of offset error correction is
therefore defined as −2048 × LSB (0x800) to +2047 × LSB (0x7FF).
This represents a voltage range of ±11.71 mV for the specified
VREFIN = 3.0 V. The default value for this register, after power on,
or after a software reset, is 0x000, which represents the zero offset
correction applied.

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Data Sheet AD4080
LAYOUT GUIDELINES

The AD4080 includes all critical bypass capacitors within the device from the left-hand side and keeping dynamic digital signals on
package, which greatly reduces the layout challenge for a precision, the right-hand side.
high-speed converter. These integrated capacitors are optimally ► Have a solid ground plane under the AD4080 and connect all
placed within the device package to ensure that maximum perform- analog ground (GND) pins, reference ground (REFGND), and
ance is easily obtained. However, as with any precision mixed digital ground (IOGND) pins to this shared plane.
signal device, care must be taken in system device placement ► Recommended connections of ground (GND), reference ground
to ensure that there is proper partitioning of the critical analog (REFGND), and digital ground (IOGND) connections are shown
signal chain component routing and routing of the high-speed digital in Figure 106. It is recommended to not keep the current return
signals to prevent unwanted coupling effects. path of the reference IC in the same current loop as the current
Note the following layout considerations: return loop from the other circuitry on the PCB. Connect the
reference local star point to the ADC star point ground on the top
► The AD4080 contains internal decoupling on all power supplies, layer of the PCB as shown in Figure 106.
AVDD33 (0.47 μF), VDD11 (1.88 μF), VIO11 (0.22 μF), as well ► See Figure 107 for the side view cross-section of the PCB board
as VDDLDO (0.22 μF). Therefore, no external bypass capacitors showing the ground planes distribution . Note that Figure 107
are required, saving board space and reducing bill of material only shows the ground planes but does not including the signal
(BOM) count and sensitivity. tracks.
► Ensure good partitioning of analog and digital domain signals
within the design by, for example, having all analog signals in

Figure 106. AD4080 External Reference Ground Connections

Figure 107. Recommended PCB Ground Planes Layout

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Data Sheet AD4080
CONFIGURATION REGISTERS

The features of the AD4080 family have been designed to simplify data. For most applications, modifications to the register space
the application of low latency data capture to a broad array of address range of Address 0x15 to Address 0x29 are sufficient.
measurement applications. This simplification is achieved through Modification of content in the configuration interface and product ID
customization of the data interface, data path, and data access space (Address 0x00 to Address 0x11) is only necessary to initiate
method to satisfy both measurement and the host processor inter- a software reset or to change the configuration access method.
face requirements via the available configuration registers. Note that changes to the configuration access method are outside
the scope of this document. For assistance with these options,
The register space was organized in contiguous regions by function contact your local Analog Devices sales representative or submit
to streamline device configuration as described in Table 30. As a request for technical assistance through the Precision ADCs
a result, the interface streaming functions (see Instruction Mode page on the ADI Engineer Zone at https://ez.analog.com/data_con-
Selection) can be leveraged to simplify device configuration to a verters/precision_adcs/.
single SPI frame consisting of an instruction word and associated
Table 30. Register Map Organization
Address Range Function
0x00 to 0x11 Configuration interface and Product ID
0x14 Device status
0x15 to 0x17 Interface configuration
0x18 to 0x1B Power and GPIO configuration
0x1C General configuration
0x1C to 0x1E FIFO configuration
0x1F to 0x24 Internal event detection
0x25 to 0x28 System error correction
0x29 Digital filter configuration

Table 31. Configuration Register Summary—Configuration Interface Functions (Address 0x00 to Address 0x11)
Addr Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W
0x00 INTERFACE_ [7:0] SW_ RE- ADDR_ SDO_ RESERVED SW_ 0x10 R/W
CONFIG_A RESET SERVED ASCENSION ENABLE RESETX
0x01 INTERFACE_ [7:0] SINGLE_ RESERVED SHORT_ RESERVED 0x00 R/W
CONFIG_B INST INSTRUC-
TION
0x02 DEVICE_ [7:0] RESERVED OPERATING_MODES 0x00 R/W
CONFIG
0x03 CHIP_TYPE [7:0] RESERVED CHIP_TYPE 0x07 R
0x04 PRODUCT_ [7:0] PRODUCT_ID[7:0] 0x00 R
ID_L
0x05 PRODUCT_ [7:0] PRODUCT_ID[15:8] 0x00 R
ID_H
0x06 CHIP_GRADE [7:0] GRADE DEVICE_REVISION 0x02 R
0x0A SCRATCH_ [7:0] SCRATCH_VALUE 0x00 R/W
PAD
0x0B SPI_ [7:0] SPI_TYPE VERSION 0x83 R
REVISION
0x0C VENDOR_L [7:0] VID[7:0] 0x56 R
0x0D VENDOR_H [7:0] VID[15:8] 0x04 R
0x0E STREAM_ [7:0] LOOP_COUNT 0x00 R/W
MODE
0x0F TRANSFER_ [7:0] RESERVED KEEP_ RESERVED 0x00 R/W
CONFIG STREAM_
LENGTH_VAL
0x10 INTERFACE_ [7:0] CRC_ENABLE STRICT_ SEND_ ACTIVE_INTERFACE_MODE CRC_ENABLEB 0x23 R/W
CONFIG_C REGISTER_ STATUS

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Data Sheet AD4080
CONFIGURATION REGISTERS

Table 31. Configuration Register Summary—Configuration Interface Functions (Address 0x00 to Address 0x11) (Continued)
Addr Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W
ACCESS
0x11 INTERFACE_ [7:0] NOT_ RESERVED CLOCK_ CRC_ERR WR_TO_RD_ REGISTER_ ADD- 0x00 R/W
STATUS_A READY_ COUNT_ ONLY_REG_ PARTIAL_ RESS_
ERR ERR ERR ACCESS_ERR INVALID_
ERR
0x14 DEVICE_ [7:0] FIFO_ FIFO_ HI_STATUS LO_STATUS POR_ANA_ ADC_ ROM_CRC_ERR 0x09 R/W
STATUS FULL READ_ FLAG CNV_ERR POR_
DONE FLAG
0x15 ADC_DATA_ [7:0] RE- RE- RESERVED INTF_ RESERVED SPI_LVDS_ RESERVED DATA_ 0x40 R/W
INTF_ SERVED SERVED CHK_EN LANES INTF_
CONFIG_A MODE
0x16 ADC_DATA_ [7:0] LVDS_CNV_CLK_CNT LVDS_ LVDS_ RESERVED 0x00 R/W
INTF_ SELF_CLK_ MNC_EN LVDS_
CONFIG_B MODE CNV_EN
0x17 ADC_DATA_ [7:0] LVDS_RX_ LVDS_VOD RESERVED 0x20 R/W
INTF_ CURRENT
CONFIG_C
0x18 PWR_CTRL [7:0] RESERVED ANA_DIG_ INTF_ 0x00 R/W
LDO_PD LDO_
PD
0x19 GPIO_ [7:0] GPIO_3_ GPIO_2_ GPIO_1_ GPIO_0_ GPO_3_EN GPO_2_EN GPO_1_EN GPO_0_ 0x01 R/W
CONFIG_A DATA DATA DATA DATA EN
0x1A GPIO_ [7:0] GPIO_1_SEL GPIO_0_SEL 0x00 R/W
CONFIG_B
0x1B GPIO_ [7:0] GPIO_3_SEL GPIO_2_SEL 0x00 R/W
CONFIG_C
0x1C GENERAL_ [7:0] INT_ HI_ LO_ROUTE ADC_CNV_ RESERVED FIFO_MODE 0x00 R/W
CONFIG EVENT_ ROUTE ERR_
EN ROUTE
0x1D FIFO_ [7:0] FIFO_WATERMARK[7:0] 0x00 R/W
0x1E WATERMARK [15:8] RE- FIFO_WATERMARK[14:8] 0x40 R/W
SERVED
0x1F EVENT_ [7:0] HYSTERESIS[7:0] 0x00 R/W
0x20 HYSTERESIS [15:8] RESERVED HYSTERESIS[10:8] 0x00 R/W
0x21 EVENT_ [7:0] HI_THRESHOLD[7:0] 0x00 R/W
0x22 DETECTION_ [15:8] RESERVED HI_THRESHOLD[11:8] 0x00 R/W
HI
0x23 EVENT_ [7:0] LO_THRESHOLD[7:0] 0x00 R/W
0x24 DETECTION_ [15:8] RESERVED LO_THRESHOLD[11:8] 0x00 R/W
LO
0x25 OFFSET [7:0] OFFSET[7:0] 0x00 R/W
0x26 [15:8] RESERVED OFFSET[11:8] 0x00 R/W
0x27 GAIN [7:0] GAIN[7:0] 0x00 R/W
0x28 [15:8] RESERVED GAIN[9:8] 0x02 R/W
0x29 FILTER_ [7:0] RE- SINC_DEC_RATE RESERVED FILTER_SEL 0x00 R/W
CONFIG SERVED

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Data Sheet AD4080
CONFIGURATION REGISTERS

REGISTER DETAILS

Interface Configuration A Register

Address: 0x00, Reset: 0x10, Name: INTERFACE_CONFIG_A

Figure 108. Interface Configuration A Settings

Table 32. Bit Descriptions for INTERFACE_CONFIG_A

Bits Bit Name Description Reset Access
7 SW_RESET First of the Two SW_RESET Bits. This bit appears in two locations in this register. Both locations must 0x0 R/W
be written to at the same time to trigger a software reset of the device. This action returns any previously
configured registers to their default settings, except for the ADDR_ASCENSION bit from the Interface
Configuration A Register, which keeps its previous value.
Only use this reset method once the ADC is in an idle state, where conversions are not being clocked, and
any existing conversions are completed.
6 RESERVED Reserved. Write 0 to this bit. 0x0 R
5 ADDR_ASCENSION Determines Sequential Addressing Behavior. 0x0 R/W
0: Address is decremented by one when streaming.
1: Address is Incremented by one when streaming.
4 SDO_ENABLE SDO Pin Enable. 0x1 R
[3:1] RESERVED Reserved. Write 000 to these bits. 0x0 R
0 SW_RESETX Second of the Two SW_RESET Bits. This bit appears in two locations in this register. Both locations must 0x0 R/W
be written to at the same time to trigger a software reset of the device. This action returns any previously
configured registers to their default settings, except for the ADDR_ASCENSION bitd from the Interface
Configuration A Register, which keeps its previous value.
Only use this reset method once the ADC is in an idle state, where conversions are not being clocked, and
any existing conversion are completed.

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Data Sheet AD4080
CONFIGURATION REGISTERS

Interface Configuration B Register

Address: 0x01, Reset: 0x00, Name: INTERFACE_CONFIG_B

Figure 109. Additional Interface Configuration B Settings

Table 33. Bit Descriptions for INTERFACE_CONFIG_B

Bits Bit Name Description Reset Access
7 SINGLE_INST Select Streaming or Single Instruction Mode. 0x0 R/W
0: Streaming mode is enabled. The address increments or decrements as successive data bytes are
received.
1: Single instruction mode is enabled.
[6:4] RESERVED Reserved. Write 0b000 to these bits. 0x0 R
3 SHORT_INSTRUCTION Set the Instruction Phase Address to 7 or 15 bits. 0x0 R/W
0: 15-Bit Addressing.
1: 7-Bit Addressing.
[2:0] RESERVED Reserved. Write 0b000 to these bits. 0x0 R

Device Configuration Register

Address: 0x02, Reset: 0x00, Name: DEVICE_CONFIG

Figure 110. Device Configuration Register

Table 34. Bit Descriptions for DEVICE_CONFIG

Bits Bit Name Description Reset Access
[7:2] RESERVED Reserved. Write 0b000000 to these bits. 0x0 R
[1:0] OPERATING_MODES Power Modes. 0x0 R/W
00: Normal Operating Mode.
10: Standby Operating Mode.
11: Sleep Mode.

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Data Sheet AD4080
CONFIGURATION REGISTERS

Chip Type Register

Address: 0x03, Reset: 0x07, Name: CHIP_TYPE
The chip type is used to identify the family of Analog Devices devices a given device belongs to. CHIP_TYPE must be used in conjunction with
the Product ID to uniquely identify a given product.

Figure 111. Chip Type Register

Table 35. Bit Descriptions for CHIP_TYPE

Bits Bit Name Description Reset Access
[7:4] RESERVED Reserved. 0x0 R
[3:0] CHIP_TYPE Precision ADC. 0x7 R

Product ID Low Register

Address: 0x04, Reset: 0x00, Name: PRODUCT_ID_L
This register is the low byte of the Product ID.

Figure 112. Product ID Low Register

Table 36. Bit Descriptions for PRODUCT_ID_L

Bits Bit Name Description Reset Access
[7:0] PRODUCT_ID[7:0] Product Identification. These bits are the device chip type/family. The PRODUCT_ID must be used in 0x1 R
conjunction with CHIP_TYPE to identify a product.

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Data Sheet AD4080
CONFIGURATION REGISTERS

Product ID High Register

Address: 0x05, Reset: 0x00, Name: PRODUCT_ID_H
This register is the high byte of the Product ID.

Figure 113. Product ID High Register

Table 37. Bit Descriptions for PRODUCT_ID_H

Bits Bit Name Description Reset Access
[7:0] PRODUCT_ID[15:8] Product Identification. These bits are the device chip type and family. The PRODUCT_ID must be used in 0x0 R
conjunction with CHIP_TYPE to identify a product.

Chip Grade Register

Address: 0x06, Reset: 0x02, Name: CHIP_GRADE
This register identifies product variations and device revisions.

Figure 114. Chip Grade Register

Table 38. Bit Descriptions for CHIP_GRADE

Bits Bit Name Description Reset Access
[7:4] GRADE Device Grade. These bits are the device performance grade. 0x0 R
[3:0] DEVICE_REVISION Device Revision. These bits are the device hardware revision. 0x2 R

Scratch Pad Register

Address: 0x0A, Reset: 0x00, Name: SCRATCH_PAD
This register can be used to test writes and reads.

Figure 115. Scratch Pad Register

Table 39. Bit Descriptions for SCRATCH_PAD

Bits Bit Name Description Reset Access
[7:0] SCRATCH_VALUE Software Scratchpad. Software can write to and read from this location without any device side effects. 0x0 R/W

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Data Sheet AD4080
CONFIGURATION REGISTERS

SPI Revision Register

Address: 0x0B, Reset: 0x83, Name: SPI_REVISION
This register indicates the SPI revision.

Figure 116. SPI Revision Register

Table 40. Bit Descriptions for SPI_REVISION

Bits Bit Name Description Reset Access
[7:6] SPI_TYPE SPI Type. These bits always read as 0x2. 0x2 R
[5:0] VERSION SPI Version. 0x3 R
11: Revision 1.1.

Vendor ID Low Register

Address: 0x0C, Reset: 0x56, Name: VENDOR_L
This register is the low byte of the Vendor ID.

Figure 117. Vendor ID Low Register

Table 41. Bit Descriptions for VENDOR_L

Bits Bit Name Description Reset Access
[7:0] VID[7:0] Analog Devices Vendor ID. 0x56 R

Vendor ID High Register

Address: 0x0D, Reset: 0x04, Name: VENDOR_H
This register is the high byte of the Vendor ID.

Figure 118. Vendor ID High Register

Table 42. Bit Descriptions for VENDOR_H

Bits Bit Name Description Reset Access
[7:0] VID[15:8] Analog Devices Vendor ID. 0x4 R

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Data Sheet AD4080
CONFIGURATION REGISTERS

Stream Mode Register

Address: 0x0E, Reset: 0x00, Name: STREAM_MODE
This mode is not supported.

Figure 119. Stream Mode Register

Table 43. Bit Descriptions for STREAM_MODE

Bits Bit Name Description Reset Access
[7:0] LOOP_COUNT Stream Mode Loop Counter. These bits set the data byte count before looping to the start address. When streaming 0x0 R/W
data, a nonzero value sets the number of data bytes written before the address loops back to the start address.
A maximum of 255 bytes can be written using this approach. A value of 0x00 disables the loop back so that
addressing wraps around at the upper and lower limits of the memory. After writing to this register, the loop value
applies only to the next SPI instruction and auto clears upon the end of that instruction.

Transfer Configuration Register

Address: 0x0F, Reset: 0x00, Name: TRANSFER_CONFIG
This register controls how data moves between the controller and the target registers.

Figure 120. Transfer Configuration Register

Table 44. Bit Descriptions for TRANSFER_CONFIG

Bits Bit Name Description Reset Access
[7:3] RESERVED Reserved. Write 0b00000 to these bits. 0x0 R
2 KEEP_STREAM_LENGTH_VAL Keep Stream Length. When set, the loop counter does not reset on the CS rising edge. 0x0 R/W
[1:0] RESERVED Reserved. Write 0b00 to these bits. 0x0 R

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Data Sheet AD4080
CONFIGURATION REGISTERS

Interface Configuration C Register

Address: 0x10, Reset: 0x23, Name: INTERFACE_CONFIG_C
This register contains additional interface configuration settings.

Figure 121. Interface Configuration C Register

Table 45. Bit Descriptions for INTERFACE_CONFIG_C

Bits Bit Name Description Reset Access
[7:6] CRC_ENABLE CRC Enable. These bits are written to enable or disable the use of CRC on the interface. The 0x0 R/W
CRC_ENABLE bits must also be written to with the inverted value of these bits for the CRC to be
enabled.
0: CRC Disabled.
1: CRC Enabled.
5 STRICT_REGISTER_ACCESS Multibyte Registers Must Be Read/Written in Full. When this mode is enabled, all bytes of a 0x1 R/W
multibyte register must be read/written in full.
0: Normal Mode. No access restrictions.
1: Strict Mode. Multibyte registers require all bytes accessed.
4 SEND_STATUS Enables Sending of Status in 4-Wire Mode. When set, status information is sent by the device on 0x0 R/W
SDO during the instruction phase. When clear, no status is sent during the instruction phase.
[3:2] ACTIVE_INTERFACE_MODE Configuration SPI Mode. These bits are the active mode the SPI operates in. 0x0 R
[1:0] CRC_ENABLE Inverted CRC Enable. These bits must be written to with the inverted value of the CRC_ENABLE. 0x3 R/W

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Data Sheet AD4080
CONFIGURATION REGISTERS

Interface Status A Register

Address: 0x11, Reset: 0x00, Name: INTERFACE_STATUS_A
Status bits are set to 1 to indicate an active condition. These bits can be cleared by writing a 1 to the corresponding bit location.

Figure 122. Interface Status A Register

Table 46. Bit Descriptions for INTERFACE_STATUS_A

Bits Bit Name Description Reset Access
7 NOT_READY_ERR Device Not Ready for Transaction. This bit is set if the user attempts to execute an SPI 0x0 R/W1C
transaction before the completion of digital initialization.
[6:5] RESERVED Reserved. Write 0b00 to these bits. 0x0 R
4 CLOCK_COUNT_ERR Clock Count Error. This bit is set when an incorrect number of clocks is detected in a 0x0 R/W1C
transaction.
3 CRC_ERR CRC Error. This bit is set when the SPI controller does not send a CRC or when the CRC 0x0 R/W1C
value calculated by the device does not match the value sent by the SPI controller.
2 WR_TO_RD_ONLY_REG_ERR Write to Read Only Register Error. This bit is set when the user attempts a write to a register 0x0 R/W1C
that is read only.
1 REGISTER_PARTIAL_ACCESS_ERR Register Partial Access Error. This bit is set when a fewer than expected number of bytes 0x0 R/W1C
are read from or written to in a multibyte register access. This bit is only valid when strict
register access is enabled.
0 ADDRESS_INVALID_ERR Invalid Address Error. This bit is set when the user tries to read from or write to a register 0x0 R/W1C
address outside of the allowed memory map space.

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Data Sheet AD4080
CONFIGURATION REGISTERS

Device Status Register

Address: 0x14, Reset: 0x09, Name: DEVICE_STATUS

Figure 123. Device Status Register

Table 47. Bit Descriptions for DEVICE_STATUS

Bits Bit Name Description Reset Access
7 FIFO_FULL FIFO Full Status Flag. 0x0 R
0: FIFO Not Full.
1: FIFO Full.
6 FIFO_READ_DONE FIFO Read Done Flag. 0x0 R
0: FIFO Read Not Done.
1: FIFO Read Done.
5 HI_STATUS High Threshold Detection Status Flag. Writing 1 to this bit clears it. 0x0 R/W1C
0: High Threshold Event Not Detected.
1: High Threshold Event Detected.
4 LO_STATUS Low Threshold Detection Status Flag. Writing 1 to this bit clears it. 0x0 R/W1C
0: Low Threshold Event Not Detected.
1: Low Threshold Event Detected.
3 POR_ANA_FLAG POR Analog Status. Allows user to detect when an analog POR event occurs. An analog POR is triggered at 0x1 R/W1C
power-up or when the 1.1 V logic supply or ADC reference drops to less than the 2.7 threshold values or when
the user issues a software reset. Writing 1 to this bit clears it.
0: Analog POR Flag Cleared.
1: Analog POR Event Detected.
2 ADC_CNV_ERR ADC Conversion Error Flag. Writing 1 to this bit clears it. 0x0 R/W1C
0: ADC Conversion Okay.
1: ADC Conversion Error. The user has breached the minimum tCONV specification, and the conversion results
are invalid. The user must ensure that the correct clock timing specifications are met.
1 ROM_CRC_ERR ROM CRC/ECC Failure Flag. 0x0 R
0: ROM CRC Check Okay.
1: ROM CRC/ECC Failure.
0 POR_FLAG POR Status. Allows user to detect when a POR event occurs. A POR is triggered at power-up or when the 1.1 0x1 R/W1C
V logic supply drops to less than the 0.93 V threshold value or when the user issues a software reset. Writing 1
to this bit clears it.
0: POR Flag Cleared.
1: POR Event Detected.

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Data Sheet AD4080
CONFIGURATION REGISTERS

ADC Data Interface Configuration A Register

Address: 0x15, Reset: 0x40, Name: ADC_DATA_INTF_CONFIG_A

Figure 124. ADC Data Interface Configuration A Register

Table 48. Bit Descriptions for ADC_DATA_INTF_CONFIG_A

Bits Bit Name Description Reset Access
7 RESERVED Reserved. Write 0b0 to this bit. 0x0 R
6 RESERVED Reserved. Always set this bit to 1. 0x1 R/W
5 RESERVED Reserved. Write 0b0 to this bit. 0x0 R
4 INTF_CHK_EN Output Fixed Test Pattern on ADC Data Interface (LVDS Only). ADC output is not available when this mode is 0x0 R/W
enabled. Fixed pattern = 20'b1010 1100 0101 1101 0110 (0xAC5D6).
0: Test Pattern Disabled.
1: Test Pattern Enabled.
3 RESERVED Reserved. Write 0b0 to this bit. 0x0 R
2 SPI_LVDS_LANES LVDS/SPI Lane Control. Determines the number of lanes that the ADC conversion data is clocked out on. 0x0 R/W
0: One Lane Active.
1: Multiple Lanes Active (Two for LVDS and Four for the SPI Data Interface).
1 RESERVED Reserved. Write 0b0 to this bit. 0x0 R
0 DATA_INTF_MODE Read Conversion Data Over SPI or LVDS. Acts as global LVDS enable, setting this bit to 1 powers down the 0x0 R/W
LVDS transmitters/receivers.
0: Data Read Back Over LVDS.
1: Data Read Back Over SPI Data Interface (DCS/DCLK). CLK+ is repurposed as the SPI data interface clock
(DCLK) for reading FIFO data, and CLK− is repurposed as the SPI chip select (DCS) for reading FIFO data.

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Data Sheet AD4080
CONFIGURATION REGISTERS

ADC Data Interface Configuration B Register

Address: 0x16, Reset: 0x00, Name: ADC_DATA_INTF_CONFIG_B

Figure 125. ADC Data Interface Configuration B Register

Table 49. Bit Descriptions for ADC_DATA_INTF_CONFIG_B

Bits Bit Name Description Reset Access
[7:4] LVDS_CNV_CLK_CNT LVDS Clock Data Capture. Determines the negative edge of the LVDS clock that the MSB of the 0x0 R/W
conversion result is available in during conversion mode. Refer to the ADC Result Latency and LVDS
Interface Alignment section of further information on setting this value.
3 LVDS_SELF_CLK_MODE Enable/Disable LVDS Self Clock Mode. 0x0 R/W
0: Echo Clock Mode Enabled. LVDS DCO transmitter is powered up.
1: Self Clock Mode Enabled. LVDS DCO transmitter is powered down .
2 LVDS_MNC_EN Enable LVDS Manchester Encoding. Manchester encoding is only applied for LVDS read during 0x0 R/W
conversion mode in dual lane mode. This mode only operates with FILTER_SEL = 0, digital filter
disabled.
0: Manchester Encoding Disabled.
1: Manchester Encoding Enabled.
1 RESERVED Reserved. Write 0b0 to this bit. 0x0 R
0 LVDS_CNV_EN Configure CNV in LVDS Mode. Only applicable when LVDS interface is selected. 0x0 R/W
0: CNV Pin Configured in CMOS Mode.
1: CNV Pin Configured in LVDS Mode.

ADC Data Interface Configuration C Register

Address: 0x17, Reset: 0x20, Name: ADC_DATA_INTF_CONFIG_C

Figure 126. ADC Data Interface Configuration C Register

Table 50. Bit Descriptions for ADC_DATA_INTF_CONFIG_C

Bits Bit Name Description Reset Access
7 LVDS_RX_CURRENT LVDS Receivers Current Mode. 1'b0 − 1× current. 1'b1 − 2x current. 0x0 R/W

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Data Sheet AD4080
CONFIGURATION REGISTERS

Table 50. Bit Descriptions for ADC_DATA_INTF_CONFIG_C (Continued)

Bits Bit Name Description Reset Access
[6:4] LVDS_VOD LVDS Differential Output Voltage. The valid entries are 0b001, 0b010, and 0b100 for the differential voltages 0x2 R/W
of ~185 mV, ~240 mV, and ~325 mV, respectively. Writing an invalid value resets the differential voltage to its
default setting of ~240 mV. However, user can read back the value written to these bits.
[3:0] RESERVED Reserved. Write 0b0000 to these bits. 0x0 R

Power Control Register

Address: 0x18, Reset: 0x00, Name: PWR_CTRL
It is not recommended to write to this register.

Figure 127. Power Control Register

Table 51. Bit Descriptions for PWR_CTRL

Bits Bit Name Description Reset Access
[7:2] RESERVED Reserved. Write 0b000000 to these bits. 0x0 R
1 ANA_DIG_LDO_PD VDD11 LDO Disable. Enable or disable the LDO that powers the VDD11 rail. It is not recommended to 0x0 R/W
write to this bit.
0: LDO Enabled.
1: LDO Disabled.
0 INTF_LDO_PD IOVDD LDO Disable. Enable or disable the LDO that powers the IOVDD rail. It is not recommended to 0x0 R/W
write to this bit.
0: LDO Enabled.
1: LDO Disabled.

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Data Sheet AD4080
CONFIGURATION REGISTERS

GPIO Configuration A Register

Address: 0x19, Reset: 0x01, Name: GPIO_CONFIG_A

Figure 128. GPIO Configuration A Register

Table 52. Bit Descriptions for GPIO_CONFIG_A

Bits Bit Name Description Reset Access
7 GPIO_3_DATA GPIO 3 Readback or Write Data. 0x0 R/W
0: Write 0 to GPIO 3.
1: Write 1 to GPIO 3.
6 GPIO_2_DATA GPIO 2 Readback or Write Data. 0x0 R/W
0: Write 0 to GPIO 2.
1: Write 1 to GPIO 2.
5 GPIO_1_DATA GPIO 1 Readback or Write Data. 0x0 R/W
0: Write 0 to GPIO 1.
1: Write 1 to GPIO 1.
4 GPIO_0_DATA GPIO 0 Readback or Write Data. 0x0 R/W
0: Write 0 to GPIO 0.
1: Write 1 to GPIO 0.
3 GPO_3_EN GPIO 3 Output Enable. 0x0 R/W
0: GPIO 3 Configured as an Input.
1: GPIO 3 Configured as an Output.
2 GPO_2_EN GPIO 2 Output Enable. 0x0 R/W
0: GPIO 2 Configured as an Input.
1: GPIO 2 Configured as an Output.
1 GPO_1_EN GPIO 1 Output Enable. 0x0 R/W
0: GPIO 1 Configured as an Input.
1: GPIO 1 Configured as an Output.
0 GPO_0_EN GPIO 0 Output Enable. 0x1 R/W
0: GPIO 0 Configured as an Input.
1: GPIO 0 Configured as an Output.

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Data Sheet AD4080
CONFIGURATION REGISTERS

GPIO Configuration B Register

Address: 0x1A, Reset: 0x00, Name: GPIO_CONFIG_B

Figure 129. GPIO Configuration B Register

Table 53. Bit Descriptions for GPIO_CONFIG_B

Bits Bit Name Description Reset Access
[7:4] GPIO_1_SEL GPIO 1 Write Select. 0x0 R/W
0000: Configuration SPI SDO Data.
0001: FIFO Full Flag.
0010: FIFO Read Done Flag.
0011: Filter Result Ready (Active Low).
0100: High Threshold Detect.
0101: Low Threshold Detect.
0110: Status Alert (Active Low).
0111: GPIO Data.
1000: Filter Synchronization Input (Active Low).
1001: External Event Trigger Input for FIFO.
1010: Do not use this setting.
[3:0] GPIO_0_SEL GPIO 0 Write Select. 0x0 R/W
0000: Configuration SPI SDO Data.
0001: FIFO Full Flag.
0010: FIFO Read Done Flag.
0011: Filter Result Ready (Active Low).
0100: High Threshold Detect.
0101: Low Threshold Detect.
0110: Status Alert (Active Low).
0111: GPIO Data.
1000: Filter Synchronization Input (Active Low).
1001: External Event Trigger Input for FIFO.
1010: Do not use this setting.

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Data Sheet AD4080
CONFIGURATION REGISTERS

GPIO Configuration C Register

Address: 0x1B, Reset: 0x00, Name: GPIO_CONFIG_C

Figure 130. GPIO Configuration C Register

Table 54. Bit Descriptions for GPIO_CONFIG_C

Bits Bit Name Description Reset Access
[7:4] GPIO_3_SEL GPIO 3 Write Select. 0x0 R/W
0000: Configuration SPI SDO Data.
0001: FIFO Full Flag.
0010: FIFO Read Done Flag.
0011: Filter Result Ready (Active Low).
0100: High Threshold Detect.
0101: Low Threshold Detect.
0110: Status Alert (Active Low).
0111: GPIO Data.
1000: Filter Synchronization Input (Active Low).
1001: External Event Trigger Input for FIFO.
1010: Do not use this setting.
[3:0] GPIO_2_SEL GPIO 2 Write Select. 0x0 R/W
0000: Configuration SPI SDO Data.
0001: FIFO Full Flag.
0010: FIFO Read Done Flag.
0011: Filter Result Ready (Active Low).
0100: High Threshold Detect.
0101: Low Threshold Detect.
0110: Status Alert (Active Low).
0111: GPIO Data.
1000: Filter Synchronization Input (Active Low).
1001: External Event Trigger Input for FIFO.
1010: Do not use this setting.

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Data Sheet AD4080
CONFIGURATION REGISTERS

General Configuration Register

Address: 0x1C, Reset: 0x00, Name: GENERAL_CONFIG

Figure 131. General Configuration Register

Table 55. Bit Descriptions for GENERAL_CONFIG

Bits Bit Name Description Reset Access
7 INT_EVENT_EN Internal Event Detection Enable. ADC result or filtered data is only used for internal event detection after 0x0 R/W
this bit is set to 1.
0: Internal event detection is disabled.
1: Internal event detection is enabled.
6 HI_ROUTE High Detection Route. Allows high detection status to be used for FIFO event detection, status register, 0x0 R/W
and alert function (via the GPIO).
0: Mask High Detection.
1: Route High Detection to Alert Pin, Status Register, and FIFO.
5 LO_ROUTE Low Detection Route. Allows low detection status to be used for FIFO event detection, status register, 0x0 R/W
and alert function (via the GPIO).
0: Mask Low Detection.
1: Route Low Detection to Alert Pin, Status Register, and FIFO.
4 ADC_CNV_ERR_ROUTE ADC Conversion Error Route. Allows ADC conversion error status to be routed to the status register and 0x0 R/W
alert function (via the GPIO).
0: Mask ADC Conversion Error.
1: Route ADC Conversion Error to Alert Pin and Status Register.
[3:2] RESERVED Reserved. Write 0b0 to these bits. 0x0 R
[1:0] FIFO_MODE Conversion Data FIFO Mode. 0x0 R/W
00: FIFO Disabled.
01: Immediate Trigger Mode.
10: Event Trigger Capture, Read Latest WATERMARK.
11: Event Trigger Capture Mode, Read All FIFO.

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Data Sheet AD4080
CONFIGURATION REGISTERS

FIFO Watermark Register

Address: 0x1D and Address: 0x1E, Reset: 0x4000, Name: FIFO_WATERMARK
In event trigger capture mode, read all FIFO, the FIFO event address can be read. Otherwise, it is the watermark value. If the user writes a
value <1, it is clipped at 1. If >16,384, clipped at 16,384.

Figure 132. FIFO Watermark Register

Table 56. Bit Descriptions for FIFO_WATERMARK

Bits Bit Name Description Reset Access
15 RESERVED Reserved. Write 0b0 to this bit. 0x0 R
[14:0] FIFO_WATERMARK Number of Conversion to Capture in FIFO. In event trigger capture mode, read all FIFO, this value must 0x4000 R/W
be set as a multiple of four only. In this mode, once a WATERMARK number of results have been written
to the FIFO, these bits contain the location in the FIFO where the event occurred.

Event Detection Hysteresis Configuration Register

Address: 0x20 and Address: 0x1F, Reset: 0x0000, Name: EVENT_HYSTERESIS

Figure 133. Event Detection Hysteresis Configuration Register

Table 57. Bit Descriptions for EVENT_HYSTERESIS

Bits Bit Name Description Reset Access
[15:11] RESERVED Reserved. Write 0b00000 to these bits. 0x0 R
[10:0] HYSTERESIS Hysteresis Value. Unsigned data format where LSB = 1.46484 mV. 0x000 represents 0 × LSB, and 0x7FF 0x0 R/W
represents 2047 × LSB.

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Data Sheet AD4080
CONFIGURATION REGISTERS

Event Detection High Threshold Configuration Register

Address: 0x21 and Address: 0x22, Reset: 0x0000, Name: EVENT_DETECTION_HI

Figure 134. Event Detection High Threshold Configuration Register

Table 58. Bit Descriptions for EVENT_DETECTION_HI

Bits Bit Name Description Reset Access
[15:12] RESERVED Reserved. Write 0b0000 to these bits. 0x0 R
[11:0] HI_THRESHOLD High Threshold Value. Twos complement data format where LSB = 1.46484 mV. 0x800 represents −2048 × 0x0 R/W
LSB, and 0x7FF represents +2047 × LSB.

Event Detection Low Threshold Configuration Register

Address: 0x23 and Address: 0x24, Reset: 0x0000, Name: EVENT_DETECTION_LO

Figure 135. Event Detection Low Threshold Configuration Register

Table 59. Bit Descriptions for EVENT_DETECTION_LO

Bits Bit Name Description Reset Access
[15:12] RESERVED Reserved. Write 0b0000 to these bits. 0x0 R
[11:0] LO_THRESHOLD Low Threshold Value. Twos complement data format where LSB = 1.46484 mV. 0x800 represents −2048 × 0x0 R/W
LSB, and 0x7FF represents +2047 × LSB.

Offset Correction Register

Address: 0x25 and Address: 0x26, Reset: 0x0000, Name: OFFSET

Figure 136. Offset Correction Register

Table 60. Bit Descriptions for OFFSET

Bits Bit Name Description Reset Access
[15:12] RESERVED Reserved. Write 0b0000 to this bit field. 0x0 R
[11:0] OFFSET Offset Correction Coefficient. Twos complement data format where LSB = 0.00572 mV. 0x800 represents −2048 × 0x0 R/W
LSB, and 0x7FF represents +2047 × LSB.

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Data Sheet AD4080
CONFIGURATION REGISTERS

Gain Correction Register

Address: 0x27 and Address: 0x28, Reset: 0x0200, Name: GAIN

Figure 137. Gain Correction Register

Table 61. Bit Descriptions for GAIN

Bits Bit Name Description Reset Access
[15:10] RESERVED Reserved. Write 0b000000 to these bits. 0x0 R
[9:0] GAIN Gain Correction Coefficient. . 0x200 R/W
GAIN = 0x3FF results in an overall system gain of 1.0 + 0.015594.
GAIN = 0x200 disables the gain correction function and allows for lower latency operation.
GAIN = 0x001 results in an overall system gain of 1.0 − 0.015594.

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Data Sheet AD4080
CONFIGURATION REGISTERS

Filter Configuration Register

Address: 0x29, Reset: 0x00, Name: FILTER_CONFIG

Figure 138. Filter Configuration Register

Table 62. Bit Descriptions for FILTER_CONFIG

Bits Bit Name Description Reset Access
7 RESERVED Reserved. Write 0b0 to this bit field. 0x0 R
[6:3] SINC_DEC_RATE Decimation Factor. These bits set the Sinc Decimation Factor N. The filter compensation block incurs an 0x0 R/W
additional 2× decimation. The total decimation for a selected filter is sinc1 = N, sinc5 = N, or sinc5 +
compensation = N × 2.
For a selected filter, setting invalid values, outside of those specified here, will set the filter at the maximum
decimation rate
0000: N = 2.
0001: N = 4.
0010: N = 8.
0011: N = 16.
0100: N = 32.
0101: N = 64.
0110: N = 128.
0111: N = 256.
1000: N = 512 (sinc1 only).
1001: N = 1024 (sinc1 only).
2 RESERVED Reserved. 0x0 R
[1:0] FILTER_SEL Filter Selection. To ensure the first filter result produces the correct data, when a user makes a change to the 0x0 R/W
filter selection, a reset must be issued via the GPIO pin configured for filter synchronization (FILTER_SYNC).
00: Filter Disabled.
01: Sinc1 Filter Selected.
10: Sinc5 Filter Selected.
11: Sinc5 + Compensation Filter Selected.

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Data Sheet AD4080
OUTLINE DIMENSIONS

Figure 139. 49-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-49-8)
Dimensions shown in millimeters

Updated: February 29, 2024

ORDERING GUIDE
Model1 Temperature Range Package Description Packing Quantity Package Option
AD4080BBCZ −40°C to +85°C CHIP SCALE BGA Tray, 640 BC-49-8
AD4080BBCZ-RL −40°C to +85°C CHIP SCALE BGA Reel, 4000 BC-49-8
AD4080BBCZ-RL7 −40°C to +85°C CHIP SCALE BGA Reel, 1000 BC-49-8
1 Z = RoHS Compliant Part.

EVALUATION BOARDS
Table 63. Evaluation Boards
Model1 Description
EVAL-AD4080-FMCZ FMC Evaluation Board
1 Z = RoHS-Compliant Part.

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