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Pass Transistor and Transmission Gate

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184 views11 pages

Pass Transistor and Transmission Gate

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manansakhiya3112
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Module 5

Combinational logic Circuits


Introduction, Static CMOS Design- Complex Logic Gates, Ratioed Logic, Pass-
Transistor Logic, Transmission gate Logic, Dynamic CMOS Logic Design:
Dynamic Logic Design Considerations. Speed and Power Dissipation of
Dynamic logic, Signal integrity issues, Cascading Dynamic gates.
Introduction
In this chapter, we examine alternative CMOS logic
configurations, called circuit families.

While the vast majority of designs synthesize exclusively onto


static CMOS libraries and even custom designs use static CMOS
for 95% of the logic, high speed, low power, or density
restrictions may force another solution.

You should design the circuit that satisfies the application and
requires the least design and verification effort.

The most commonly used alternative circuit families are


ratioed circuits, dynamic circuits, and pass- transistor circuits.
Pass transistor Logic
In the circuit families we have explored so far, inputs are applied
only to the gate terminals of transistors.

In pass-transistor circuits, inputs are also applied to the


source/drain diffusion terminals. These circuits build switches
using either nMOS pass transistors or parallel pairs of nMOS and
pMOS transistors called transmission gates.

Many authors have claimed substantial area, speed, and/or


power improvements for pass transistors compared to static
CMOS logic.

Full adders and other circuits rich in XORs also can be efficiently
constructed with transmission gates
AND gate using Pass transistor

The promise of this approach is that fewer transistors are required to


implement a given function. For example, the implementation of the AND
gate in Figure requires 4 transistors (including the inverter required to invert
B),while a complementary CMOS implementation would require 6 transistors.
The reduced number of devices has the additional advantage of lower
capacitance.

However, an NMOS device is effective at passing a 0 but is poor at pulling a


node to VDD. When the pass transistor pulls a node high, the output only
charges up to VDD -VTn. The situation is worsened by the fact that the devices
experience body effect, as there exists a significant source-to-body voltage
when pulling high.
The above example demonstrates that pass-transistor gates cannot be cascaded by
connecting the output of a pass gate to the gate input of another pass transistor.

This is illustrated in Figure, where the output of M1 (node x) drives the gate of another
MOS device. Node x can charge up to VDD -VTn1. If node C has a rail to rail swing, node Y
only charges up to the voltage on node x - VTn2 , which works out to VDD-VTn1-VTn2.

Figure on the other hand has the output of M1 (x) driving the junction of M2 , and there
is only one threshold drop. This is the proper way of cascading pass gates.
Unfortunately, differential pass-transistor logic, like
single-ended pass-transistor logic, suffers from static
power dissipation and reduced noise margins, since the
high input to the signal-restoring inverter only charges up
to VDD –VTn .

Solution 1: Level Restoration. A common solution to the


voltage drop problem is the use of a level restorer, which
is a single PMOS configured in a feedback path
Differential Pass Transistor Logic
For high performance design, a differential pass-transistor logic family, called CPL
or DPL, is commonly used.

These gates possess a number of interesting properties:


• Since the circuits are differential, complementary data inputs and outputs are always
available. Although generating the differential signals requires extra circuitry, the
differential style has the advantage that some complex gates such as XORs and adders
can be realized efficiently with a small number of transistors. Furthermore, the
availability of both polarities of every signal eliminates the need for extra inverters, as is
often the case in static CMOS or pseudo-NMOS.
• CPL belongs to the class of static gates, because the output-defining nodes are always
connected to either VDD or GND through a low resistance path. This is advantageous for
the noise resilience.
• The design is very modular. In effect, all gates use exactly the same topology. Only the
inputs are permutated. This makes the design of a library of gates very simple. More
complex gates can be built by cascading the standard pass-transistor modules.
Transmission Gate Logic

The most widely-used solution to deal with the voltage-drop problem is the use of
transmission gates. It builds on the complementary properties of NMOS and PMOS
transistors: NMOS devices pass a strong 0 but a weak 1, while PMOS transistors pass
a strong 1 but a weak 0.
The transmission gate combines the best of both device flavors by placing a NMOS
device in parallel with a PMOS device
The control signals to the transmission gate are complementary.

The transmission gate acts as a bidirectional switch controlled by the gate signal C.
When C =1, both MOSFETs are on, allowing the signal to pass through the gate. On
the other hand, C = 0 places both transistors in cutoff, creating an open circuit between
nodes A and B.

Though the transmission gate requires two


transistors and more control signals, it enables
rail-to-rail swing.
Transmission gates can be used to build some complex gates very efficiently.
Figure shows an example of a simple inverting two-input multiplexer.

4x1 Multiplexer:
Another example of the effective use of transmission gates is the popular XOR
circuit shown in Figure.

C= A’(A’B’+AB) + C’(AB’+A’B)
= A’B’+AB’C’+A’BC’
=B’(A’+C’)+A’BC’
=A’B’+B’C’+A’BC’
=A’(B’+BC’)+B’C’
=A’B’+A’C’ +B’C’

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