HOOGHLY ENGINEERING & TECHNOLOGY COLLEGE

Approved by AICTE || Recognized by UGC || Affiliated to MAKAUT

LAB MANUAL

Analog & Digital Electronics

Code: ESC-301

Department of Computer Science and Engineering

Campus: Vivekananda Road, Pipulpati, Hooghly, Pin No- 712103

Website: https://www.hetc.ac.in/

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 EXPERIMENT – 1

1.1. TITLE: Introduction (Familiarization with basic gates and universal gates).

1.2. APPARATUS REQUIRED:

a. Logic trainer kit.

b. Breadboard.
c. Single strand wires.
d. Transistor Transistor Logic (TTL) IC’s (AND (IC-7408), OR (IC-7432), NOT (IC-7404), NAND
(IC-7400), NOR (IC-7402), XOR (IC-7486) and XNOR (IC-74266)).

1.3. THEORY:

Logic gates are idealized or physical devices implementing a Boolean function, which it performs a
logical operation on one or more logical inputs and produce a single output. Depending on the context, the
term may refer to an ideal logic gate, one that has for instance zero rise time and unlimited fan out or it
may refer to anon-ideal physical device. The main hierarchy is as follows:

1.3.1. LOGIC GATES:

1.3.1.1. AND GATE: The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low level when any one of the
inputs is low. 7408 is the two Inputs AND gate IC. A & B are the Input terminals & Y is the Output
terminal. Its logical equation is, Y = A.B.

1.3.1.1.1. SYMBOL:

1.3.1.1.2. PIN DIAGRAM:

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1.3.1.1.3. TRUTH TABLE:

Input Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

1.3.1.2. OR GATE: The OR gate performs a logical addition commonly known as OR function. The
output is high when any one of the inputs is high. The output is low level when both the inputs are low.
7432 is the two Input OR gate IC. A & B is the input terminals & Y is the Output terminal. Its logical
equation is, Y = A + B.

1.3.1.2.1. SYMBOL:

1.3.1.2.2. PIN DIAGRAM:

1.3.1.2.3. TRUTH TABLE:

Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

1.3.1.3. NOT GATE: The NOT gate is called an inverter. The output is high when the input is low. The
output is low when the input is high. It has one input (A) & one output (Y). IC No. is 7404. Its logical
equation is, Y = A.

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1.3.1.3.1. SYMBOL:

1.3.1.3.2. PIN DIAGRAM:

1.3.1.3.3. TRUTH TABLE:

Input Output
A Y
0 1
1 0

1.3.1.4. NAND GATE: The NOT-AND operation is known as NAND operation. NAND gate is inverted
AND gate. The output is high when both inputs are low and any one of the input is low. The output is low
level when both inputs are high. The IC no. for NAND gate is 7400. Its logical equation is, Y = (A. B).

1.3.1.4.1. SYMBOL:

1.3.1.4.2. PIN DIAGRAM:

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1.3.1.4.3. TRUTH TABLE:

Input Output
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

1.3.1.5. NOR GATE: The NOT- OR operation is known as NOR operation. NOR gate is inverted OR
gate. The output is high when both inputs are low. The output is low when one or both inputs are high.
The IC no. for NOR gate is 7402. Its logical equation is, Y = (A + B).

1.3.1.5.1. SYMBOL:

1.3.1.5.2. PIN DIAGRAM:

1.3.1.5.3. TRUTH TABLE:

Input Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

1.3.1.6. XOR GATE: XOR gate is not a basic gate. XOR operation can be performed using basic gates.
Output of XOR gate is high when any one of the inputs is high. The output is low when both the inputs
are low and both the inputs are high. The IC no. for XOR gate is 7486. Its logical equation is, Y= A⊕B.

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1.3.1.6.1. SYMBOL:

1.3.1.6.2. PIN DIAGRAM:

1.3.1.6.3. TRUTH TABLE:

Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

1.3.1.7. XNOR GATE: XNOR operation can also be performed using basic gates. Output of XNOR gate
is high when both the inputs are low and both the inputs are high. The output is low when any one of the
inputs is high. The IC no. for XNOR gate is 74266. Its logical equation is, Y=A⊙B.

1.3.1.7.1. SYMBOL:

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1.3.1.7.2. PIN DIAGRAM:

1.3.1.7.3. TRUTH TABLE:

Input Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 1

1.3.1.8. ADVANTAGES OF TTL GATES:

a. TTL family is the fastest saturating logic family (working in between the saturation and cut-off
modes). Also, TTL gates are available in a variety of forms, such as high-speed TTL, high-speed
Schottky TTL, low-power TTL etc.
b. Typical supply voltage is only +5 V with a permitted variation of ±0.25 V. At present, TTL gates of
3-volt and even to 1.5-volt supply are possible.
c. It has good noise immunity. Typical noise-margin is about 0.4 V.
d. Power dissipation is in the range of several mW only. In the case of low-power Schottky TTL gates,
this is less than 2 mW per gate.
e. TTL gates are compatible with other logic families.
f. Commercial and military versions of TTL gates are available.
g. These gates are more freely available in the open market than most other logic families.
h. Good fan-out; TTL gates can drive up to 10 gates.
i. TTL gates producing almost all of the logic functions are available in the market.
j. TTL gates exhibit low output impedance for high/low states.

1.3.1.9. DISADVANTAGES OF TTL GATES:

a. Noise immunity is not very high; so TTL gates cannot be used in applications where large noise
voltages exist.
b. Because of isolation problems, which require more chip space, TTL VLSI circuits are not possible in
its conventional form.
c. Power dissipation of TTL gates is much higher than that of MOS gates.
d. Cost of TTL gates is higher than that of NMOS/CMOS gates, when MSI and LSI gates are
considered.

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e. TTL gates generate transient voltages at switching instants.
f. Wired-OR capability is not possible for the conventional TTL gates; open-collector gates are required
for this application.
1.3.1.10. APPLICATIONS OF TTL GATES: Before the advent of VLSI devices, TTL integrated
circuits were a standard method of construction for the processors of minicomputer and
midrange mainframe computers, such as the DEC VAX and Data General Eclipse; however some
computer families were based on proprietary components (e.g. Fairchild CTL) while supercomputers and
high-end mainframes used Emitter-coupled logic. They were also used for equipment such as machine
tool numerical controls, printers and video display terminals, and as microprocessors became more
functional for "glue logic" applications, such as address decoders and bus drivers, which tie together the
function blocks realized in VLSI elements. The Gigatron TTL is a more recent (2018) example of a
processor built entirely with TTL integrated circuits.
1.3.2. BREADBOARD: The breadboard is organized into rows (1, 2, 3, 4,…) and columns (A, B, C,
D,…J) of electrical sockets. The figure below depicts the photograph of a breadboard. Those rows and
columns can be further subdivided into groups. The breadboards that are provided with the logic trainer
have pairs of columns with + and – labels (usually between red and blue lines). These are power rails or
buses that are used to supply a common voltage (+5V or +12V) and a common ground to the circuits in
the main part of the board. Good bus management will save you time and trouble with complicated
circuits by simplifying circuit wiring and by removing unnecessary clutter. Clutter is your enemy in
building circuits. Between the power rails are groups of sockets that will be used to build the circuit and,
within these groups of sockets, only the rows of sockets are electrically connected. The two groups across
the central gap are not connected.
To prevent damage to the breadboard sockets, use 22-gauge solid wire to make connections. Cut the wires
to the correct length or use the pre-cut wires. If needed strip about 1/2” of insulation from each end and
push the bare wires into the breadboard sockets until they bottom out. Forcing wires or component leads
into the board will damage the internal socket connections or make for an intermittent connection. If wires
or component leads do not fit easily into the breadboard, they may be too thick for the breadboard sockets.
To keep the circuit organized and easier to troubleshoot use colored wires to make your wiring easier to
follow and locate signals. For example, red wires for power connections, black or green wires for ground
connections, and other colored wires for signals. Use the shortest wire possible to make the electrical
connection.

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1.3.2.1. ADVANTAGES OF DESIGNING WITH BREADBOARDS:

a. It is adjustable.
b. It acts as a shield.
c. It is flexible.
d. Makes it easy for testing.
1.3.2.2. DISADVANTAGES OF DESIGNING WITH BREADBOARDS:

a. Not suitable for designing circuits with high voltage.

b. Not good for high current applications.
c. High Resistance.
1.3.2.3. APPLICATIONS OF BREADBOARD: A breadboard is a construction base used to build semi-
permanent prototypes of electronic circuits. Unlike a perfboard or stripboard, breadboards do not
require soldering or destruction of tracks and are hence reusable. For this reason, breadboards are also
popular with students and in technological education. A variety of electronic systems may be prototyped
by using breadboards, from small analog and digital circuits to complete central processing units (CPUs).

1.4. PROCEDURE:
I. Place the breadboard gently on the observation table.
II. Fix the IC which is under observation between the half shadow line of breadboard, so there is no
shortage of voltage.
III. Connect the wire to the main voltage source (Vcc) whose other end is connected to last pin of the IC
(14 place from the notch).
IV. Connect the ground of IC (7th place from the notch) to the ground terminal provided on the digital
lab kit.
V. Give the input at any one of the gate of the ICs i.e. 1st, 2nd, 3rd, 4th gate by using connecting wires.
(In accordance to IC provided).
VI. Connect output pins to the led on digital lab kit.
VII. Switch on the power supply.
VIII. If LED glows red then output is true, if it glows green output is false, which is numerically
denoted as 1 and 0 respectively.

1.5. OBSERVATION TABLE:

1.5.1. TRUTH TABLE OF AND GATE:

Input Output
A B Y

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1.5.2. TRUTH TABLE OF OR GATE:

Input Output
A B Y

1.5.3. TRUTH TABLE OF NOT GATE:

Input Output
A Y

1.5.4. TRUTH TABLE OF NAND GATE:

Input Output
A B Y

1.5.5. TRUTH TABLE OF NOR GATE:

Input Output
A B Y

1.5.6. TRUTH TABLE OF XOR GATE:

Input Output
A B Y

1.5.7. TRUTH TABLE OF XNOR GATE:

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 Input Output
A B Y

1.6. RESULT:
Thus the logic gates are studied and their truth tables were verified.

1.7. PRECAUTIONS:

• All connections should be made neat and tight.

• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.

1.8. CONCLUSION:

1.9. VIVA QUESTIONS:

Q1. what is logic gate?

Q2. what do you mean by universal gate?
Q3. what is truth table?
Q4. Make truth table of NAND gate?
Q5. what is different between XOR & XNOR gate?
Q6. Draw the NAND gate?
Q7. Draw the XOR gate?
Q8. Draw the XOR gate by using the NAND gate?
Q9. Draw the XNOR gate?
Q10. Draw the XNOR by using the NAND gate?

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 EXPERIMENT – 2

2.1. TITLE: Design a Full Adder using basic gates and verify its output / Design a Full Subtractor circuit
using basic gates and verify its output.

2.2. APPARATUS REQUIRED:

a. Logic trainer kit.

b. NAND gates (IC 7400).
c. XOR gates (IC 7486).
d. AND gates (IC 7408).
e. NOT gates (IC 7404).
f. Connecting wires.

2.3. THEORY: A combinational logic circuit is a type of digital circuit that uses logic gates to implement
Boolean functions. The output of a combinational logic circuit only depends on the current combination
of inputs, regardless of the previous state.

2.3.1. HALF ADDER: An adder, or summer is a digital circuit that performs addition of numbers. The
half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C).

2.3.1.1. TRUTH TABLE FOR HALF ADDER:

Input Output
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

2.3.1.2. K-MAP FOR SUM AND CARRY FOR HALF ADDER:

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2.3.1.3. HALF ADDER USING BASIC GATES:

2.3.1.4. ADVANTAGES OF HALF ADDER:

a. Simple design, the basic building block to understanding 1-bit addition.

b. Just with an inverter, it can be converted to the half subtractor.

2.3.1.5. DISADVANTAGES OF HALF ADDER:

a. Half adders have no scope of adding the carry bit resulting from the addition of previous bits.
b. The real-time scenarios involve adding the multiple numbers of bits which cannot be accomplished
using half adder.

2.3.1.6. APPLICATIONS OF HALF ADDER:

a. Half adder is used to realize full adder circuit.

b. Half adder is used in ALU (Arithmetic Logic Unit) of computer processors to add binary bits.
c. Half adder is used in calculators.

2.3.2. FULL ADDER: A full adder adds binary numbers and accounts for values carried in as well as out.
A one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands,
and Cin is a bit carried in from the previous less-significant stage. The circuit produces a two-bit output
such as sum (S) and carry (Cout).

2.3.2.1. TRUTH TABLE FOR FULL ADDER:

Input Output
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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2.3.2.2. K-MAP FOR SUM AND CARRY FOR FULL ADDER:

2.3.2.3. FULL ADDER USING BASIC GATES:

2.3.2.4. ADVANTAGES OF FULL ADDER:

a. Provides facility to add the carry from the previous stage.

b. Full adder can be easily converted into a half subtractor just by adding a NOT gate in the circuit.
c. Low power consumption.
d. High speed and robustness to supply voltage scaling, transistor sizing.

2.3.2.5. DISADVANTAGES OF FULL ADDER:

a. When used in a chain structure such as a ripple adder, the output drive capability is reduced.
2.3.2.6. APPLICATIONS OF FULL ADDER:
a. A Full Adder’s circuit can be used as a part of many other larger circuits like Ripple Carry Adder,
which adds n-bits simultaneously.
b. The dedicated multiplication circuit uses Full Adder’s circuit to perform Carryout Multiplication.
c. Full Adders are used in ALU- Arithmetic Logic Unit.

2.3.3. HALF SUBTRACTOR: A subtractor is a digital circuit that performs subtraction of numbers.
Subtractor can be designed using the same approach as that of an adder. The half subtractor is a

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combinational circuit which is used to perform subtraction of two bits. It has two inputs, the minuend X
and subtrahend Y and two outputs the difference (D) and borrow (B).

2.3.3.1. TRUTH TABLE FOR HALF SUBTRACTOR:

Input Output
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

2.3.3.2. K-MAP FOR DIFFERENCE AND BORROW FOR HALF SUBTRACTOR:

2.3.3.3. HALF SUBTRACTOR USING BASIC GATES:

2.3.3.4. ADVANTAGES OF HALF SUBTRACTOR:

a. The implementation and construction of this circuit is simple and easy.

b. This circuit consumes minimal power in digital signal processing.
c. Computational functionalities can be performed at improved speed rates.
2.3.3.5. DISADVANTAGES OF HALF SUBTRACTOR:
a. The half subtractor circuits will not accept “Borrow-in” from the previous outputs where this is the
crucial drawback of this circuit.
b. As many real-time applications operate on the subtraction of numerous number of bits, half
subtractors devices do not hold any capability of subtracting many bits.
2.3.3.6. APPLICATIONS OF HALF SUBTRACTOR:

a. Half subtractor is used to realize full subtractor circuit.

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b. Half subtractor is used in ALU (Arithmetic Logic Unit) of computer processors to add binary bits.

2.3.4. FULL SUBTRACTOR: The full subtractor is a combinational circuit which is used to perform
subtraction of three input bits: the minuend X, subtrahend Y, and borrow in Bin. The full subtractor
generates two output bits: the difference (D) and borrow (Bout). Bin is set when the previous digit is
borrowed from X.

2.3.4.1. TRUTH TABLE FOR FULL SUBTRACTOR:

Input Output
X Y Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

2.3.4.2. K-MAP FOR DIFFERENCE AND BORROW FOR FULL SUBTRACTOR:

2.3.4.3. FULL SUBTRACTOR USING BASIC GATES:

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2.3.4.4. ADVANTAGES OF FULL SUBTRACTOR:

a. The designing of subtractor is very simple as well as implement.

b. Computational tasks can be carried out at high speed.
2.3.4.5. DISADVANTAGES OF FULL SUBTRACTOR:
a. Speed of the subtractor is limited through the propagation delay in the circuit.

2.3.4.6. APPLICATIONS OF FULL SUBTRACTOR:

a. Full subtractors are used in ALU (Arithmetic Logic Unit) in computers CPUs.
b. Full subtractors are extensively used to perform arithmetical operations like subtraction in electronic
calculators and many other digital devices.
c. Full subtractors are used in different microcontrollers for arithmetic subtraction.
d. They are used in timers and program counters (PC).

2.4. PROCEDURE:

I. Connections are given as per the circuit diagram.

II. Logical inputs are given as per circuit diagram.
III. Observe the output and verify the truth table.

2.5. OBSERVATION TABLE:

2.5.1. TRUTH TABLE FOR FULL ADDER:

Input Output
A B Cin S Cout

2.5.2. TRUTH TABLE FOR FULL SUBTRACTOR:

Input Output
X Y Bin D Bout

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2.6. RESULT:

Thus full adder and full subtractor were designed and their truth tables were verified.

2.7. PRECAUTIONS:

• All connections should be made neat and tight.

• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.

2.8. CONCLUSION:

2.9. VIVA QUESTIONS:

Q1. what is use of half adder?

Q2. In Half adder how many inputs are used?
Q3. In output of Half adder what we gate?
Q4. In Half adder SUM=?
Q5. In half adder Carry=?
Q6. How many AND gate required to make a Half adder?
Q7. Draw the half adder diagram?
Q8. What is difference between the half and full adder?
Q9. What is use of Full adder?
Q10. In full adder how many inputs are used?
Q11. In output of full adder what we gate?
Q12. In full adder SUM=?
Q13. In full adder Carry=?
Q14. How many half adders required to make a full adder?
Q15. In full adder how many types of gates are required?
Q16. Draw the full adder diagram?
Q17. What is use of half Subtractor?
Q18. In Half Subtractor how many inputs are used?
Q19. In output of Half Subtractor what we gate?
Q20. In Half Subtractor Difference=?
Q21. How many AND gate required to make a Half Subtractor?
Q22. Draw the half subtractor diagram?
Q23. What is difference between full & half subtractor?

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Q24. What is difference between half adder and half subtractor?
Q25. If input of half subtractor is 11 then output is?
Q26. In Full Subtractor how many inputs are used?
Q27. In output of Full Subtractor what we gate?
Q28. In Full Subtractor Difference=?
Q29. How many NAND gate required to make a Full Subtractor?
Q30. In Full Subtractor how many Half Subtractor are required?
Q31. Draw the full subtractor diagram?

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 EXPERIMENT – 3

3.1. TITLE: Construction of simple Decoder & Multiplexer circuits using logic gates.

3.2. APPARATUS REQUIRED:

a. Logic trainer kit.

b. AND gates (IC-7408).
c. OR gates (IC-7432).
d. NOT gates (IC-7404).
e. Connecting wires.

3.3. THEORY: A combinational logic circuit is a type of digital circuit that uses logic gates to implement
Boolean functions. The output of a combinational logic circuit only depends on the current combination
of inputs, regardless of the previous state.

3.3.1. DECODER: A decoder is a combinational logic circuit that converts binary information from the n
coded inputs to a maximum of 2n unique outputs. They are utilized in a wide variety of applications,
including instruction decoding, data multiplexing and data demultiplexing, seven segment displays, and as
address decoders for memory and port-mapped input/output.

3.3.1.1. TRUTH TABLE FOR 2×4 DECODER:

Input Output
E A1 A0 Y3 Y2 Y1 Y0
0 × × 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

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3.3.1.2. K-MAP FOR OUTPUTS OF 2×4 DECODER:

3.3.1.3. 2×4 DECODER USING BASIC GATES:

3.3.1.4. ADVANTAGES OF DECODER:

a. Increased flexibility: Binary decoders provide a flexible way to select one of multiple outputs based
on a binary code, allowing for a wide range of applications.
b. Improved performance: By converting a serial code into a parallel set of outputs, binary decoders
can improve the performance of a digital system by reducing the amount of time required to transmit
information from a single input to multiple outputs.
c. Improved reliability: By reducing the number of lines required to transmit information from a single
input to multiple outputs, binary decoders can reduce the possibility of errors in the transmission of
information.

3.3.1.5. DISADVANTAGES OF DECODER:

a. Increased complexity: Binary decoders are typically more complex circuits compared to
demultiplexers, and require additional components to implement.
b. Limited to specific applications: Binary decoders are only suitable for applications where a serial
code must be converted into a parallel set of outputs.
c. Limited number of outputs: Binary decoders are limited in their number of outputs, as the number
of outputs is determined by the number of inputs and the binary code used.

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3.3.1.6. APPLICATIONS OF DECODER:

a. Converting digital signals into analogue signals, which are more suitable for human senses.
b. Inputting data to a specified output line, as in addressing core memory.
c. Code conversions.
d. Minimizing the effects of system decoding in high-performance memory systems.

3.3.2. MULTIPLEXER: A multiplexer (or mux), also known as a data selector, is a device that selects
between several analog or digital input signals and forwards the selected input to a single output line. The
selection is directed by a separate set of digital inputs known as select lines. A multiplexer of 2n inputs has
n select lines, which are used to select which input line to send to the output.

3.3.2.1. TRUTH TABLE FOR 4:1 MULTIPLEXER:

E Select Input Output

S1 S0 D3 D2 D1 D0 Y
0 × × × × × × 0
1 0 0 × × × 1 1
1 0 1 × × 1 × 1
1 1 0 × 1 × × 1
1 1 1 1 × × × 1

3.3.2.2. K-MAP FOR OUTPUT OF 4:1 MULTIPLEXER:

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3.3.2.3. 4:1 MULTIPLEXER USING BASIC GATES:

3.3.2.4. ADVANTAGES OF MULTIPLEXER:

a. Multiplexer makes the transmission circuit economical and less complex.

b. Analog switching current is low of order 10mA-20mA. Due to such a low magnitude of the current,
the heat dissipation is very low.
c. The ability of multiplexer to switch digital signals can be extended to switch to a video signal, audio
signals etc.

3.3.2.5. DISADVANTAGES OF MULTIPLEXER:

a. Additional delays required within switching ports & I/O signals which propagate throughout the
multiplexer.
b. The ports which can be utilized at the same time have limitations.
c. Multiplexers can introduce latency and delay in the transmission of data.
d. If the multiplexer is not configured or used correctly, it can also lead to data loss or errors.

3.3.2.6. APPLICATIONS OF MULTIPLEXER:

a. Communication System.
b. Computer Memory.
c. Computer System of a Satellite Transmission.
d. Telephone Network.

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3.4. PROCEDURE:

I. Assemble the circuit on bread board, as per above diagram.

II. Give the logical inputs and check for the proper output, as per the truth table.

3.5. OBSERVATION TABLE:

3.5.1. TRUTH TABLE FOR 2×4 DECODER:

Input Output
E A1 A0 Y3 Y2 Y1 Y0

3.5.2. TRUTH TABLE FOR 4:1 MULTIPLEXER:

E Select Input Output

S1 S0 D3 D2 D1 D0 Y

3.6. RESULT:

Thus, Decoder & Multiplexer circuits were designed and their truth tables were verified.

3.7. PRECAUTIONS:

• All connections should be made neat and tight.

• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.

3.8. CONCLUSION:

3.9. VIVA QUESTIONS:

Q1. What are combinational circuits?
Q2. What do you understand by decoder?
Q3. What is the main difference between devoder and demultiplexer?
Q4. What do you mean by multiplexing?

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Q5. What is digital multiplexer?
Q6. How many 4:1 multiplexer will be required to design 8:1 multiplexer?

25
 EXPERIMENT – 4

4.1. TITLE: Realization of S-R/ J-K / D flip flops using logic gates.

4.2. APPARATUS REQUIRED:

a. Logic trainer kit.

b. AND gates (IC-7408).
c. NOT gates (IC-7404).
d. NAND gates (IC-7400).
e. NOR gates (IC-7402).
f. Connecting wires.

4.3. THEORY: Sequential circuits are digital circuits that store and use the previous state information to
determine their next state. Unlike combinational circuits, which only depend on the current input values to
produce outputs, sequential circuits depend on both the current inputs and the previous state stored in
memory elements. Sequential circuits are commonly used in digital systems to implement state machines,
timers, counters, and memory elements. Block disgram of sequential circuit is represented below.

4.3.1. S-R FLIP FLOP: It is a sequential circuit with two inputs, one is S and other is R. S here stands
for Set and R here stands for Reset. Set basically indicates set the flip flop which means output 1 and reset
indicates resetting the flip flop which means output 0. Here clock pulse is supplied to operate this flop
flop, hence it is clocked flip flop.

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4.3.1.1. TRUTH TABLE FOR S-R FLIP FLOP:

S R Qn+1 State
0 0 Qn Hold
0 1 0 Reset
1 0 1 Set
1 1 × Invalid

4.3.1.2. CHARACTERISTIC TABLE OF S-R FLIP FLOP:

Qn S R Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 ×
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 ×

4.3.1.3. CHARACTERISTIC EQUATION OF S-R FLIP FLOP:

4.3.1.4. S-R FLIP FLOP USING LOGIC GATES:

4.3.1.4.1. S-R FLIP FLOP CONSTRUCTION USING 2 NOR + 2 AND GATES:

27
4.3.1.4.2. S-R FLIP FLOP CONSTRUCTION USING 4 NAND GATES:

4.3.1.5. ADVANTAGES OF S-R FLIP FLOP:

Sequential logic circuits, as opposed to combinational logic circuits, depend not only on the present inputs
but also on past inputs. They utilize memory elements like flip flops to remember past data. The S-R flip
flop is a primary example of a memory element in sequential logic circuits. By capturing and storing
binary values, S-R flip flops contribute significantly to the operation of sequential logic systems.

4.3.1.6. DISADVANTAGES OF S-R FLIP FLOP:

The primary limitation of S-R flip flop is the undefined or unpredictable state when both the Set and
Reset inputs are active (i.e., when both are 1). This condition is generally avoided in practical applications
as it can lead to an unstable output, disrupting the functionality of the circuit.
4.3.1.7. APPLICATIONS OF S-R FLIP FLOP:

SR Flip-flops serve a vital role in many different types of digital electronics systems. They are used
extensively in memory devices and data storage applications due to their ability to retain a binary state.
This is particularly important for computer systems, where reliable data storage and retrieval is critical.
Besides, they are also used in counters and shift registers, allowing for the storage and shifting of binary
data. In such applications, multiple flip-flops are connected in a chain, with the output of one flip-flop
connected to the input of the next.

4.3.2. J-K FLIP FLOP: A J-K flip-flop is a sequential bi-state single-bit memory device. In general it
has one clock input pin (CLK), two data input pins (J and K), and two output pins (Q and Q̅).

28
4.3.2.1. TRUTH TABLE FOR J-K FLIP FLOP:

J K Qn+1 State
0 0 Qn Hold
0 1 0 Reset
1 0 1 Set
1 1 Qn Toggle

4.3.2.2. CHARACTERISTIC TABLE OF J-K FLIP FLOP:

Qn S R Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

4.3.2.3. CHARACTERISTIC EQUATION OF J-K FLIP FLOP:

4.3.2.4. J-K FLIP FLOP USING LOGIC GATES:

4.3.2.4.1. J-K FLIP FLOP CONSTRUCTION USING 2 NOR + 2 AND GATES:

29
4.3.2.4.2. J-K FLIP FLOP CONSTRUCTION USING 4 NAND GATES:

4.3.2.5. ADVANTAGES OF J-K FLIP FLOP:

a. Versatility: Among the basic flip-flops, the J-K flip-flop is the most versatile.
b. Improved variation: It is an improved variation of the SR Flipflop.
c. Speed: The J-K flip flop is much faster than other flip-flops.
d. Toggle state: The J-K flip flop has a toggle state.
4.3.2.6. DISADVANTAGES OF J-K FLIP FLOP:
a. Complexity: The JK flip-flop is more complex than some other types of flip-flops, which can make it
more difficult to design and implement in digital systems.
b. Power consumption: The JK flip-flop can consume more power than other types of flip-flops,
especially when used in toggle mode.
c. Timing problem: The JK flip-flop has a timing problem known as “RACE”. The condition of RACE
arises if the output Q changes its state before the timing pulse of the clock input has time to go in
OFF state. This condition is not possible always thus a much-improved flip-flop named Master Salve
JK Flip Flop was developed. This eliminates all the timing problems by using two RS flip-flop
connected in series.
4.3.2.7. APPLICATIONS OF J-K FLIP FLOP:

a. Shift registers.
b. Storage registers.
c. Counters and control circuits.

30
4.3.3. D FLIP FLOP: D flip flop is an electronic devices that is known as “delay flip flop” or “data flip
flop” which is used to store single bit of data. The D flip flop has two inputs, data and clock input which
controls the flip flop. when clock input is high, the data is transferred to the output of the flip flop and
when the clock input is low, the output of the flip flop is held in its previous state.

4.3.3.1. TRUTH TABLE FOR D FLIP FLOP:

D Qn+1 State
0 0 Reset
1 1 Set

4.3.3.2. CHARACTERISTIC TABLE OF D FLIP FLOP:

Qn D Qn+1
0 0 0
0 1 1
1 0 0
1 1 1

4.3.3.3. CHARACTERISTIC EQUATION OF D FLIP FLOP:

31
4.3.3.4. D FLIP FLOP USING LOGIC GATES:

4.3.3.4.1. D FLIP FLOP CONSTRUCTION USING 2 NOR + 2 AND + 1 NOT GATES:

4.3.3.4.2. D FLIP FLOP CONSTRUCTION USING 4 NAND + 1 NOT GATES:

4.3.3.5. ADVANTAGES OF D FLIP FLOP:

a. D flip flop is very simple to design.

b. The computation speed of D flip flop is very fast compared to other flip flops.
c. D flip flop requires very few components to design which makes it simple to understand.
4.3.3.6. DISADVANTAGES OF D FLIP FLOP:
a. D flip flops are glitch prone. When input varies fast, flip flop output may glitch. Digital circuit
glitches are hard to identify and fix.
4.3.3.7. APPLICATIONS OF D FLIP FLOP:
a. Memory: D flip flop is used to create memory circuit for holding the data.
b. Registers: D flip flop is used to create register, which can hold data in digital system. By using the D
flip flop the designer can built any size of register as per the requirement.
c. Counters: D flip flops are used to create the counters which counts the number of event occurred in
the digital system.
d. Synchronous System: D flip flop is having in developing the synchronous system.

32
4.4. PROCEDURE:

I. Connections are given as per circuit diagram.

II. Logical inputs are given as per circuit diagram.
III. Observe the output and verify the truth table.

4.5. OBSERVATION TABLE:

4.5.1. TRUTH TABLE FOR S-R FLIP FLOP:

S R Qn+1 State

4.5.2. TRUTH TABLE FOR J-K FLIP FLOP:

J K Qn+1 State

4.5.3. TRUTH TABLE FOR D FLIP FLOP:

D Qn+1 State

4.6. RESULT:

Thus, S-R, J-K & D Flip flops were designed using logic gates and their truth tables were verified.

4.7. PRECAUTIONS:

• All connections should be made neat and tight.

• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.

4.8. CONCLUSION:

4.9. VIVA QUESTIONS:

Q1. What are sequential circuits?

Q2. Flip flop is astable or bistable?

33
Q3. What are the inputs of J-K Flip flop where this race around condition occurs?
Q4. When S-R Flip flop is said to be in a SET state?
Q5. When S-R Flip flop is said to be in a RESET state?
Q6. What is the truth table of J-K Flip flop?
Q7. What is the function of clock signal in Flip flop?
Q8. What is the advantage of J-K Flip flop over S-R Flip flop?
Q9. In D Flip flop input is 0 what is output?
Q10. What type of Flip flop you can use in memory?
Q11. What type of Flip flop you can use in counter circuit?

34
 EXPERIMENT – 5

5.1. TITLE: Design of Shift Register using J-K Flip Flop / D Flip Flop.

5.2. APPARATUS REQUIRED:

a. Logic trainer kit.

b. J-K Flip Flops (IC-7476).
c. D Flip Flops (IC-7474).
d. Connecting wires.

5.2.1. PIN DIAGRAM OF IC-7476 AND IC-7474:

5.3. THEORY: A shift register is a type of digital circuit using a cascade of flip-flops where the output of
one flip-flop is connected to the input of the next. They share a single clock signal, which causes the data
stored in the system to shift from one location to the next. Shift registers can have
both parallel and serial inputs and outputs. These are often configured as “Serial-in serial-out (SISO)”,
“Serial-in parallel-out (SIPO)” and “Parallel-in serial-out (PISO)”. There are also types that have both
serial and parallel input and types with serial and parallel output. There are also "bidirectional" shift
registers, which allow shifting in both directions: L → R or R → L. A PIPO register (parallel-in parallel-
out) is very fast – an output is given within a single clock pulse.

35
5.3.1. SERIAL-IN/SHIFT-RIGHT/SERIAL-OUT OPERATION: Data is shifted in the right hand
direction one bit at a time with each transition of the clock signal. The data enters the shift register serially
from the left hand side and after four clock transitions the 4-bit registers has 4-bits of data. The data is
shifted out serially one bit at a time from the right hand side of the register if clock signals are
continuously applied. Thus after 8 clock signals the 4-bit data is completely shifted out of the shift
register.

Serial shift registers can be implemented using any type of flip-flops such as J-K Flip Flop / D Flip Flop.
Serial shift register implemented using J-K Flip Flop and D flip-flops are represented below.

5.3.2. SERIAL-IN/SHIFT-RIGHT/SERIAL-OUT REGISTER USING J-K FLIP FLOP:

5.3.3. SERIAL-IN/SHIFT-RIGHT/SERIAL-OUT REGISTER USING D FLIP FLOP:

36
5.3.4. TIMING DIAGRAM OF A SERIAL-IN/SHIFT-RIGHT/SERIAL-OUT REGISTER:

5.3.5. SERIAL-IN/SHIFT-RIGHT/SERIAL-OUT REGISTER TRUTH TABLE:

Outputs �� �� �� ��
Reset 0 0 0 0
CLK pulse 1 1 0 0 0
CLK pulse 2 0 1 0 0
CLK pulse 3 0 0 1 0
CLK pulse 4 0 0 0 1

5.3.6. ADVANTAGES OF SHIFT REGISTER:

a. Storing and shifting large amounts of data in a small space.

b. Low power consumption.
c. High-speed operation.
d. Flexibility in data manipulation and conversion.
e. Use in a wide range of applications.
f. Very fast to use.
g. Very quick when you want to convert data from serial to parallel or vice versa.
h. Very simple in design.
5.3.7. DISADVANTAGES OF SHIFT REGISTER:
a. Speed of data loading and data reading operations is limited due to propagation delay in shift register.
5.3.8. APPLICATIONS OF SHIFT REGISTER:

a. Temporary data storage.

b. Serial adder and subtractor.
c. Multiplication and division operation.

37
d. Delay line.
e. Serial to parallel converter.
f. Parallel to serial converter.
g. Ring counter.
h. Twisted ring counter or Johnson counter.

5.4. PROCEDURE:
I. Connections are given as per circuit diagram.
II. Logical inputs are given as per circuit diagram.
III. Observe the output and verify the truth table.

5.5. OBSERVATION TABLE:

5.5.1. SERIAL-IN/SHIFT-RIGHT/SERIAL-OUT REGISTER TRUTH TABLE:

Outputs �� �� �� ��
Reset
CLK pulse 1
CLK pulse 2
CLK pulse 3
CLK pulse 4

5.6. RESULT:
Thus the Shift registers were designed and their truth table is verified.

5.7. PRECATIONS:
• All connections should be made neat and tight.
• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.

5.8. CONCLUSION:

5.9. VIVA QUESTIONS:

Q1. What do you mean by serial data?

Q2. What do you mean by parallel data?
Q3. What do you mean by serial data transfer?
Q4. What is a register?
Q5. What do you mean by the storage capacity of a register?
Q6. What do you mean by loading a register?
Q7. What are the types of loading the registers?
Q8. What is serial loading?

38
Q9. What is parallel loading?
Q10. What is the serial output?
Q11. What is the parallel output?
Q12. What are shift registers?
Q13. What is the basic difference between a shift register and a counter?
Q14. How will you use a shift register to multiply or divide a binary number by 2?
Q15. What is a universal shift register?

39
 EXPERIMENT – 6

6.1. TITLE: Realization of Synchronous Up/Down counter.

6.2. APPARATUS REQUIRED:

a. Logic trainer kit.

b. J-K Flip Flops (IC-7476).
c. Connecting wires.

6.3. THEORY:

6.3.1. SYNCHRONOUS COUNTER: Synchronous generally refers to something which is coordinated

with others based on time. In asynchronous Counter, the output of that counter is directly connected to the
input of next subsequent counter and making a chain system, and due to this chain system propagation
delay appears during counting stage and create counting delays. In synchronous counter, the clock input
across all the flip-flops use the same source and create the same clock signal at the same time. So, a
counter which is using the same clock signal from the same source at the same time is called Synchronous
counter.

6.3.2. SYNCHRONOUS UP COUNTER:

It can be seen above, that the external clock pulses (pulses to be counted) are fed directly to each of the J-
K flip-flops in the counter chain and that both the J and K inputs are all tied together in toggle mode, but
only in the first flip-flop, flip-flop FFA (LSB) are they connected HIGH, logic “1” allowing the flip-flop
to toggle on every clock pulse. Then the synchronous counter follows a predetermined sequence of states
in response to the common clock signal, advancing one state for each pulse.
The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-flop FFA, but
the J and K inputs of flip-flops FFC and FFD are driven from separate AND gates which are also supplied
with signals from the input and output of the previous stage. These additional AND gates generate the
required logic for the JK inputs of the next stage.
If we enable each JK flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q) are
“HIGH” we can obtain the same counting sequence as with the asynchronous circuit but without the
ripple effect, since each flip-flop in this circuit will be clocked at exactly the same time.

40
Then as there is no inherent propagation delay in synchronous counters, because all the counter stages are
triggered in parallel at the same time, the maximum operating frequency of this type of frequency counter
is much higher than that for a similar asynchronous counter circuit.

6.3.2.1. STATE DIAGRAM OF SYNCHRONOUS UP COUNTER:

6.3.2.2. SYNCHRONOUS UP COUNTER WAVEFORM TIMING DIAGRAM:

This synchronous counter counts sequentially on every clock pulse the resulting outputs count upwards
from 0 (0000) to 15 (1111). Therefore, this type of counter is also known as a 4-bit Synchronous Up
Counter.

41
6.3.2.3. TRUTH TABLE OF SYNCHRONOUS UP COUNTER:

CLK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

6.3.3. SYNCHRONOUS DOWN COUNTER: Synchronous down counter can easily be constructed by
connecting the AND gates to the Q output of the flip-flops (as shown below) to produce a waveform
timing diagram the reverse of the above. Here the counter starts with all of its outputs HIGH (1111) and it
counts down on the application of each clock pulse to zero, (0000) before repeating again.

42
6.3.3.1. STATE DIAGRAM OF SYNCHRONOUS DOWN COUNTER:

6.3.3.2. SYNCHRONOUS DOWN COUNTER WAVEFORM TIMING DIAGRAM:

43
6.3.3.3. TRUTH TABLE OF SYNCHRONOUS DOWN COUNTER:

CLK QD QC QB QA
0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0

6.3.4. ADVANTAGES OF SYNCHRONOUS COUNTER:

a. Easier to design and implement.

b. Faster operation and less propagation delay.
c. Less prone to errors and erroneous states.
d. More control over the count sequence using logic gates.

6.3.5. DISADVANTAGES OF SYNCHRONOUS COUNTER:

a. Synchronous counters can consume more power than asynchronous counters.

6.3.6. APPLICATIONS OF SYNCHRONOUS COUNTER:

a. Alarm Clock, Set AC Timer, Set time in camera to take the picture, flashing light indicator in
automobiles, car parking control etc.
b. Counting the time allotted for special process or event by the scheduler.
c. The UP/DOWN counter can be used as a self-reversing counter.
d. It is also used as clock divider circuit.

6.4. PROCEDURE:

I. Connections are given as per circuit diagram.

II. Logical inputs are given as per circuit diagram.
III. Observe the output and verify the truth table.

44
6.5. OBSERVATION TABLE:

6.5.1. TRUTH TABLE OF SYNCHRONOUS UP COUNTER:

CLK QD QC QB QA
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

6.5.2. TRUTH TABLE OF SYNCHRONOUS DOWN COUNTER:

CLK QD QC QB QA
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

45
6.6. RESULT:

Thus the Counters were designed and their truth table is verified.

6.7. PRECATIONS:

• All connections should be made neat and tight.

• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.

6.8. CONCLUSION:

6.9. VIVA QUESTIONS:

Q1. What are problems associated with ripple counters?

Q2. Define synchronous counter.
Q3. What are salient features of a synchronous counter?
Q4. Design a MOD-8 synchronous down counter with T Flip flop.
Q5. How is a counter different from a register?
Q6. Write the count sequence of three bit binary down counter.

46
 EXPERIMENT – 7

7.1. TITLE: Design of MOD- N Counter.

7.2. APPARATUS REQUIRED:

a. Logic trainer kit.

b. K Flip Flops (IC-7476).
c. Connecting wires.

7.3. THEORY:

7.3.1. MOD- N COUNTER: The n-bit counter (consists of n Flip Flops) can count maximum 2�
numbers. Its modulus or MOD number is 2� . For example, 3-bit binary counter is a MOD-8 counter.
This basic counter can be modified to produce MOD numbers less than 2� by allowing the counter to skip
states those are normally part of counting sequence. Let us design MOD-6 counter using J-K Flip Flops.

Step 1: Find number of Flip Flops required to build the counter: If we are designing MOD-N counter
and n number of flip-flops are required then n can be found out by this equation: N <=2n
Here we are designing Mod-6 counter. Therefore, N= 6 and number of Flip flops (n) required is 3.

Step 2: Draw the state diagram: This counter counts from 0 to 5 and again reset to 0.

Step 3: Write a previous state and next state table:

Previous state Next state

QA QB QC QA+1 QB+1 QC+1
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 0 0 0

47
Step 4: Write an excitation table for J-K Flip flops:

Previous state Next state Flip flop inputs

QA QB QC QA+1 QB+1 QC+1 JA KA JB KB JC KC
0 0 0 0 0 1 0 × 0 × 1 ×
0 0 1 0 1 0 0 × 1 × × 1
0 1 0 0 1 1 0 × × 0 1 ×
0 1 1 1 0 0 1 × × 1 × 1
1 0 0 1 0 1 × 0 0 × 1 ×
1 0 1 0 0 0 × 1 0 × × 1
1 1 0 × × × × × × × × ×
1 1 1 × × × × × × × × ×

Step 5: K-map simplification for flip flop inputs:

48
Step 6: Implementation of the counter:

7.3.2. ADVANTAGES OF MOD- N COUNTER:

a. Can have less than 2� (n is the number of bits) counting states.

7.3.3. DISADVANTAGES OF MOD- N COUNTER:

a. Requirement of additional circuitry in designing a MOD- N (N<2� ) counter.

7.3.4. APPLICATIONS OF MOD- N COUNTER:

a. Can be utilized in Timer/Counter circuit of a microcomputer.

7.4. PROCEDURE:

I. Connections are given as per circuit diagram.

II. Logical inputs are given as per circuit diagram.
III. Observe the output and verify the truth table.

7.5. OBSERVATION TABLE:

7.5.1. PREVIOUS STATE AND NEXT STATE TABLE:

Previous state Next state

QA QB QC QA+1 QB+1 QC+1

49
7.6. RESULT:

Thus the Counter was designed and its truth table is verified.

7.7. PRECATIONS:

• All connections should be made neat and tight.

• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.

7.8. CONCLUSION:

7.9. VIVA QUESTIONS:

Q1. What do you mean by MOD counter.

Q2. State the procedure for designing MOD counter from n-bit ripple counter.
Q3. Draw the circuit for MOD-12 counter. Explain the same with neat waveform.
Q4. What is the similarity between a decade counter and binary counter?
Q5. Design a MOD-5 synchronous counter using J-K Flip flop.

50
 EXPERIMENT – 8

8.1 TITLE: Study of DAC.

8.2. APPARATUS REQUIRED:

a. Logic trainer kit.

b. Resistors.
c. Op amps (IC-741).
d. Connecting wires.

8.2.1. PIN DIAGRAM OF IC-741:

8.3. THEORY: A Digital to Analog Converter (DAC) converts a digital input signal into an analog
output signal. The digital signal is represented with a binary code, which is a combination of bits 0 and 1.
The block diagram of DAC is shown in the following figure −

A Digital to Analog Converter (DAC) consists of a number of binary inputs and a single output. In
general, the number of binary inputs of a DAC will be a power of two.

51
8.3.1. TYPES OF DAC: There are two types of DAC: Weighted Resistor DAC and R-2R Ladder DAC.

WEIGHTED RESISTOR DAC: A weighted resistor DAC produces an analog output, which is almost
equal to the digital (binary) input by using binary weighted resistors in the inverting adder circuit. In short,
a binary weighted resistor DAC is called as weighted resistor DAC. The circuit diagram of a 3-bit binary
weighted resistor DAC is shown in the following figure:

The bits of a binary number can have only one of the two values. i.e., either 0 or 1. Let the 3-bit binary
input is �2 �1 �0 . Here, the bits �2 and �0 denote the Most Significant Bit (MSB) and Least Significant Bit
(LSB) respectively. The digital switches shown in the above figure will be connected to ground, when the
corresponding input bits are equal to ‘0’. Similarly, the digital switches shown in the above figure will be
connected to the negative reference voltage, (− VR ) when the corresponding input bits are equal to ‘1’. In
the above circuit, the non-inverting input terminal of an op-amp is connected to ground. That means zero
volts is applied at the non-inverting input terminal of op-amp. According to the virtual short concept, the
voltage at the inverting input terminal of op amp is same as that of the voltage present at its non-inverting
input terminal. So, the voltage at the inverting input terminal’s node will be zero volts. The output voltage
(Vo ) is:
1 1 1
�� = − �� {�2 ( 20 ) + �1 ( 21 ) + �0 ( 22 )}

R-2R LADDER DAC: The R-2R Ladder DAC overcomes the disadvantages of a binary weighted
resistor DAC. As the name suggests, R-2R Ladder DAC produces an analog output, which is almost equal
to the digital (binary) input by using a R-2R ladder network in the inverting adder circuit. The circuit
diagram of a 3-bit R-2R Ladder DAC is shown in the following figure:

52
The bits of a binary number can have only one of the two values. i.e., either 0 or 1. Let the 3-bit binary
input is �2 �1 �0 . Here, the bits �2 and �0 denote the Most Significant Bit (MSB) and Least Significant Bit
(LSB) respectively. The digital switches shown in the above figure will be connected to ground, when the
corresponding input bits are equal to ‘0’. Similarly, the digital switches shown in above figure will be
connected to the negative reference voltage, (− VR ) when the corresponding input bits are equal to ‘1’. It
is difficult to get the generalized output voltage equation of a R-2R Ladder DAC. But, we can find the
analog output voltage values of R-2R Ladder DAC for individual binary input combinations easily.

8.3.2. ADVANTAGES OF DAC:

a. Large digital – binary inputs can be converted into its analog form easily.
b. One of the fastest methods of conversion.
c. Simple circuitries to implement.

8.3.3. DISADVANTAGES OF DAC:

a. Circuits use expensive operational amplifiers.
b. Some errors like – gain error, offset error, Non-linearity is generally caused by resister employed in
the circuit.
c. Power dissipation is high.

53
8.3.4. APPLICATIONS OF DAC:

a. Audio Processing.
b. Video Encoding.
c. Digital Display.
d. Calibration.
e. Controlling Motor.
8.4. PROCEDURE:

I. Connections are given as per circuit diagram.

II. Logical inputs are given as per circuit diagram.
III. Observe the output and verify the truth table.

8.5. OBSERVATION TABLE:

8.5.1. TRUTH TABLE OF DAC:

�2 �1 �0 VO

8.6. RESULT:

Thus the DAC was designed and its truth table is verified.

8.7. PRECATIONS:

• All connections should be made neat and tight.

• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.

8.8. CONCLUSION:

8.9. VIVA QUESTIONS:

Q1. What is the primary disadvantage of the flash analog-to digital converter (ADC)?
Q2.What is the major advantage of the R/2R ladder digital-to-analog (DAC), as compared to a binary-
weighted digital-to-analog DAC converter?

54
Q3. A 4-bit R/2R digital-to-analog (DAC) converter has a reference of 5 volts. What is the analog output for
the input code 0101.
Q4. What is the resolution of a digital-to-analog converter (DAC)?

55
 EXPERIMENT – 9

9.1 TITLE: Design a Class A amplifier

9.2. APPARATUS REQUIRED:

a. Class A power amplifier trainer kit.

b. Transistor-CL 100.
c. Resistors- 1k, 2.2 k, 4.7k, 8.2k, 33k.
d. Capacitors-10µF.
e. Function Generator.
f. CRO.
g. BNC Probes and connecting wires.
h. 12 volt Power Supply.

9.3. THEORY: The amplifier is said to be class A power amplifier if the q point and the input signal are
selected such that the output signal is obtained for a full input cycle. For this class the position of q point
is approximately y at the midpoint of the load line. For all the values of input signal the transistor remains
in the active region and never entire into the cutoff or saturation region. The collector current flows for
3600 (life cycle) of the input signal in other words the angle of the collector current flow is 3600 the class
a amplifiers or furthers classified as directly coupled and transformer coupled and transformer coupled
amplifiers in directly coupled type .The load is directly connected in the collector circuit while in the
transformer coupled type, the load is coupled to the collector using the transformer.

9.3.1. CIRCUIT DIAGRAM:

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9.3.2. ADVANTAGES OF CLASS A AMPLIFIER:
a. Distortion analysis is very important.
b. It amplifies audio frequency signals faithfully hence they are called as audio amplifiers.

9.3.3. DISADVANTAGES OF CLASS A AMPLIFIER:

a. H parameter analysis is not applicable.
b. Due to large power handling the transistor is used power transistor which is large in size and having
large power rating.

9.3.4. APPLICATIONS OF CLASS A AMPLIFIER:

a. Low-level amplifier in audio circuits.

b. RF and IF stages of receivers of all kinds.
c. Video stages of TV receivers and displays.

9.4. PROCEDURE:

I. Switch ON Class –A power amplifier trainer.

II. Set Vs (say 250 to 300 mV), at 10 KHz using signal generator.
III. Connect milli ammeter to the ammeter terminals.
IV. By keeping the input voltage constant, vary the frequency from 0 to 1MHz in
regular steps.
V. Note down the corresponding output voltage from CRO.
VI. Calculate the DC input power using the formula Pdc= VccIc.
VII. Calculate the AC output power using the formula Pac = VO2/8RL.
VIII. Calculate the efficiency η = Pac /Pdc.
IX. Plot the graph between Gain (db) and frequency.
X. Calculate bandwidth from the graph.

9.5. CALCULATIONS:
Input power: Pdc= VccIc =
Outpower: Pac = VPP2/8RL =
η = Efficiency=output power/input power*100 = Pac /Pdc*100 =

9.6. EXPECTED GRAPH:

9.6.1. INPUT:

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9.6.2. OUTPUT:

9.7. RESULT:

Gain and frequency as observed of Class A power amplifier.

η = Efficiency=output power/input power*100
η = Pac /Pdc*100 =

9.8. PRECATIONS:

• Check connections before switching ON power supply.

• Don’t apply over voltage.
• When you are not using the equipment switch them OFF.
• Handle all equipment carefully.

9.9. CONCLUSION:

9.10. VIVA QUESTIONS:

Q1. On which criteria based the power amplifiers are classified?

Q2. What is the operating point of class-A power Amplifier?
Q3. What is meant by efficiency?
Q4. How much efficiency will be obtained in Class-A Power Amplifier?
Q5. What are the applications of Power Amplifier?

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 EXPERIMENT – 10

10.1 TITLE: Design a Phase-Shift Oscillator.

10.2. APPARATUS REQUIRED:

a. Op amp (IC-741).
b. Bread Board.
c. DC Dual power supply.
d. Oscilloscope.
e. Capacitors & Resistors.

10.3. THEORY: The basic RC Oscillator which is also known as a Phase-shift Oscillator, produces a sine
wave output signal using regenerative feedback obtained from the resistor-capacitor combination. This
regenerative feedback from the RC network is due to the ability of the capacitor to store an electric charge.
This resistor-capacitor feedback network can be connected to produce a leading phase shift (phase
advance network) or interchanged to produce a lagging phase shift (phase retard network) the outcome is
still the same as the sine wave oscillations only occur at the frequency at which the overall phase-shift is
360o. By varying one or more of the resistors or capacitors in the phase-shift network, the frequency can
be varied and generally this is done by keeping the resistors the same and using a 3-ganged variable
capacitor. In a Resistance-Capacitance Oscillator or simply an RC Oscillator, we make use of the fact that
a phase shift occurs between the input to a RC network and the output from the same network by using
RC elements in the feedback branch, for example.

10.3.1. RC PHASE-SHIFT NETWORK: The circuit on the left shows a single resistor-capacitor
network whose output voltage “leads” the input voltage by some angle less than 90o. An ideal single-pole
RC circuit would produce a phase shift of exactly 90o, and because 180o of phase shift is required for
oscillation, at least two single-poles must be used in an RC oscillator design. The phase Shift Network is
represented schematically below:

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10.3.2. CIRCUIT DIAGRAM:

10.3.3. ADVANTAGES OF RC PHASE-SHIFT OSCILLATOR:

a. The oscillator circuit designing is easy with basic components like resistors as well as capacitors.
b. This circuit is not expensive and gives excellent frequency stability.
c. These are mainly suitable for low-frequencies.
d. This circuit is simpler compared with a Wein bridge oscillator because it doesn’t require the
stabilization planning & negative feedback.
e. The circuit output is sinusoidal that is somewhat distortion free.
f. The frequency range of this circuit will range from a few Hz to hundreds of kHz.

10.3.4. DISADVANTAGES OF RC PHASE-SHIFT OSCILLATOR:

a. The output of this circuit is small because of the smaller feedback.
b. It requires 12 volts battery for developing a suitably huge feedback voltage.
c. It is hard for this circuit to create oscillations because of the small feedback.
d. The frequency stability of this circuit is not good to compare with Wien bridge oscillator.

10.3.5. APPLICATIONS OF RC PHASE-SHIFT OSCILLATOR:

a. This phase shift oscillator is used to generate the signals over an extensive range of frequency. They
used in musical instruments, GPS units, & voice synthesis.
b. The applications of this phase shift oscillator include voice synthesis, musical instruments, and GPS
units.

10.4. PROCEDURE:

I. Construct the RC phase circuit on the breadboard as shown in the circuit diagram.
II. Use: V+ = 12 V, V-- = -12 V, Ri = 10kΩ, and Rf = 470kΩ.
III. Capacitor value is 0.0022 uF.
IV. Find fc practically and theoretically.

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10.5. THEORETICAL FREQUENCY CALCULATION:

10.6. EXPECTED GRAPH:

10.7. OBSERVATION TABLE:

Theoretical Frequency of the Oscillator = 2.95KHz

Practical Frequency of the Oscillator = 2.589KHz

10.8. RESULT:

Thus the Oscillator was designed and frequency of oscillation was calculated both theoretically and
practically.

10.9. PRECATIONS:

• Check connections before switching ON power supply.

• Don’t apply over voltage.
• When you are not using the equipment switch them OFF.
• Handle all equipment carefully.

10.10. CONCLUSION: The practical circuit of RC phase shift oscillator is successfully conducted, it has
generated a sine wave of frequency fc=2.589 KHz. The error percentage is 11 %.

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10.11. VIVA QUESTIONS:

Q1. What is the frequency of RC phase shift oscillator?

Q2. What is a phase shift oscillator?
Q3. Why RC oscillators cannot generate high frequency oscillations?
Q4. What are the applications of RC phase shift oscillators?
Q5. What phase shift does RC phase shift oscillator produce?
Q6. Why we need a phase shift between input and output signal?
Q7. How is phase angle determined in RC phase shift oscillator?
Q8. How can we get a maximum phase angle of 90 degrees in RC phase shift oscillator?

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 EXPERIMENT – 11

11.1 TITLE: Design of a Schmitt Trigger using 555 timer.

11.2. APPARATUS REQUIRED:

a. IC 555 timer.
b. Capacitor.
c. Resistor.
d. Power supply ( 0-12V).
e. Multi-meter.
f. CRO.
g. Function Generator.
h. Bread Board.
i. Connecting Wire.

11.3. THEORY: Schmitt trigger converts an irregular – shaped waveform to a square wave or pulse. The
output of Schmitt trigger is a square wave when the input is sine wave or triangular wave, where as if the
input is a saw tooth wave then the output is a pulse wave. So this circuit is also known as squaring circuit.
555 timer can be used as Schmitt trigger. Here two internal comparators are tied together and externally
biased at VCC/2 through R1 & R2. Since the upper comparator will trip at (2/3) VCC and the lower
comparator at (1/3) VCC the bias provided by R1 & R2 is centered within these two thresholds. Thus a
sine wave of sufficient amplitude (> VCC /6 = 2/3 VCC – VCC/2) to exceed the reference levels causes
the internal flip–flop to alternately set and reset providing a square wave output The input voltage Vin
triggers (changes the state of ) the output Vo every time it exceeds certain voltage levels called Upper
threshold voltage, VUT and Lower threshold voltage, VLT. The hysteresis width is the difference
between these two threshold voltages i.e. VUT – VLT.

11.3.1. CIRCUIT DIAGRAM:

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11.3.2. ADVANTAGES OF SCHMITT TRIGGER:
a. Versatility.
b. Cost-effectiveness.
c. Ability to amplify a weak input signal.

11.3.3. DISADVANTAGES OF SCHMITT TRIGGER:

a. The potential for oscillations.
b. The need for precise component values to ensure proper operations.

11.3.4. APPLICATIONS OF SCHMITT TRIGGER:

a. Schmitt triggers are mainly used for changing a sine wave to square wave.
b. They must be utilized in the switch de-bouncer circuit for a noisy otherwise slow input requirements
like to be cleaned up or speed up.
c. These are normally utilized in applications like signal conditioning for removing signals noise
in digital circuits.
d. These are used to implement relaxation oscillators for closed loop negative response designs.
e. These are used in switching power supplies as well as function generators.

11.4. PROCEDURE:

I. Initially set +Vcc = 15 volts.

II. Measure all resistors that are used in the amplifier circuits using the multi-meter and record these
values.
III. As shown in the circuit diagram connect the circuit for Schmitt Trigger on a breadboard.
IV. Before turning any power on, double check the wiring to make sure that it is correct. Make sure that
the power supply to the 555 is correctly wired as not to apply the incorrect polarity to the 555.
V. Apply the input sine wave with peak voltage greater than the designed voltage using function
generator.
VI. Connect the channel–1 of CRO at the input terminals and Channel-2 at the output terminals.
VII. Observe the output square waveform corresponding to input sinusoidal signal.
VIII. Overlap both the input and output waves and note down voltages at positions on sine wave where
output changes its state. These voltages denote the Upper threshold voltage and the Lower threshold
voltage (see EXPECTED WAVEFORMS below).
IX. Verify that these practical threshold voltages are almost same as the theoretical threshold voltages
calculated using formula.
X. Sketch the waveforms on graph paper by noting down the amplitude and the time period of the input
Vin and the output Vo.

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11.5. EXPECTED WAVEFORMS:

11.6. OBSERVATION:

11.6.1. INPUT WAVEFORM:

65
11.6.2. OUTPUT WAVEFORM:

11.7. RESULT:

Hence the output of Schmitt trigger using IC 555 Timer is observed.

11.8. PRECATIONS:

• Check connections before switching ON power supply.

• Don’t apply over voltage.
• When you are not using the equipment switch them OFF.
• Handle all equipment carefully.

11.9. CONCLUSION:

11.10. VIVA QUESTIONS:

Q1. What are the circuits used to generate square wave?

Q2. What do you mean by zero crossing detector?
Q3. Define hysteresis width?
Q4. What are the other names for Schmitt Trigger?
Q5. What is the duty cycle of the output square wave of the Schmitt Trigger?
Q6. What is a Schmitt Trigger?
Q7. For what requirements, Schmitt Trigger is used?
Q8. Define UTP and LTP. What are the values of UTP and LTP for the above circuit?
Q9. What is the basic difference between the comparator and Schmitt trigger?
Q10. Which type of feedback is used in Schmitt trigger?

66