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U1-Introduction To Computer Architecture

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U1-Introduction To Computer Architecture

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CSE2003- Computer Architecture and

Organisation
Course Objectives:
• to provide basic concepts of computer architecture and
Computer organization
• to impart the knowledge of implementation of arithmetic
operations in the computer.
• to develop a deeper understanding of the hardware
environment upon which all processing are carried out.
• to provide knowledge about internals of memory system,
interfacing techniques and subsystem devices.

Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
1
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
CSE2003- Computer Architecture and
Organisation
A student who successfully fulfills the course requirements will
be able to:
1. Identify and explain the building blocks of computer.
2. Recognize addressing modes, and data/instruction formats.
3. Perform the arithmetic operations using various algorithms and number
systems.
4. Design the single cycle data path for an instruction format for a given
architecture.
5. Compare various cache memory mapping techniques.
6. Explain memory control, direct memory access, interrupts, and memory
organization.
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
2
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
CSE2003- Computer Architecture and
Organisation
Student Outcomes (SO): a, b, c
a. An ability to apply the knowledge of mathematics, science and computing
appropriate to the discipline
b. An ability to analyze a problem, identify and define the computing
requirements appropriate to its solution.
c. An ability to design, implement and evaluate a system / computer‐based
system, process, component or program to meet desired needs

U2 -

Books, Web reference:

1. David A. Patterson and John L. Hennessy “Computer Organization and
Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition,
2011.
2. James P Hayes, “Computer Architecture and Organization”, Mc Graw Hill,
3rd Edition, 2012, ISBN:9781259028564.
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
5
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
UNIT 1
U1- Introduction to Computer Architecture:
Introduction to computer systems - Overview of Organization and
Architecture -Functional components of a computer -Registers and register
files-Interconnection of components- Organization of the von Neumann
machine and Harvard architecture-Performance of processor Introduction to
ISA (Instruction Set Architecture)-Instruction formats- Instruction types
and addressing modes- Instruction execution (Phases of instruction cycle)-
Assembly language programming-Subroutine call and return mechanisms-Single
cycle Data path design-Introduction to multi cycle data path-Multi cycle
Instruction execution.

Tutorial on Assembly Language Programming

a computer is a sophisticated electronic calculating machine

that:
Accepting information to be processed as input.
Storing a list of instructions to process the information.
Processing the information according to the list of instructions.
Providing the results of the processing as output.

Stores information:
•Instructions,
•Data
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
8
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Input Unit

Tasks are performed by the input unit:

- Interfaces with input devices.
- Accepts binary information from the input devices.
- Presents this binary information in a format expected by the computer.
- Transfers this information to the memory or processor.

Memory unit stores instructions and data as a series of bits.

Processor reads instructions and reads/writes data from/to the memory
during the execution of a program.
In theory, instructions and data could be fetched one bit at a time.
In practice, a group of bits is fetched at a time.
Group of bits stored or retrieved at a time is termed as “word”
Number of bits in a word is termed as the “word length” of a computer.

Primary storage of the computer consists of RAM units.

Fastest, smallest unit is Cache.
Slowest, largest unit is Main Memory.
Primary storage is insufficient to store large amounts of data and programs.
Primary storage can be added, but it is expensive.

Store large amounts of data on secondary storage devices:

Magnetic disks and tapes,
Optical disks (CD-ROMS).
SSDs
Access to the data stored in secondary storage in slower, but take advantage of the fact that
some information may be accessed infrequently.
Cost of a memory unit depends on its access time, lesser access time implies higher
cost.

Instructions specify commands to:

Transfer information within a computer (e.g., from memory to ALU)
Transfer of information between the computer and I/O devices (e.g., from
keyboard to computer, or computer to printer)
Perform arithmetic and logic operations (e.g., Add two numbers, Perform a
logical AND).

A sequence of instructions to perform a task is called a program,

which is stored in the memory.
Processor fetches instructions that make up a program from the
memory and performs the operations stated in those instructions.
Instruction Example:
add a,b,c

Data is collection of fact an figures.

Data are the “operands” upon which instructions will operate.

Data could be:

Numbers,
Encoded characters.

Data, in a broad sense means any digital information.

Computers use data that is encoded as a string of binary digits
called bits.
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
16
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Arithmetic and Logic Unit
(ALU)
Operations are executed in the Arithmetic and Logic Unit (ALU).
Arithmetic operations such as addition, subtraction.
Logic operations such as comparison of numbers.

In order to execute an instruction, operands need to be brought into the ALU

from the memory.
Operands are stored in general purpose registers available in the ALU.
Access times of general purpose registers are faster than the cache.

Results of the operations are stored back in the memory or retained in the
processor for immediate use.

Register is a very fast computer memory used to speed the

execution of computer programs

Registers are the top of the memory hierarchy, and are the
fastest way for the system to manipulate data.
They are normally measured by the number of bits they can
hold, for example, an “8-bit register” or a “32-bit register”,
“64-bit register”, actually according to the memory word size

There are several other classes of registers:

(a) General Purpose Registers: General purpose registers are used to store
data and intermediate results during program execution. Its contents
can be accessed through assembly programming (R1, R2, R3,…….)
(b) Special Purpose Registers: Users do not access these registers. These
are used by computer system at the time of program execution.

Some types of special purpose registers are given below:

Memory Address Register (MAR): It stores address of data or
instructions to be fetched from memory
Instruction Register (IR): stores the instruction currently being executed .
When one instruction is completed, next instruction is fetched in memory
for processing.
Program Counter (PC): holds the address of the instruction that should be
executed next

•Computers represent information in a specific binary form. Output

units:
- Interfaces with output devices.
- Accepts processed results provided by the computer in specific
binary form.
- Converts the information in binary form to a form understood by an
output device.

Operation of a computer can be summarized as:

Accepts information from the input units (Input unit).
Stores the information (Memory).
Processes the information (ALU).
Provides processed results through the output units (Output unit).

Operations of Input unit, Memory, ALU and Output unit are coordinated by
Control unit.
Instructions control “what” operations take place (e.g. data transfer,
processing).
Control unit generates timing signals which determines “when” a particular
operation takes place.

Bus

•For a computer to achieve its operation, the functional

units need to communicate with each other.
•Functional units may be connected by a group of parallel
wires.
•The group of parallel wires is called a bus.
•Each wire in a bus can transfer one bit of information.
•The number of parallel wires in a bus is equal to the
word length of a computer
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
24
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Buses

There are a number of possible interconnection systems

Single and multiple BUS structures are most common
e.g. Control/Address/Data bus (PC)
e.g. Unibus (DEC-PDP)

A communication pathway connecting two or more devices

Usually broadcast
Often grouped
A number of channels in one bus
e.g. 32 bit data bus is 32 separate single bit channels
Power lines may not be shown

Carries data
Remember that there is no difference between “data” and “instruction” at this level
Width is a key determinant of performance
8, 16, 32, 64 bit

Identify the source or destination of data

e.g. CPU needs to read an instruction (data) from a given location in
memory
Bus width determines maximum memory capacity of system
e.g. 8080 has 16 bit address bus giving 64k address space

Control and timing information

Memory read/write signal
Interrupt request
Clock signals

What do buses look like?

Parallel lines on circuit boards
Ribbon cables
Strip connectors on mother boards
e.g. PCI
Sets of wires

Lots of devices on one bus leads to:

Propagation delays
Long data paths mean that co-ordination of bus use can adversely affect performance
If aggregate data transfer approaches bus capacity
Most systems use multiple buses to overcome these problems

Applications software

Systems software
Hardware

System software
Operating system – supervising program that interfaces the user’s program
with the hardware (e.g., Linux, MacOS, Windows)
Handles basic input and output operations
Allocates storage and memory
Provides for protected sharing among multiple applications
Compiler – translate programs written in a high-level language (e.g., C, Java)
into instructions that the hardware can execute

High-level language program (in C)

swap (int v[], int k)
( int temp;
temp = v[k];
v[k] = v[k+1]; C compiler
v[k+1] = temp;
)
Assembly language program (for MIPS)
swap: sll $2, $5, 2
add $2, $4, $2
.
.
jr $31
Machine (object, binary) code (for MIPS)
000000 00000 00101 0001000010000000assembler
000000 00100 00010 0001000000100000
. . .
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
41
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Content Coverage

Computer architecture refers to those attributes of a system

visible to a programmer or, put another way, those attributes
that have a direct impact on the logical execution of a program.

A term that is often used interchangeably with computer

architecture is instruction set architecture (ISA) . The ISA
defines instruction formats, instruction opcodes, registers,
instruction and data memory; the effect of executed instructions
on the registers and memory; and an algorithm for controlling
instruction execution.
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
43
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Instruction Set Architecture (ISA) … Cntd.
Computer organization refers to the operational units and their
interconnections that realize the architectural specifications.

Examples of architectural attributes include the instruction set,

the number of bits used to represent various data types (e.g.,
numbers, characters), I/O mechanisms, and techniques for
addressing memory. Organizational attributes include those
hardware details transparent to the programmer, such as control
signals; interfaces between the computer and peripherals; and the
memory technology used.
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
44
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Instruction Set Architecture (ISA) … Cntd.
Instruction Set Architecture (ISA), or simply Architecture,
of a computer is the interface between the hardware and the
lowest-level software.

ISA encompasses all the information necessary for

programmers to write a machine language program that will
run correctly, including instructions, registers, memory
access, I/O devices, etc.

ISA allows computer designers to talk about functions

independently from the hardware that performs them
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
45
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Instruction Set Architecture (ISA) (cont.)

Application Binary Interface (ABI) is the combination of the basic

instruction set and the OS interface provided for application programmers
ABI is the user portion of the instruction set plus the OS interfaces used by
application programmers
Binary compatibility is extraordinarily important! It enables upgrading the
computer without having to replace software

Procedure of interrupt operation

The device raises an interrupt signal
The state of the processor is first saved before servicing the interrupt
Normally, the contents of the PC, the general registers, and some control
information are stored in memory
The processor provides the requested service by executing an appropriate interrupt-service
routine
When the interrupt-service routine is completed, the state of the processor is restored so
that the interrupted program may continue
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
47
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Classes of Interrupts

Programmed
Generated by some condition that occurs as a result of an
instruction execution such as arithmetic overflow, division
by zero, attempt to execute an illegal machine instruction,
or reference outside a user’s allowed memory space

Timer (Timed)
Generated by a timer within the processor. This allows the
operating system to perform certain functions on a regular
basis

I/O
Generated by an I/O controller, to signal normal
completion of an operation or to signal a variety of
error conditions

Hardware failure
Generated by a failure such as power failure or
memory parity error

Performance is the key of the effectiveness of an entire system

of hardware and software choosing among different computers
based on their performance.

To improve the performance of a software system, we need to

know:
– what hardware factors contribute to overall system
performance

– the relative importance of these factors

– Also known as response time, elapsed time, or latency

– It is the time between the start and completion of a task

– Measured in seconds per program

– The computer that performs the same amount of work in the least time is the
fastest

– Important for individual computer users

– It is the total amount of work done in a given time

– Important for datacenter managers

Decreasing execution time almost always improves throughput

Changing either execution time or throughput often affects the

other
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
53
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Measuring Performance (cont.)

CPU execution time (simply CPU time)

• The actual time the CPU spends computing a task’s lines of code

• Does not include time spent waiting for I/O activities or

running other programs

CPU time can be further divided into:

– User CPU time
• the CPU time spent in the program itself
• expresses CPU performance

– System CPU time

• the CPU time spent in the OS performing tasks on
behalf of the program

Do the following changes to a computer system decrease

response time, increase throughput, or both?
Replacing the processor in a computer with a faster
version
Both response time and throughput are improved

Adding additional processors to a system that uses multiple

processors for separate tasks, e.g., searching the WWW
• No one task gets work done faster
• Only throughput increases
• If demand for processing is as large as the
throughput, the system might force requests to queue up
• In this case, increasing the throughput could also
improve response time, since it would reduce the waiting
time in the queue

To maximize performance, minimize response time or

execution time for some task
𝟏
𝑷𝒆𝒓𝒇𝒐𝒓𝒎𝒂𝒏𝒄𝒆 =
𝑬𝒙𝒆𝒄𝒖𝒕𝒊𝒐𝒏 𝒕𝒊𝒎𝒆

SPEEDUP: "X is n times faster than Y” means:

𝑷𝒆𝒓𝒇𝒐𝒓𝒎𝒂𝒏𝒄𝒆𝒙 𝑬𝒙𝒆𝒄𝒖𝒕𝒊𝒐𝒏 𝒕𝒊𝒎𝒆𝒚
= =𝒏
𝑷𝒆𝒓𝒇𝒐𝒓𝒎𝒂𝒏𝒄𝒆𝒚 𝑬𝒙𝒆𝒄𝒖𝒕𝒊𝒐𝒏 𝒕𝒊𝒎𝒆𝒙

If computer A runs a program in 10 seconds and computer B runs the same

program in 15 seconds
– How much faster is A than B? SpeedUP?

𝑷𝒆𝒓𝒇𝒐𝒓𝒎𝒂𝒏𝒄𝒆𝑨 𝑬𝒙𝒆𝒄𝒖𝒕𝒊𝒐𝒏 𝒕𝒊𝒎𝒆𝑩 𝟏𝟓

= = = 𝟏. 𝟓
𝑷𝒆𝒓𝒇𝒐𝒓𝒎𝒂𝒏𝒄𝒆𝑩 𝑬𝒙𝒆𝒄𝒖𝒕𝒊𝒐𝒏 𝒕𝒊𝒎𝒆𝑨 𝟏𝟎

Computer C’s performance is 4 times faster than the performance of computer

B, which runs a given application in 28 seconds

– How long will computer C take to run that application?

10 nsec clock cycle => 100 MHz clock rate

5 nsec clock cycle => 200 MHz clock rate
2 nsec clock cycle => 500 MHz clock rate
1 nsec (10-9) clock cycle => 1 GHz (109) clock rate
500 psec clock cycle => 2 GHz clock rate
250 psec clock cycle => 4 GHz clock rate
200 psec clock cycle => 5 GHz clock rate
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
63
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Clock Cycles Per Instruction

Different instructions take different amounts of time depending

on what they do:
– Multiplication takes more time than addition
– Floating point operations take longer than integer ones
– Accessing memory takes more time than accessing registers
Instructions can be divided into classes of similar instructions
Instructions in the same class have the same Clock cycles Per
Instruction (CPI) value

Total CPU clock cycles for a certain program can be calculated by looking at
various instruction classes and their individual CPIs
𝒏

𝑪𝑷𝑼 𝒄𝒍𝒐𝒄𝒌 𝒄𝒚𝒄𝒍𝒆𝒔 𝒇𝒐𝒓 𝒂 𝒑𝒓𝒐𝒈𝒓𝒂𝒎 = ෍(𝑪𝑷𝑰𝒊 ∗ 𝑪𝒊 )

𝒊=𝟏
– CPIi is the clock cycles per instruction for class i (integer number),
– Ci is the count of instructions executed from class i, and
– n is the number of instruction classes

The CPU time for a program can be expressed in two ways:

A program runs on computer A with a 2 GHz clock in 10

seconds. What clock rate must a computer B run at to run
this program in 6 seconds? Unfortunately, to accomplish this,
computer B will require 1.2 times as many clock cycles as
computer A to run the program.

Collection of bits are stored or retrieved simultaneously is called a word

Number of bits in a word is called word length

Word length can be 16 to 64 bits

Collection of 8 bits known as a “byte”

Word length of 16 bits, is equivalent to word length of 2 bytes

Words may be 2 bytes (older architectures), 4 bytes (current architectures), or

8+ bytes (modern architectures).
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
70
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Memory organization (cont.)
Accessing the memory to obtain information requires specifying
the “address” of the memory location

Addresses are assigned to a single byte. “Byte addressable

memory”
Suppose k bits are used to hold the address of a memory
location: size of the memory in bytes is given by 2
k

For example, a 24-bit address generates an address space of 2

(16,777,216) locations (bytes)

Word #0 starts at Byte #0.

Word #? Byte 65532 Word #1 starts at Byte #4.
Byte 65533
Byte 65534
Byte 65535
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
74
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Execution of an instruction

The steps involved in the execution of an instruction by a

processor:
Fetch an instruction from the memory.
Fetch the operands.
Execute the instruction.
Store the results.

Basic processor architecture has several registers to assist in

the execution of the instructions.

Instruction Register (IR):

Instruction that is currently being executed.
Program Counter (PC):
Address of the next instruction to be fetched and executed.
Memory Address Register (MAR):
Address of the memory location to be accessed.
Memory Data Register (MDR):
Data to be read into or read out of the current memory
location, whose address is in the Memory Address Register
(MAR).

Memory Address of the memory

location to be accessed
Address of the next
instruction to be fetched
and executed. Data to be read into or
read out of the current
location
MAR MDR
Control

PC R0

R1 General purpose
IR registers
Instruction that is
currently being ALU
executed R(n-1)
-

general
n purpose
registers Processor

Control Data
Path Path

MAR MDR Processor

Control path is responsible for:

•Instruction fetch and execution sequencing
•Operand fetch
•Saving results
Data path:
•Contains general purpose registers
•Contains ALU
•Executes instructions
Memory
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
78
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Fetch/Execute cycle

Execution of an instruction takes place in two phases:

Instruction fetch.
Instruction execute.
Instruction fetch:
Fetch the instruction from the memory location whose address is in the Program Counter
(PC).
Place the instruction in the Instruction Register (IR).

Instruction execute:
Instruction in the IR is examined (decoded) to determine which operation is to be
performed.
Fetch the operands from the memory or registers.
Execute the operation.
Store the results in the destination location.
Basic fetch/execute cycle repeats indefinitely.

Addr 65532 Byte 65532 Word #16383

Byte 65533 MDR contains either the
Byte 65534 data to be written to that
address or read from that
Byte 65535
Ref:
address.
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
81
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
82
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
83
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Addressing Modes

A high-level language enables the programmer to use constants, local and global
variables, pointers, and arrays
When translating a high-level language program into assembly language, the
compiler must be able to implement these constructs using the facilities in the
instruction set of the computer
The different ways in which the location of an operand is specified in an
instruction are referred to as addressing modes
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
84
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Addressing Modes (cont.)

Some of important addressing modes are:

Immediate mode
Register mode
Absolute mode
Indirect mode
Index mode

Register mode
Operand is the contents of a processor register.
Address of the register (its Name) is given in the instruction.
E.g. Clear R1 or Move R1, R2

Operand is in a memory location.

Address of the memory location is given explicitly in the
instruction.

E.g. Clear A or Move R2, LOC

Also called as “Direct mode” in some assembly languages

Indirection is denoted by placing the name of the register or the

memory address given in the instruction in parentheses
The register or memory location that contains the address of an
operand is called a pointer

E.g. Move R1, (R2): in this case R2 contains the address of the
operand to be loaded in R1
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
88
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Register Indirect Addressing Diagram

The index mode is useful in dealing with lists and arrays

We denote the Index mode symbolically as X(Ri), where X denotes the
constant value (offset) contained in the instruction and Ri is the name of
the register involved.

The effective address of the operand is given by EA=X+(Ri).

E.g. Move R1, X(R2): in this case X+R2 represents the address of the
operand to be loaded in R1
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
90
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Instruction types
Computer instructions must be capable of performing 4 types of
operations.

1. Arithmetic and logic operations:

E.g., addition, subtraction, comparison between two numbers.

2. Data transfer/movement between memory and processor registers.

E.g., memory read, memory write

3. Program sequencing and flow of control:

Branch instructions (decisions and loops)

4. Input/output transfers: to transfer data to and from the real world.

MIPS assembly language notation for arithmetic operations:

operation destination, source1, sourse2

Each MIPS arithmetic instruction performs only one operation

Each MIPS arithmetic instruction must have exactly three operands

Operand order is fixed (destination first)

The words to the right of the sharp symbol (#) are comments
Comments always terminate at the end of a line

C code:
a = b + c + d + e;
g = a - f;

MIPS code:
add a, b, c # b + c → a
add a, a, d # a + d → a
add a, a, e # a + e → a
sub g, a, f # a - f → g

In MIPS, arithmetic instructions’ operands must be registers

MIPS has only 32 registers (limited number!) • For MIPS, a word is 32 bits
(or 4 bytes) •

MIPS registers hold 32 bits of data (a word size)

MIPS is a general-purpose register architecture
MIPS registers are general-purpose registers (GPRs)
MIPS registers can be used for addresses or data with any instruction

It is the compiler’s job to associate program variables with registers

MIPS code:
add $t0, $s2, $s3 # $t0 is a temporary register
add $t1, $s4, $s5 # $t1 is a temporary register
sub $s1, $t0, $t1
add $s0, $s1, $zero # copy f ($s1) to e ($s0)
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
98
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Data Transfer Instructions
Data transfer instructions: transfer data between memory and registers

load word (lw): copies a word from memory to a register

store word (sw): copies a word from a register to memory

lw $s0, c ($s1) # Memory [$s1 + c] → $s0

sw $s0, c ($s1) # $s0 → Memory [$s1 + c]

$s1 is the Index (base) register

constant c is the offset

MIPS memory is only accessed through loads and stores

The address is:1000+4600=5600

it writes the word in the register $s5 to the memory location 5600 and loads
it in
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
101
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Exercise (4)
Lets also assume that the base address of the integer array d is in register $s4
and a value is in register $s1
Compile the following C statement into MIPS assembly code:
d[3] = d[2] + a;

Lets also assume that the base address of the integer array A is in register $s3
Compile the following C statement into MIPS assembly code:

A[i] = h + A[8];

Language of The Computer

(MIPS)

106
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Small Constant or Immediate Operands
A faster way is to use the arithmetic instruction version in which one
operand is a constant of up to 16 bits
addi $s3, $s3, 4 # add immediate
# $s3 = $s3 + 4

Before performing the addition, addi extends the 16-bit immediate

field of the instruction to a 32-bit word by copying the leftmost (sign)
bit of the constant into the upper 16 bits of the word (sign extension)

e.g. 0000 0000 1100 0101 represents 389,it will be extended

to 0000 0000 0000 0000 0000 0000 1100 0101
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
107
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Small Constant or Immediate Operands
Since MIPS supports negative constants, there is no need for
subtract immediate in MIPS

addi $s3, $s3, -4 # add immediate

# $s3 = $s3 - 4

NOT is implemented using a NOR with one operand being $zero for regularity
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
109
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Exercise 1

Consider the following register contents:

$s0 = 0001 0000 1100 0101 1111 1100 0011 1010
$s1 = 0101 0110 1001 1111 0000 0011 1100 0101
What would the value in register $t0 be after executing each
of the following instructions?
1. sll $t0, $s0, 4
2. and $t0, $s0, $s1
3. or $t0, $s0, $s1
4. nor $t0, $s0, $s1

$s0 = 0001 0000 1100 0101 1111 1100 0011 1010

$s1 = 0101 0110 1001 1111 0000 0011 1100 0101

Write MIPS assembly instructions to

–Set bits 1, 5, and 12 of $s0 to 0
–Set bits 2, 3, 11 of $s0 to 1
–Invert all bits of $s0
Hint: you can use register $t1 for a mask

Set bits 1, 5, and 12 of $s0 to 0

$t1 = 1111 1111 111111111110 1111 1101 1101
and $s0, $s0, $t1
Set bits 2, 3, 11 of $s0 to 1
$t1 = 0000 00000000000000001000 0000 1100
or $s0, $s0, $t1
Invert all bits of $s0
nor $s0, $s0, $zero

0000 0000 0011 1101 0000 1001 0000 0000

Lui $s0, 61 # 61 is 0000 0000 0011 1101

The value of register $s0 afterward is
Ori $s0,$s0,2304 # 2304 is 0000 1001 0000 0000

The value of register $s0 now is

Decision making instructions alter the control flow

Decisions can be done by:
–Choosing from two alternatives: if-else (may be combined with goto)
–Iterating a computation: loops(e.g., while, do-while, for, etc.)
–Selecting one of many alternatives: case/switch

MIPS conditional branch instructions:

beq $t0, $t1, Label # branch if equal
bne $t0, $t1, Label # branch if not equal
MIPS unconditional branch instructions:
j Label # Label is a word address
jr $t0 # jump register (to address in $t0)

Assuming that the five integer variables f through j correspond to the

five registers $s0 through $s4
What is the compiled MIPS assembly code for the following C code
segment?
if(i == j)
gotoL1;
f = g + h;
L1:f = f -i;

C Code:
if(i == j)
gotoL1;
f = g + h;
L1:f = f -i;
MIPS Code:
beq $s3, $s4, L1
add $s0, $s1, $s2
L1:sub $s0, $s0, $s3
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
120
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Exercise 5

Assuming that the five integer variables f through j correspond to

the five registers $s0 through $s4
What is the compiled MIPS assembly code for the following C code
segment?
if(i == j)
f = g + h;
else
f = g -h;

C Code: if(i == j)
f = g + h;
else
f = g -h;
MIPS Code:
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else:sub $s0, $s1, $s2
Exit:

Slt $t0, $s3, $s4 # Set on less than

# Sets $t0 to 1 if $s3 < $s4
# else sets it to 0
Slti $t0, $s2, 10 # slti mmediate
# Sets $t0 to 1 if $s2 < 10
# else sets it to 0

MIPS architecture does not include a single compare and

branch instruction because it is too complicated
Either it would stretch the clock cycle time or it would take
extra clock cycles per instruction
Two faster instructions are more useful

Common variations of assembly instructions that are not part of

the instruction set
Often appear in MIPS programs and are treated as regular ones
Their appearance in assembly language simplifies programming
The assembler produces a minimal sequence of actual MIPS
instructions to accomplish their operations
The assembler uses the $at register to accomplish this, if needed

clear $s3 # 0 →$s3

add $s3, $zero, $zero # using $zero
move $s3, $s4 # $s4 →$s3
add $s3, $s4, $zero # Example 2 on using $zero
not $s3, $s4 # not($s4) →$s3
nor $s3, $s4, $zero # Example 3 on using $zero
blt $s3, $s4, Less # branch on less than
slt $at, $s3, $s4
bne $at, $zero, Less # Example 4 on using $zero

Decompile the following MIPS assembly code to a C code

segment
slti $at, $s5, 5
beq $at, $zero, Else
add $s6, $s5, $zero
j Exit
Else:add $s6, $zero, $zero
Exit:
Assume that the decompiler associates registers $s5 and
$s6 with integer variables i and x

C Code: if(i < 5) x = i;

else x = 0;
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
129
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Exercise 8

Assuming A is an integer array with base in $s4 and that the

compiler associates the integer variables g, i, and n with the
registers $s1, $s2, and $s3, respectively
What is the compiled MIPS assembly code for the following C
code segment?
for(i = 0; i < n; i++)
g = g + A[i];

There are two ways to implement case/switch statements: –

1. Turn a switch statement into a chain of if-then-else
statements in the high-level language and then into chained
conditional jumps MIPS
2. Encode a table of addresses of alternative instruction
sequences, called a jump address table ( Jump Table)

L0: add $s0,$s3, $s4 #f=i+j

j Exit # break
L1: add$ $s0,$s1, $s2 #f=g+h
j Exit # break
L2: sub $s0,$s1, $s2 # f = g –h
j Exit # break
L3: sub $s0,$s3, $s4 # f = i –j
j Exit # break
Exit: Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
136
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Exercise 2 Sol.
Jump Table
the Jump Table is just an array of words containing addresses that
correspond to labels in the code
the program loads the appropriate entry from JumpTable into a register
and then it jumps to the proper address using a jump register (jr)
To access the JumpTable, assume that four sequential words in memory,
starting at an address contained in register $t4, have addresses
corresponding to the labels L0, L1, L2, and L3

L0: add $s0,$s3, $s4 #f=i+j

j Exit # break
L1: add$ s0,$s1, $s2 #f=g+h
j Exit # break
L2: sub $s0,$s1, $s2 # f = g –h
j Exit # break
L3: sub $s0,$s3, $s4 # f = i –j
j Exit # break
Exit: Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
138
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Instruction Formats

Register format: R-format

Used by arithmetic and logical instructions
Immediate format: I-format
Used by data transfer instructions
Used by instructions that have immediate operands
Used by relative-address branching
Jump format: J-format
Used by absolute-jump instructions
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
139
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Instruction Formats (cont.)

op: basic operation of the instruction, traditionally called opcode

rs: the first register source operand
rt: the second register source operand in R-format. This field
sometimes specifies a destination register in I-format
rd: the register destination operand that gets the operation result
shamt: shift amount, used in shift instructions
Funct: function code that selects the specific variant of the
operation in the op field in R-format

Show the real MIPS machine language version for the instruction represented
symbolically as
add $t0, $s1, $s2
Registers have numbers: $t0 = 8, $s1 = 17, $s2 = 18

add $t0, $s1, $s2

$t0 = 8, $s1 = 17, $s2 = 18

Show the real MIPS machine language code for the following instruction:
sll $t2, $s0, 4
Registers have numbers: $t2 = 10, $s0 = 16

sll $t2, $s0, 4

$t2 = 10, $s0 = 16

Assemble the following MIPS instruction into real MIPS machine code:
lw $t0, 32 ($s3)
Registers have numbers: $t0 = 8, $s3 = 19

lw $t0, 32 ($s3)
$t0 = 8, $s3 = 19

Show the real MIPS machine language version for the instruction
addi $s1, $s2, 4
Registers have numbers: $s1 = 17, $s2 = 18

addi $s1, $s2, 4

$s1 = 17, $s2 = 18

Assuming that integer array A has its base in $t1 and that $s2 corresponds to
integer variable h, show the real MIPS machine language code for
A[300] = h + A[300];
Registers have numbers: $t0 = 8, $t1 = 9, $s2 = 18
MIPS: lw $t0,1200($s1)
add $t0,$s2,$t0
sw $t0,1200($s1)

The implementation of the processor determines both the

clock cycle time and the number of clock cycles per
instruction (CPI)
We will be examining an implementation that includes a
subset of the core MIPS instruction set:
The memory-reference instructions: lw, sw
The arithmetic-logical instructions: add, sub, and, or, slt
The control flow (branch and jump) instructions: beq, j

A simple implementation that uses a single long clock cycle for every
instruction will be shown
Every instruction begins execution on one clock edge and completes
execution on the next clock edge

clock

Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
156
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
MIPS Summary (cont.)
Instruction Format op funct Instruction Format op funct
add R 010 3210 lw I 35
addi I 8 nor R 0 39
and R 0 36 or R 0 37
andi I 12 ori I 13
beq I 4 sb I 40
bne I 5 sh I 41
j J 2 sll R 0 0
jal J 3 slt R 0 42
jr R 0 8 slti I 10
lb I 32 srl R 0 2
lh I 33 sub R 0 34
lui I 15 sw I 43
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
MIPS Summary (cont.)
MIPS Registers
Register number Preserve on
Name Usage
(decimal) call?
$zero 0 the constant value 0 n.a.
$at 1 reserved for the assembler n.a.
procedure return values and expression
$v0-$v1 2-3 no
evaluation
$a0-$a3 4-7 procedure arguments (parameters) no
$t0-$t7 8-15 temporary registers no
$s0-$s7 16-23 general purpose saved registers yes
$t8-$t9 24-25 more temporary registers no
$k0-$k1 26-27 reserved for the OS n.a.
$gp 28 global pointer yes
$sp 29 stack pointer yes
$fp 30 frame pointer yes
$ra 31 procedure return address yes
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
MIPS Summary (cont.)
Simplicity and regularity
fixed size instructions
small number of instruction formats
opcode always the first 6 bits
Smaller is faster
limited instruction set
limited number of registers in register file
limited number of addressing modes

Immediate addressing: the operand is a constant within the instruction

addi $s1, $s2, 100
Register addressing: the operand is a register
add $s1, $s2, $s3

Base or Index addressing: the operand is at the memory location whose address is the sum of
a register and a constant in the instruction
lw $s1, 100($s2)

Pseudodirect addressing: the jump address is a constant (26 bits) in the instruction
(multiplied by 4) concatenated with the upper 4 bits of the PC
j 2500

There are two different types of logic elements:

1.elements that operate on data values (combinational), e.g., ALU
2.elements that contain state (sequential), e.g., memory and
registers

cycle time rising edge falling edge

A clocking methodology is used in synchronous systems to define when

signals can be read and when they can be written
Edge-triggered – all state changes occur on a clock edge
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
162
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Clocking Methodology (cont.)

Typical execution
read contents of state elements -> send values through combinational logic -> write results to
one or more state elements

The time necessary for the signals to reach state element 2 defines the length of the
clock cycle
The value stored in a state element is changed only when the write control signal is
sent from the control unit and a clock edge occurs
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
163
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Clocking Methodology (cont.)

An edge-triggered methodology allows doing all of the following in

the same clock cycle:
reading the contents of a register
sending the value read through some combinational logic
writing back to that register
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
164
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Generic Implementation
Fetch / Execute Cycle:
use the program counter (PC) to supply the instruction address and
fetch the instruction from memory (and update the PC)
decode the instruction (and read registers)
execute the instruction

Fetch
PC = PC+4

Exec Decode

There are some similarities across different instruction classes, e.g.,

All instruction classes, except j, use the ALU after reading the registers:
Memory-reference instructions use the ALU for an address calculation
Arithmetic-logical instructions use it for the operation execution
The branch instruction (beq) uses it for comparison

After using the ALU, the actions required to complete various instruction
classes differ:
A memory-reference instruction accesses the data memory either to
write data for a store or read data for a load
An arithmetic-logical instruction writes the data from the ALU back
into a register
A branch instruction may need to change the next instruction address
based on the comparison; otherwise the PC should be incremented by 4
to get the address of the next instruction

Control Data
Path Path

MAR MDR Processor

Control path is responsible for:

•Instruction fetch and execution sequencing
•Operand fetch
•Saving results
Data path:
•Contains general purpose registers
•Contains ALU
•Executes instructions
Ref:
Memory
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
168
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Datapath Elements (1)

Datapath element: A functional unit used to operate on or hold data

within a processor
Instruction memory:
Stores and supplies the instructions of a program given an address
No read signal is needed as it is read every clock cycle
This memory is not written

Program counter (PC):

Holds the address of the current
instruction (to be fetched)
No write signal is needed as it is written
every clock cycle
PC adder:
Used to increment the PC to the address
of the next instruction

updating the PC value to be the address of Instruction

Memory
the next (sequential) instruction PC Read Instruction
Address

PC is updated every clock cycle, so it does

not need an explicit write control signal just Fetch
a clock signal PC = PC+4

Reading from the Instruction Memory Exec Decode

doesn’t need an explicit read control signal
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
171
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Fetching Instructions (cont.)
Thick lines (with no width indication) indicate buses of 32 bits

Add

Instruction
Memory
PC Read Instruction
Address

Register file:
A collection of the processor 32
general-purpose registers in which any
register can be read or written by
specifying its number in the file
The register file contains the register
state of the computer
Writes are controlled by the write
control signal (RegWrite)

Arithmetic and logic unit:

The ALU is used to operate on the values read from
the registers
It takes two 32-bit inputs and produces a 32-bit
result, as well as sets a 1-bit signal if the result is
zero
It is controlled by a 4-bit control signal (ALU
operation)

Decoding instructions involves:

sending the fetched instruction’s Control
opcode and function field bits to the Unit
Register
control unit then the control unit File
sends a 4 bit signal to ALU to Read Addr 1
determine the operation Read Addr 2
Read
Data 1
Instruction
reading two values from the Register
File
Write Addr Read
Write Data Data 2
- Register File addresses are
Ref:
contained in the instruction
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
175
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Executing R Format Operations

R format operations (add, sub, slt, and, or)

perform operation (op and funct) on values in rs and rt
store the result back into the Register File (into location rd)

31 25 20 15 10 5 0
R-type: op rs rt rd shamt funct

4 ALU operation
Read
register 1 Read
Read data 1 ALU
Instructio n register 2 Zero
Registe rs ALU
Write result
register Read
Write data 2
data
Reg Write

store value (read from the Register File during decode)

written to the Data Memory (needs a read control
signal(MemRead))

load value, read from the Data Memory, written to the

A L U o p e r a ti o n
Read 4
re g is te r 1 M e m W ri t e
Read
d a ta 1
Read
re g is te r 2 Zero
I n s t r u c ti o n
R e giste r s ALU ALU
W ri t e Read
re s ult A d d re s s
re g is te r d a ta
Read
d a ta 2
W ri t e
D a ta
d a ta
m e m o ry
R e g W ri t e W ri t e
d a ta

16 32
S ig n Mem Read
e x te n d

$s0

$s2
content
$s1 content + $s2 content
Ref:
Write the result to register $s0
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
181
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
addi $s0, $s1, 20
$s1
$s1 content

$s0

16 bit 32 bit
represents represents
20 20
$s1 content + 20
Ref:
Write the result to register $s0
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
182
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
lw $s0, 100($s1)
Calculated memory address
$s1
$s1 content

$s0

16 bit 32 bit
represents represents
100 100 memory address
content
Ref:
Write memory address content to register $s0
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
183
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
sw $s0, 100($s1)
Calculated memory address
$s1
$s1 content
$s0

16 bit 32 bit
represents represents
100 100
Data to be written in
Ref:
the memory address
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
184
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Executing Branch Operations

Branch operations involves:

compare the operands read from the Register File during decode for equality (zero ALU
output)
compute the branch target address by adding the updated PC to the 16-bit signed-extended
constant field in the instruction
beq $s1, $s2, 100

Jump operation involves:

replace the lower 28 bits of the PC with the lower 26 bits of the fetched
instruction shifted left by 2 bits

Add

4 4
Jump
Instruction Shift address
Memory left 2
28
PC Read Instruction
Address 26

Execution steps for R-type instructions:

1. The instruction is fetched from the instruction memory, and the PC is incremented
2. Two register values are read from the register file using bits 25:21 and 20:16 of the
instruction to select the source registers
a) also, the main control unit computes the setting of the control lines during this
step
3. The ALU operates on the data values read from the register file, using the function code
(bits 5:0, which is the funct field, of the instruction) to generate the ALU function
4. The result from the ALU is written into the register file using bits 15:11 of the instruction
to select the destination register

Execution steps for a lw instruction:

1. The instruction is fetched from the instruction memory, and the PC is incremented
2. A register value is read from the register file using bits 25:21 of the instruction to
select the source register
a) also, the main control unit computes the setting of the control lines during this
step
3. The ALU computes the sum of the value read from the register file and the sign-
extended, lower 16 bits of the instruction
4. The sum from the ALU is used as the address for the data memory
5. The data from the memory unit is written into the register file using bits 20:16 of the
instruction to select the destination register

Execution steps for a beq instruction:

1. The instruction is fetched from the instruction memory, and the PC is incremented
2. Two register values are read from the register file using bits 25:21 and 20:16 of the
instruction to select the source registers
a) also, the main control unit computes the setting of the control lines during this step
3. The ALU performs a subtract on the data values read from the register file
a) The value of PC+4 is added to the sign-extended 16 bits constant of the instruction
shifted left by two, the result is the branch target address
4. The Zero result from the ALU is used to decide which adder result to store into the PC

Uses the clock cycle inefficiently – the clock cycle must be

timed to accommodate the slowest instruction
Cycle 1 Cycle 2
Clk

lw sw Waste

May be wasteful of area since some functional units (e.g.,

adders) must be duplicated since they can not be shared
during a clock cycle but Is simple and easy to understand

Under ideal conditions and with a large number of instructions,

the speedup from pipelining is approximately equal to the number
of pipe stages
A five stage pipeline is nearly five times faster because the CC is nearly five times faster

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5

lw IFetch Dec Exec Mem WB

IFetch: Instruction Fetch and Update PC

Dec: Registers Fetch and Instruction Decode
Exec: Execute R-type; calculate memory address
Mem: Read/write the data from/to the Data Memory
WB: Write the result data into the register file
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
194
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
A Pipelined MIPS Processor

Start the next instruction before the current one has

completed
improves throughput - total amount of work done in a given time
instruction latency (execution time - time from the start of an instruction to its completion)
is not reduced
clock cycle (pipeline stage time) is limited by the slowest stage
for some stages don’t need the whole clock cycle (e.g., WB)
for some instructions, some stages are wasted cycles (i.e., nothing is done
during that cycle for that instruction)

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8

lw IFetch Dec Exec Mem WB

sw IFetch Dec Exec Mem WB

R-type IFetch Dec Exec Mem WB

Single Cycle Implementation (CC = 800 ps):

Cycle 1 Cycle 2
Clk

lw sw Waste

Pipeline Implementation (CC = 200 ps): ❑ To complete an entire

lw IFetch Dec Exec Mem WB instruction in the
pipelined case takes
sw IFetch Dec Exec Mem WB 1000 ps
R-type IFetch Dec Exec Mem WB

What makes it easy

all instructions are the same length (32 bits) so they can fetch in the 1st stage and decode in
the 2nd stage
Some instructions can begin reading register file in 2nd stage
memory operations occur only in loads and stores and can use the execute stage to
calculate memory addresses
each instruction writes at most one result (i.e., changes the machine state) and does it in the
last two pipeline stages (MEM or WB)
operands must be aligned in memory so a single data transfer takes only one data memory
access

IF/ID ID/EX EX/MEM

Add
Shift Add MEM/WB
4
left 2
Read Addr 1
Instruction Read Data
Register
Memory Memory
Read Addr 2 Data 1
Read File
PC

Read
Address ALU Address
Write Addr Data
Read
Data 2 Write Data
Write Data

Sign
16 Extend 32

System
Ref:
Clock
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
199
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Graphically Representing MIPS Pipeline

Reg ALU DM Reg

IM
(ID) (MEM) (WB)
(IF)
(EX)

Once the pipeline is full,

ALU
I Inst 0 IM Reg DM Reg one instruction is
n completed every cycle,
s so CPI = 1

ALU
t Inst 1 IM Reg DM Reg
r.

ALU
O Inst 2 IM Reg DM Reg
r
d

ALU
e Inst 3 IM Reg DM Reg
r

ALU
Inst 4 IM Reg DM Reg

Time to fill the pipeline

Yes: Pipeline Hazards

structural hazards: attempt to use the same resource by two different instructions at the
same time
data hazards: attempt to use data before it is ready
An instruction’s source operand(s) are produced by a prior instruction still in
the pipeline
control hazards: attempt to make a decision about program control flow before the condition
has been evaluated and the new PC target address calculated
branch and jump instructions

Reading data from memory

ALU
I Mem Reg Mem Reg
n
s

ALU
t Inst 1 Mem Reg Mem Reg
r.

ALU
O Inst 2 Mem Reg Mem Reg
r
d

ALU
e Inst 3 Mem Reg Mem Reg

ALU
Inst 4 Mem Reg Mem Reg
Reading instruction from
memory
❑ Fix with separate instruction and data memories (I$ and D$)
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
203
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
How About Register File Access?
Time (clock cycles)

Fix register file access hazard

add $s1,

ALU
I IM Reg DM Reg by doing reads in the second
n half of the cycle and writes
s in the first half

ALU
t Inst 1 IM Reg DM Reg
r.

ALU
O Inst 2 IM Reg DM Reg
r
d

ALU
e add $s2,$s1, IM Reg DM Reg
r

ALU
add $s1, IM Reg DM Reg

ALU
sub $s4,$s1,$s5 IM Reg DM Reg

ALU
and $s6,$s1,$s7 IM Reg DM Reg

ALU
or $s8,$s1,$s9 IM Reg DM Reg

ALU
IM DM Reg
xor $s4,$s1,$s5 Reg

❑ Read before write (data hazard)

The compiler inserts two nops (no operation instruction) before the and instruction
add $s1, $s2, $s3
nop
nop
sub $s4, $s1, $s5
and $s6, $s1, $s7
or $s8, $s1, $s9
xor $s4, $s1, $s5

ALU
I IM Reg DM Reg
n
s
t nops
r.

O nops
r
d
sub $s4,$s1,$s5

ALU
e IM Reg DM Reg
r

ALU
and $s6,$s1,$s7 IM Reg DM Reg

ALU
I add $s1, IM Reg DM Reg
as they are available to
n where they are needed
s

ALU
IM Reg DM Reg
t sub $s4,$s1,$s5
r.

ALU
IM Reg DM Reg
r and $s6,$s1,$s7
d
e

ALU
r IM Reg DM Reg
or $s8,$s1,$s9

ALU
IM Reg DM Reg
xor $s4,$s1,$s5
Ref:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer organization”, Mc Graw Hill, Fifth edition , 2011, ISBN: 9781259005275. Only for internal use. Adarsh Patel, SCAI (SCSE), CSE2003
2. W. Stallings, “Computer organization and architecture: Designing for Performance”, Prentice-Hall, 9th edition, 2013, ISBN: 978-9332518704.
3. David A. Patterson and John L. Hennessy “Computer Organization and Design-The Hardware/Software Interface”, Morgan Kaufmann, 5th edition, 2011.
208
Intrim Semester 2024-25 (04Sep-24Dec-MTE-06-16Nov-TEE-26Dec-11Jan25)
Loads Can Cause Data Hazards
Dependencies backward in time cause hazards

ALU
I lw $s1,4($s2) IM Reg DM Reg
n
s

ALU
t sub $s4,$s1,$s5 IM Reg DM Reg
r.

ALU
O and $s6,$s1,$s7 IM Reg DM Reg
r
d

ALU
e or $s8,$s1,$s9 IM Reg DM Reg
r

ALU
IM DM Reg
xor $s4,$s1,$s5 Reg

❑ Load-use data hazard

beq

ALU
I IM Reg DM Reg
n
s

ALU
t lw IM Reg DM Reg
r.

ALU
O Inst 3 IM Reg DM Reg
r
d

ALU
IM Reg DM Reg
e Inst 4
r

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