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LAB 1 - Introduction To Quartus II Design Software

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LAB 1 - Introduction To Quartus II Design Software

Uploaded by

wiamakif2005
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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LAB 1:-Introduction to Quartus II Design

Software

CEG 2136[C] - Computer Architecture Fall 2024

School of Electrical Engineering and Computer Science


University of Ottawa

Course coordinator: Dr. Fadi Malek


TAs:

Group Number: 25

Students:
Wiam Akif: 300343866
Soukaina Bennasser: 300360203

Experiment dates: 12/09/2024


Submission date: 20/09/2024

Objectives:
This lab experiment aims to:

● Introduce students who are unfamiliar with the Altera Quartus II


Design Software and the Altera FPGA-based DE2-115 platform.
● Serve as a refresher for more advanced students.

Equipment & Components:

°Computer:Used for programming the circuit and running simulations.


°DE2-115 Altera Card:Employed for programming the circuit and
simulating its responses.
°Quartus II 13.0 sp1 ( 64-bit edition on lab computers):Software used for
designing and simulating digital circuits.
Circuit Diagrams:
– Full adder :

Experimental Data and Data Processing:

– Full adder:

Altera Card:
Table 1 : Experimental data observed from MAX 7000
circuit board:

Input Input Input Observed Observed


given given given Output Output
from dip from dip from dip from from
switches switches switches LED’s LED’s

A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Discussion and Conclusion

The objective of this lab was to design and analyze a full adder circuit using basic
logic gates. The circuit was created and simulated using the Quartus-II software on
the Altera DE2-115 board.

In this experiment, we built a full adder using XOR, AND, and OR gates to handle
the binary addition of two bits (A and B) along with a carry-in (Cin). The output of the
full adder includes a sum (S) and a carry-out (Cout), which are used in multi-bit
addition.

After simulating the circuit, the waveform output for all combinations of inputs (A, B,
Cin) was generated. The results were consistent with the expected behavior
according to the truth table of a full adder. The sum output (S) correctly reflected the
modulo-2 addition of A, B, and Cin, while the carry-out (Cout) was high when two or
more of the inputs were high, as expected from the logical combination of the inputs
through the AND and OR gates.

There were no unexpected behaviors, and the simulation accurately demonstrated


the theoretical functioning of a full adder. This successful output shows that the logic
gates were correctly implemented, and the full adder operated as expected in all
cases.

PRE-LAB

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