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MAX77752 Multichannel Integrated Power Management IC

General Description Benefits and Features

The MAX77752 is a highly-integrated power manage- ●● Highly Integrated
ment solution including three step-down converters, • Three Buck Regulators
a low-dropout linear regulator, two external regulators • Integrated High-Accuracy Brownout
enable outputs, two dedicated load switch controllers, Comparators
and an inrush-current limiter which can be configured as • One Low-Dropout Linear Regulator
a third load switch controller using OTP. The MAX77752 • Low-Input Voltage
provides a combination of high-performance power • Two Dedicated Load Switch Controllers
management components, high-accuracy monitoring, • One Inrush-Current Limiter, Configurable to be
and a customized top-level controller that results in an Load Switch 3 Controller Using OTP
efficient, size optimized solution.
• Two External Regulator Enable Outputs
The 40-pin, 5mm x 5mm x 0.8mm, 0.4mm pitch TQFN • Voltage Monitor for Backup Power Control
package is ideal for space constrained applications.
●● Highly Flexible and Configurable
Numerous factory programmable options allow the device • I2C-Compatible Interface
to be tailored for many variations of the end application. • Factory OTP Options Available
• Flexible Power Sequencer
Applications • Configurable Sleep-State Control
●● Solid-State Drive Systems
●● Handheld Devices ●● Small Size
●● Gaming Consoles • 40-Pin, 5mm x 5mm x 0.8mm, 0.4mm Pitch TQFN
●● Drones • 70mm2 Total Solution Size
●● Automation Systems
Ordering Information appears at end of data sheet.
●● Cameras

Simplified Block Diagram

VSYS
RSENSE

INR_OUT SYS INB1

DC SOURCE VSYS VBUCK1
2.6V TO 5.5V 0.6V TO 2.194V
OVERCURRENT LX1
2A MAX
SENSOR
BUCK1
PGND1

LSW3 DRIVER INB2

LSW_DRV3 VSYS VBUCK2
(INRUSH
LX2 0.6V TO 2.194V
FBLSW3 LIMITER)
2A MAX
VLSW3 BUCK2
PGND2
CENTRAL BIAS, INB3
GND TEMP SENSOR, VSYS
VBUCK3
VOLTAGE
LX3 0.26V TO 1.52V
MONITORS
3A MAX
BUCK3
PGND3
LP_MODE
LP_REQ VINLSW1
LP_ACK
LSW_DRV1
PGOOD LSW1 DRIVER
CENTRAL FBLSW1
RESET_L LOGIC VLSW1

WP_L SEQUENCER VINLSW2

EREG_EN1
LOGIC I/O LSW_DRV2
EREG_EN2 LSW2 DRIVER
REGISTERS FBLSW2
EREG_POK VLSW2
AND DIGITAL
IN_PHUP INTERFACE IN_LDO
VSYS
BLD_IO VLDO
SDA OUT_LDO 0.8V TO 3.96V
PMOS LDO 0.15A MAX
SCL

19-100217; Rev 3; 7/18

MAX77752 Multichannel Integrated Power Management IC

Absolute Maximum Ratings

Top Buck
IN_DRV to GND..............................................-0.3V to +16.0V INB1, INB2, INB3 to SYS..................................-0.3V to +0.3V
IN_SNS to GND (Note 1)..................................-0.3V to +6.0V INB1 to PGND1.................................................-0.3V to +6.0V
INR_OUT to GND..............................................-0.3V to +6.0V INB2 to PGND2.................................................-0.3V to +6.0V
SYS to GND......................................................-0.3V to +6.0V INB3 to PGND3.................................................-0.3V to +6.0V
IN_PHUP to GND..............................................-0.3V to +6.0V LX1 to PGND1 (Note 3).......................... -0.3V to VINB1+0.3V
RESET_L to GND..................................... -0.3V to VSYS+0.3V LX2 to PGND2 (Note 3).......................... -0.3V to VINB2+0.3V
LP_REQ to GND...................................... -0.3V to VSYS+0.3V LX3 to PGND3 (Note 3).......................... -0.3V to VINB3+0.3V
LP_ACK to GND....................................... -0.3V to VSYS+0.3V LX1, LX2 RMS Current per pin (TJ = +110°C)
LP_MODE to GND................................... -0.3V to VSYS+0.3V (RMS current per pin (TJ = +110°C))................................1.7A
WP_L to GND (Note 2)....................................-0.3V to VH_INT LX3 RMS Current per pin (TJ = +110°C)
PGOOD to GND (Note 2)................................-0.3V to VH_INT (RMS current per pin (TJ = +110°C))................................3.0A
EREG_EN1 to GND (Note 2)..........................-0.3V to VH_INT FBB1, FBB2, FBB3 to GND..................... -0.3V to VSYS+0.3V
EREG_EN2 to GND............................................-0.3V to 6.0V PGND1, PGND2, PGND3 to GND....................-0.3V to +0.3V
EREG_POK to GND ................................ -0.3V to VSYS+0.3V I2C
BLD_IO to GND (Note 2)..................................-0.3V to +6.0V SDA, SCL to GND......................... -0.3V to VIN_VIO_I2C+0.3V
WP_L Sink Current..........................................................35mA SDA Sink Current............................................................35mA
RESET_L Sink Current....................................................35mA Load Switch
PGOOD Sink Current......................................................35mA LSW_DRV1 to GND........................................-0.3V to +16.0V
EREG_EN1 Sink Current................................................35mA LSW_DRV2 to GND........................................-0.3V to +16.0V
EREG_EN2 Sink Current................................................35mA FBLSW1 to GND...................................... -0.3V to VSYS+0.3V
LP_REQ Sink Current.....................................................35mA FBLSW2 to GND...................................... -0.3V to VSYS+0.3V
DGND to GND...................................................-0.3V to +0.3V Continuous Power Dissipation (Multilayer Board)
LDO TA = +70°C, derate 35.70mW/°C
IN_LDO to GND................................................-0.3V to +6.0V above +70°C............................................... mW to 2857.1mW
OUT_LDO to GND..............................-0.3V to VIN_LDO+0.3V Operating Temperature Range............................ -40°C to +85°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -40°C to +150°C
Soldering Temperature (reflow)........................................+260°C
Note 1: IN_SNS voltage ramp rates greater than 2.8V/μs trigger the internal ESD device and should be avoided. The ESD device
recovers if exposed to an excessive ramp rate.
Note 2: VH_INT is the maximum voltage of VSYS and VIN_PHUP.
Note 3: The specified voltage limitation is for steady state conditions. Dead times of a few nano seconds exist during the dynamic
BUCK regulator transitions from inductor charging to inductor discharging and vice versa. These dead times allow internal
clamping diodes to PGNDx and INBx to forward bias (Vf~1V). When the LXx waveform is observed on a high-bandwidth oscil-
loscope (≥100MHz), the LXx transition edges are commonly seen with 1.5V spikes. These spikes are due to (1) the internal
clamping diode forward voltage and (2) the high rate of current change through the current loop's inductance (V = L x di/dt).
Designs must follow the recommended printed circuit board (PCB) layout in order to minimize this current loop's inductance.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

www.maximintegrated.com Maxim Integrated │ 2

MAX77752 Multichannel Integrated Power Management IC

Package Information
TQFN
PACKAGE CODE T4055+1C
Outline Number 21-0140
Land Pattern Number 90-0016
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θJA) 45°C/W
Junction to Case (θJC) 2°C/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA) 28°C/W
Junction to Case (θJC) 2°C/W

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Electrical Characteristics—Global Resources

(VSYS = 3.6V, VIO = 1.8V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SUPPLY CURRENT

VSYSUVLO < VSYS < VSYS_RESET

(rising), OTP_INT_PU = 1, all regulators
OFF State Quiescent
IQSYS_OFF are disabled. This includes any central 86 135 µA
Current
bias currents disabled (EREG_EN1
pulled to VSYS)

VSYS = 3.3V, VSYS > VSYS_RESET,

OTP_INT_PU = 0, PMIC in DEVSLP
State, Buck2, Buck3, LDO enabled in 70 125
low-power mode. No load on all
regulators. All other regulators disabled
DEVSLP State Quiescent
IQSYS_DEVSLP µA
Current
VSYS = 5V, VSYS > VSYS_RESET,
OTP_INT_PU = 0, PMIC in DEVSLP
state, Buck2, Buck3, LDO enabled in 90 155
low-power mode. No load on all
regulators. All other regulators disabled

VSYS = 5V, VSYS > VSYS_RESET, all

Buck Quiescent Supply
IQSYS_BUCK bucks enabled in normal-power mode 233 420 µA
Current
and skip mode

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Global Resources (continued)

(VSYS = 3.6V, VIO = 1.8V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

BIAS AND REFERENCE CURRENT GENERATOR
Operating Voltage Range VSYS 2.6 5.5 V
Quiescent Supply Current IQCBRG VSYS > VSYSUVLO (rising) 25 µA
Shutdown Supply Current VSYS < VSYSUVLO (falling) 0.1 µA
Bias Enable time tBIASOK 100 µs
POR COMPARATOR (INTERNAL)
Quiescent Supply Current IQSYS_POR 1 µA
POR Undervoltage-Lockout
VPOR VSYS falling 1.33 V
Threshold
POR Threshold Hysteresis VHYS_POR VSYS rising 160 mV
Response Time 100mV overdrive 300 µs
VSYS rising across POR (1V to 2V) 100
POR to UVLO Delay tPORUVLO µs
VSYS falling across POR 50
SYS UNDERVOLTAGE-LOCKOUT COMPARATOR
Quiescent Supply Current IQSYS_UVLO 1 µA
SYS Undervoltage-Lockout
VSYSUVLO VSYS falling 2.00 2.10 2.25 V
Threshold
SYS Undervoltage-Lockout
VINUVLO_HYS 400 mV
Hysteresis
SYS Undervoltage-Lockout
tSYSUVLO 100mV overdrive, falling edge 150 µs
Response Time
SYS RESET COMPARATOR
Quiescent Supply Current IQSYS_RESET 3 µA
Reset Falling Threshold
VSYS_RESET Programmed by SYSRST[3:0] 2650 4150 mV
Range

Reset Threshold Step Size 100 mV

Reset Threshold Hysteresis VSYSRESET_

Programmed by SYSRSTHYS[1:0] 150 300 mV
Range HYS
Reset Threshold Hysteresis
50 mV
Step Size
Reset Comparator
tSYSRESET 5 µs
Response Time
SYSRSTTH[3:0] = 0x0, 0x1, 0x5,
Reset Comparator Accuracy -2.5 +2.5 %
0xA, 0xF

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Global Resources (continued)

(VSYS = 3.6V, VIO = 1.8V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SYS BROWNOUT COMPARATOR
Brownout Falling Threshold
VSYS_BO Programmed by SYSBOTH[3:0] 2800 4300 mV
Range
Brownout Threshold Step
100 mV
Size
Brownout Threshold
VSYS_BO_HYS Programmed by SYSBOHYS[1:0] 150 300 mV
Hysteresis Range
Brownout Threshold
50 mV
Hysteresis Step Size
SYS_BO_PR[1:0] = 0b00 (fast),
PMIC not in DEVSLP state, 100mV
1.04
under-drive with falling slew rate of
150mV/μs

SYS_BO_PR[1:0] = 0b01 (med-fast),

PMIC not in DEVSLP state, 100mV
1.14
under-drive with falling slew rate of
Brownout Comparator 150mV/μs
tSYSBO μs
Response Time SYS_BO_PR[1:0] = 0b10 (med-slow),
PMIC not in DEVSLP state, 100mV
1.30
under-drive with falling slew rate of
150mV/μs

SYS_BO_PR[1:0] = 0b11 (slow),

PMIC not in DEVSLP state, 100mV
1.68
under-drive with falling slew rate of
150mV/μs
Brownout Comparator PMIC in DEVSLP state, 100mV under-
tSYSBO 3.53 μs
Response Time (DEVSLP) drive with falling slew rate of 150mV/μs
SYS_BO_PR[1:0] = 0b00 (fast), PMIC
13.4
not in DEVSLP state
SYS_BO_PR[1:0] = 0b01 (med-fast),
10.4
PMIC not in DEVSLP state
Quiescent Supply Current IQSYS_BO µA
SYS_BO_PR[1:0] = 0b10 (med-slow),
7.4
PMIC not in DEVSLP state
SYS_BO_PR[1:0] = 0b11 (slow),
4.4
PMIC not in DEVSLP state
Quiescent Supply Current
IQSYS_BO PMIC in DEVSLP state 1.3 µA
(DEVSLP)
Brownout Comparator SYSBO[3:0] = 0x0, 0x1, 0x5, 0xA, 0xF,
-2.5 +2.5 %
Accuracy PMIC is not in DEVSLP state
Brownout Comparator SYSBO[3:0] = 0x0, 0x1, 0x5, 0xA, 0xF,
-2.5 +2.5 %
Accuracy (DEVSLP) PMIC is in DEVSLP state
Brownout Timer Period tBO T_BO_EN = 1 100 ms

www.maximintegrated.com Maxim Integrated │ 5

MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Global Resources (continued)

(VSYS = 3.6V, VIO = 1.8V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OSCILLATOR
Clock Frequency CLK32K VSYS = 5V 31.5 kHz
VSYS = 3.3V -10 +10
Oscillator Tolerance %
VSYS = 5V -10 +10
WP_L OUTPUT (OPEN DRAIN)
WP_L Output-Voltage Low VOL ISINK = 2mA 0.4 V
VSYS = VWP_L = 5.5V, TA = +25°C,
0.001 1
WP_L Open Leakage OTP_INT_PU[0] = 0b0
μA
Current VSYS = VWP_L = 5.5V, TA = +85°C,
0.01
OTP_INT_PU[0] = 0b0
WP_L Falling Edge Time CWP_L = 25pF, VWP_L = 1.8V ≥ 0 25 ns
WP_L_DLY[1:0] = 0b00
0
(based on an internal 31.5kHz clock)
WP_L_DLY[1:0] = 0b01 (based on an
254
WP_L Output Deassert internal 31.5kHz clock)
tWPDLY µs
Delay Time WP_L_DLY[1:0] = 0b10
508
(based on an internal 31.5kHz clock)
WP_L_DLY[1:0] = 0b11
1016
(based on an internal 31.5kHz clock)
WP_L Output Assert
0 µs
Delay Time
Pulled up to VIN_VIO,
WP_L Pullup Resistance RPU_WP_L 50 100 170 kΩ
OTP_INT_PU[0] = 0b1
RESET_L OUTPUT (OPEN DRAIN)
RESET_L Output-Voltage
VOL ISINK = 2mA 0.4 V
Low
VSYS = VRESET_L = 5.5V, TA = +25°C,
0.001 1
RESET_L Open Leakage OTP_INT_PU[0] = 0b0
μA
Current VSYS = VRESET_L = 5.5V, TA = +85°C,
0.01
OTP_INT_PU[0] = 0b0
RESET_L Falling Edge CRESET_L = 25pF, VRESET_L falling
25 ns
Time from 1.8V ≥ 0

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Global Resources (continued)

(VSYS = 3.6V, VIO = 1.8V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

RST_L_DLY[1:0] = 0b00
0
(based on an internal 31.5kHz clock)
RST_L_DLY[1:0] = 0b01
254
RESET_L Output Deassert (based on an internal 31.5kHz clock)
tRSTDLY µs
Delay Time RST_L_DLY[1:0] = 0b10
508
(based on an internal 31.5kHz clock)
RST_L_DLY[1:0] = 0b11
1016
(based on an internal 31.5kHz clock)
RESET_L Output Assert
0 µs
Delay Time
RESET_L Pullup Pulled up to VIN_VIO,
RPU_RESET_L 50 100 170 kΩ
Resistance OTP_INT_PU[0] = 0b1
PGOOD OUTPUT (OPEN DRAIN)
PGOOD Output-Voltage
VOL ISINK = 2mA 0.4 V
Low
VSYS = VPGOOD = 5.5V, TA = +25°C,
0.001 1
PGOOD Open Leakage OTP_INT_PU[0] = 0b0
μA
Current VSYS = VPGOOD = 5.5V, TA = +85°C,
0.01
OTP_INT_PU[0] = 0b0
PGOOD Falling Edge Time CPGOOD = 25pF, VPGOOD = 1.8V ≥ 0 25 ns
PG_DLY[1:0] = 0b00
31.5
(based on an internal 31.5kHz clock)
PG_DLY[1:0] = 0b01
254
PGOOD Output Assert (based on an internal 31.5kHz clock)
tPGOODDLY µs
Delay Time PG_DLY[1:0] = 0b10
508
(based on an internal 31.5kHz clock)
PG_DLY[1:0] = 0b11
1016
(based on an internal 31.5kHz clock)
PGOOD Output Deassert
0 µs
Delay Time
Pulled up to VIN_VIO, OTP_INT_PU[0]
PGOOD Pullup Resistance RPU_PGOOD 50 100 170 kΩ
= 0b1

www.maximintegrated.com Maxim Integrated │ 7

MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Global Resources (continued)

(VSYS = 3.6V, VIO = 1.8V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

LP_MODE INPUT
LP_MODE I/O Pad
VSYS 2.6 5.5 V
Operating Voltage
LP_MODE Input-Low
VIL 0.4 V
Voltage
LP_MODE Input-High
VIH 1.4 V
Voltage
LP_MODE Input Hysteresis VHYS 50 mV
VSYS = VIN_VIO = 5.5V,
0.001 1
LP_MODE Input Leakage VLP_MODE = 0V and 5.5V, TA = +25°C
µA
Current VSYS = VIN_VIO = 5.5V,
0.01
VLP_MODE = 0V and 5.5V, TA = +85°C

Debounce applies to rising and falling

LP_MODE Debounce tLPMD_DBNC edge. Does not account for oscillator 95 127 μs
tolerance (Note 4)

LP_MODE I/O Pad

VSYSUVLO VSYS falling 2.1 V
Undervoltage Lockout
LP_MODE Mask
tLPMD_MSK 16 20 25 ms
Deassertion Timer
LP_ACK INPUT
I/O Pad Operating Voltage VSYS 2.6 5.5 V
Input Low Voltage VIL 0.4 V
Input High Voltage VIH 1.4 V
Input Hysteresis VHYS 50 mV
VSYS = 5.5V, VLP_ACK = 0V and 5.5V,
0.001 1
TA = +25°C, OTP_INT_PU[0] = 0b0
Input Leakage Current µA
VSYS = 5.5V, VLP_ACK = 0V and 5.5V,
0.01
TA = +85°C, OTP_INT_PU[0] = 0b0
Pulled up to VIN_VIO,
LP_ACK Pullup Resistance RPU_LP_ACK 50 100 170 kΩ
OTP_INT_PU[0] = 0b1

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Global Resources (continued)

(VSYS = 3.6V, VIO = 1.8V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

LP_REQ OUTPUT (OPEN DRAIN)
LP_REQ Output Voltage
VOL ISINK = 2mA 0.4 V
Low
VSYS = VLP_REQ = 5.5V, TA = +25°C,
0.001 1
LP_REQ Open Leakage OTP_INT_PU[0] = 0b0
μA
Current VSYS = VLP_REQ = 5.5V, TA = +85°C,
0.01
OTP_INT_PU[0] = 0b0
LP_REQ Falling Edge Time CLP_REQ = 25pF, VLP_REQ = 1.8V ≥ 0 25 ns

LP_REQ_T_EN = 0, PMIC in master

mode (OTP_SLP_MSTRSLV = 0), 31.75 μs
applies during DevSlp exit sequence
LP_REQ Delay tLPREQ_LOW
LP_REQ_T_EN = 1, PMIC in master
mode (OTP_SLP_MSTRSLV = 0), 20 ms
applies during DevSlp exit sequence

Pulled up to VIN_VIO,
LP_REQ Pullup Resistance RPU_LP_REQ 50 100 170 kΩ
OTP_INT_PU[0] = 0b1
EREG_ENx OUTPUT (OPEN DRAIN)
EREG_EN1 Output-Voltage
VOL ISINK = 2mA 0.4 V
Low
EREG_EN2 Output-Voltage
VOL ISINK = 10mA 0.4 V
Low
VSYS = VEREG_ENx = 5.5V, TA = +25°C,
0.001 1
EREG_ENx Open OTP_INT_PU[0] = 0b0
μA
Leakage Current VSYS = VEREG_ENx = 5.5V, TA = +85°C,
0.01
OTP_INT_PU[0] = 0b0
EREG_ENx Falling Edge CEREG_ENx = 25pF, VEREG_ENx = 1.8V
25 ns
Time ≥0
EREG_EN1 Pullup RPU_EREG_ Pulled up to VH_INT, OTP_INT_PU[0]
50 100 170 kΩ
Resistance ENx = 0b1
EREG_EN2 Pullup RPU_EREG_ Pulled up to VIN_VIO, OTP_INT_PU[0]
50 100 170 kΩ
Resistance ENx = 0b1
EREG_POK INPUT
I/O Pad Operating Voltage VSYS 2.6 5.5 V
Input Low Voltage VIL 0.4 V
Input High Voltage VIH 1.4 V
Input Hysteresis VHYS 50 mV

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Global Resources (continued)

(VSYS = 3.6V, VIO = 1.8V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VSYS = 5.5V, VEREG_POK = 0V

and 5.5V, TA = +25°C, 0.001 1
OTP_INT_PU[0] = 0b0
Input Leakage Current µA
VSYS = 5.5V, VEREG_POK = 0V
and 5.5V, TA = +85°C, 0.01
OTP_INT_PU[0] = 0b0
EREG_POK Pullup RPU_EREG_ Pulled up to VIN_VIO,
50 100 170 kΩ
Resistance POK OTP_INT_PU[0] = 0b1
THERMAL MONITORS
Quiescent Supply Current IQTM 1.5 µA
Shutdown Supply Current 0.1 µA
Thermal Overload TJOVLD TJ rising, 15°C hysteresis 165 °C
Response Time 5°C overdrive 10 µs
FLEXIBLE POWER SEQUENCER
Measured from internal FPSxEN =
Power-Up Sequence
tFPSDON 1 to start of sequence 63.492 μs
Enable Delay
(based on a 31.5kHz clock)
Measured from internal FPSxEN =
Power-Down Sequence
tFPSDOFF 0 to start of sequence 95.240 μs
Enable Delay
(based on a 31.5kHz clock)
MSTRxUPF[2:0] =
31
MSTRxDNF[2:0] = 0b000
MSTRxUPF[2:0] =
63
MSTRxDNF[2:0] = 0b001
MSTRxUPF[2:0] =
127
MSTRxDNF[2:0] = 0b010
MSTRxUPF[2:0] =
253
Flexible Power Sequencer tFPS_PU, MSTRxDNF[2:0] = 0b011
µs
Event Period tFPS_PD MSTRxUPF[2:0] =
508
MSTRxDNF[2:0] = 0b100
MSTRxUPF[2:0] =
984
MSTRxDNF[2:0] = 0b101
MSTRxUPF[2:0] =
1936
MSTRxDNF[2:0] = 0b110
MSTRxUPF[2:0] =
3904
MSTRxDNF[2:0] = 0b111

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Global Resources (continued)

(VSYS = 3.6V, VIO = 1.8V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PD_DLY[1:0] = 0b00 0

Power-Down Sequence PD_DLY[1:0] = 0b01 1.0

tPD_DLY ms
Delay PD_DLY[1:0] = 0b10 1.5
PD_DLY[1:0] = 0b11 2.0
BLD_IO
Maximum Bleed Time tBLEED_MAX 20 22 ms
Minimum Bleed Time tBLEED_MIN 31.5 μs
Bleed Threshold BLD_IO falling 90 100 mV
Bleed Resistance RBLEED BLD_IO = 0.3V 20 27 Ω
VSYS = 5.5V, VBLD_IO = 0V and 5.5V,
0.01
BLD_IO Input Leakage TA = +85°C
µA
Current VSYS = 5.5V, VBLD_IO = 0V and 5.5V,
0.001 1
TA = +25°C
ON/OFF CONTROLLER
HICCUP_
Hiccup Counter Limit 7 counts
CNT_LIM
IN_PHUP
Operating Voltage Range VIN_PHUP 2.4 5.5 V
IN_PHUP Supply Current IIN_PHUP VSYS = VIN_PHUP = 5.5V, TA = +25°C 5.0 µA

Note 4: The LP_MODE debounce period has a variation due to the variability associated with quantizing an asynchronous input sig-
nal. Additionally, while measuring the period from a valid LP_MODE edge to a subsequent event, such as LP_REQ asser-
tion, there is one more clock cycle (CLK32K) of delay observed in a real system.

www.maximintegrated.com Maxim Integrated │ 11

MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Inrush Control

(VIN_SNS = 5.0V, limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range
are guaranteed by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLY
Supply Voltage Range VIN 2.1 5.5 V
IN Undervoltage-Lockout
VINUVLO VIN rising 2.3 2.55 V
Threshold
IN Undervoltage-Lockout
VINUVLO_HYS 200 mV
Hysteresis
IN Undervoltage-Lockout
tINUVLO VIN rising (VIN = VINUVLO + 100mV) 39 µs
Response Time
IN Overvoltage-Lockout
VINOVLO VIN rising 5.70 5.87 6.10 V
Threshold
IN Overvoltage-Lockout
VINOVLO_HYS 80 mV
Hysteresis
IN Overvoltage-Lockout
tINOVLO VIN rising (VIN = VINOVLO + 50mV) 8 µs
Response Time
VIN = 5.5V, VIN_DRV = 0V and 11V,
0.001 1
TA = +25°C
Leakage ILKG_VIN_DRV µA
VIN = 5.5V, VIN_DRV = 0V and 11V ,
0.01
TA = +85°C
VIN_DRV-VINR_OUT < VIN_SNS (soft-
start state), OTP_GDRV_FREQ = 85
0b111 (800kHz), VIN_SNS = 3.3V
Supply Current (Soft-Start) IQ_IN_SS µA
VIN_DRV-VINR_OUT < VIN_SNS
(soft-start state), OTP_GDRV_FREQ = 138
0b111 (800kHz), VIN_SNS = 5V

VIN_DRV-VINR_OUT = VIN_SNS
(steady state), tSS_DONE expired, 26
Supply Current (Steady- fGDRV = 12.5kHz, VIN_SNS = 3.3V
IIN µA
State) VIN_DRV-VINR_OUT = VIN_SNS
(steady state), tSS_DONE expired, 37
fGDRV = 12.5kHz, VIN_SNS = 5V

NMOS SWITCH DRIVER

Voltage with respect to

ground when external
Gate Drive ON Voltage VIN_DRV_ON VIN = 5V 8.5 11 V
MOSFET is being driven to
it's fully ON state

VIN = 3.3V, 1X gate drive frequency

Gate Drive Current IGDRV_INRUSH 1.8 3.0 4.2 µA
setting
4x Gate Drive Oscillator OTP_INR_FREQ[2:0] = 0b111,
fGDRV_4X 720 kHz
Frequency VIN = 3.3V, VIN = 5V

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Inrush Control (continued)

(VIN_SNS = 5.0V, limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range
are guaranteed by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

2x Gate Drive Oscillator OTP_INR_FREQ[2:0] = 0b110,
fGDRV_2X 360 kHz
Frequency VIN = 3.3V, VIN = 5V

OTP_INR_FREQ[2:0] = 0b101
1x Gate Drive Oscillator
fGDRV_1X (nominal gate drive strength), 120 180 240 kHz
Frequency
VIN = 3.3V, VIN = 5V

0.5x Gate Drive Oscillator OTP_INR_FREQ[2:0] = 0b100,

fGDRV_0.5X 90 kHz
Frequency VIN = 3.3V, VIN = 5V
0.25x Gate Drive Oscillator OTP_INR_FREQ[2:0] = 0b011,
fGDRV_0.25X 45 kHz
Frequency VIN = 3.3V, VIN = 5V
0.125x Gate Drive Oscillator OTP_INR_FREQ[2:0] = 0b010,
fGDRV_0.125X 15 23 32 kHz
Frequency VIN = 3.3V, VIN = 5V
0.0625x Gate Drive Oscilla- OTP_INR_FREQ[2:0] = 0b001,
fGDRV_0.0625X 11.25 kHz
tor Frequency VIN = 3.3V, VIN = 5V
0.03125x Gate Drive Oscil- OTP_INR_FREQ[2:0] = 0b000,
fGDRV_0.03125X 5.625 kHz
lator Frequency VIN = 3.3V, VIN = 5V
Resistance from INR_DRV to
74
Gate Drive Discharge INR_OUT, VINR_DRV-INR_OUT = 4V
RGDRV_DIS Ω
Resistance Resistance from INR_DRV to
100
INR_OUT, VINR_DRV-INR_OUT = 3.3V
TIMING
Time from VIN rising above VINUVLO
to the internal charge pump being
cycles of
Start-Up Delay tEN_INRUSH enabled. Duration is based on the 128
fGDRV
gate drive oscillator frequency (fGDRV)
selected by OTP_INR_FREQ[2:0]

Duration from MOSFET drive

circuit being enabled (subsequent to
startup delay) to the point when the
IN_SS_DONE (internal signal) is cycles of
Soft-Start Done Time tSS_1 512
asserted allowing a power-up fGDRV
sequence to occur. Based on default
gate drive frequency (fGDRV) selected
by OTP_INR_FREQ[2:0]

Duration from MOSFET drive circuit

being enabled (subsequent to the
startup delay) to the point when the
gate drive oscillator frequency folds cycles of
Gate Drive Idle Time tSS_DONE 1024
back to the 12.5kHz setting (idle gate fGDRV
drive). Based on default gate drive
frequency (fGDRV) selected by
OTP_INR_FREQ[2:0]

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Current Sense Amplifier

(VSYS = 3.3V, CLOAD = 10pF, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range
and relevant supply voltage range are guaranteed by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

INPUT OVERCURRENT
Input Overcurrent Threshold 2.25A setting, VSYS = 3.3V -6.5 +6.5 %
OTP_CSA_DBNC = 0 100
CSA Debounce Timer μs
OTP_CSA_DBNC = 1 50
Overcurrent-Sense Overcurrent limit,
VOC_THR 30 mV
Comparator Threshold 1 CSTH_OPT[1:0] = 0b00
Overcurrent-Sense Overcurrent limit,
VOC_THR 35 mV
Comparator Threshold 2 CSTH_OPT[1:0] = 0b01
Overcurrent-Sense Overcurrent-limit,
VOC_THR 40 mV
Comparator Threshold 3 CSTH_OPT[1:0] = 0b10
Overcurrent-Sense Overcurrent limit,
VOC_THR 45 mV
Comparator Threshold 4 CSTH_OPT[1:0] = 0b11

Electrical Characteristics—Buck Regulators (BUCK1/2 - 2A Output)

(VSYS = 3.6V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range are guaranteed
by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SUPPLY VOLTAGE AND CURRENT
Input Voltage Range VINBx 2.6 5.5 V
Shutdown Supply Current IQSHDN_BUCKx (Note 5) 0.1 µA
No switching, no load, (Note 6),
19 30
IQ_SKIP_NM_ VSYS = 3.3V
µA
BUCKx No switching, no load, (Note 6),
19 30
VSYS = 5V
FPWM mode (switching at fixed
10
IQ_FPWM_ frequency), no load, VSYS = 3.3V
Supply Quiescent Current mA
BUCKx FPWM mode (switching at fixed
10
frequency), no load, VSYS = 5V
Low-power mode (no switching),
5 9
IQ_SKIP_LPM_ no load, (Note 6), VSYS = 3.3V
µA
BUCKx Low-power mode (no switching),
5 9
no load, (Note 6), VSYS = 5V

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Buck Regulators (BUCK1/2 - 2A Output) (continued)

(VSYS = 3.6V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range are guaranteed
by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OUTPUT VOLTAGE

Programmable in 6.25mV steps with

Output Voltage Range VOUT_BUCKx BUCK1VOUT[7:0] and 0.600 2.194 V
BUCK2VOUT[7:0]

VOUT_ACC_NM_ FPWM mode, normal mode,

-2 +2
BUCKx no load, VOUT_BUCK1 = 1.800V
VOUT_ACC_ Low-power mode, no load,
-4 +4
LPM_BUCKx VOUT_BUCK1 = 1.800V
Output Voltage Accuracy %
VOUT_ACC_NM_ FPWM mode, normal mode,
-2 +2
BUCKx no load, VOUT_BUCK2 = 1.200V
VOUT_ACC_ Low-power mode, no load,
-4 +4
LPM_BUCKx VOUT_BUCK2 = 1.200V
OUTPUT CURRENT
IOUT_MAX_
RMS, normal mode, L = 1μH 2000
NM_BUCKx
Maximum Output Current mA
IOUT_MAX_
RMS, low-power mode, L = 1μH 10
LPM_BUCKx
VSYS = 3.6V 2300 2875 4200
PMOS Peak Current Limit ILIMP mA
VSYS = 5V 2300 2875 4200
VSYS = 3.6V 2125
NMOS Valley Current Limit ILIMV mA
VSYS = 5V 2125

NMOS Negative Current VSYS = 3.6V 800

ILIMN mA
Limit VSYS = 5V 800
PERFORMANCE PARAMETERS
Line Regulation VSYS = VINBx = 2.6V to 5.5V 0.2 %/V
Load Regulation Load = 0 to 1A, FPWM mode 0.125 %/A

FPWM mode, VOUT_BUCKx = default,

L = 1μH, COUT = 12μF effective 88
∆ IOUT = 0.2A–2A, ∆t = 3μs
Load Transient Response mV
Skip mode, VOUT_BUCKx = default,
L = 1μH, COUT = 12μF effective 90
∆ IOUT = 10mA to 0.7A, ∆t = 3μs,

Switching Frequency fSW VSYS = 3.3V 1.8 2 2.2 MHz

Dead Time tDEAD VSYS = 3.3V 2.0 ns
Switching Frequency fSW VSYS = 5V 1.8 2 2.2 MHz

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Buck Regulators (BUCK1/2 - 2A Output) (continued)

(VSYS = 3.6V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range are guaranteed
by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Dead Time tDEAD VSYS = 5V 2.0 ns
Fixed for buck 1 6.5
Soft-Start Slew Rate mV/µs
Fixed for buck 2 17
Output Voltage Ramp-Up Fixed for buckx (Notes 5, 8, 9),
40 mV/µs
Slew Rate COUT = 22μF

Fixed for buck 1, 2 (Notes 5, 8),

Output Voltage Ramp-Down
COUT = 22μF, BUCKxFPWMEN = 1 18 mV/µs
Slew Rate
(x = 1, 2), no load

VSYS = VINBUCKx = 3.6V,

100 150
IOUT = 150mA
PMOS ON Resistance RON_PCH mΩ
VSYS = VINBUCKx = 5V,
100 150
IOUT = 150mA
VSYS = VINBUCKx = 3.6V,
60 100
IOUT = 150mA
NMOS ON Resistance RON_NCH mΩ
VSYS = VINBUCKx = 5V,
60 100
IOUT = 150mA
NMOS Zero-Crossing Threshold to determine transition from
IZX 20 mA
Threshold PWM to SKIP mode

VOUT_BUCKx = 1.0V, L = 1μH,

Output Voltage Ripple in
COUT = 12μF effective, no load 40 mVP-P
Skip Mode
(Note 5)

VOUT_BUCKx = 1.0V, L = 1μH,

Output Voltage Ripple in COUT = 12μF effective,
5 mVP-P
PWM Mode ILOAD = 0.5 x IOUT_MAX_BUCKx
(Note 5)

IL_LX_25C VLXx = 5.5V or 0V, TA = +25°C 0.1 1

LX Leakage VLXx = 5.5V or 0V, TA = +85°C µA
IL_LX_85C 1
(Note 5)
Output Active Discharge RDISCHG_ Resistance from FBBx to PGNDx,
100 Ω
Resistance BUCKx output disabled, (Note 7)
Nominal Output Inductance LNOM 1.0 µH
Minimum Effective Output
COUT_EFF_MIN 0mA < IOUT < 2000mA 18 µF
Capacitance

Low-power mode, IOUT = 0.5mA,

VOUT_BUCKx = 1.0V, L = 1μH,
Light Load Efficiency EffLIGHT 75 %
DCRL = 50mΩ, COUT = 22μF
(Note 5)

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Buck Regulators (BUCK1/2 - 2A Output) (continued)

(VSYS = 3.6V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range are guaranteed
by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IOUT = 0.25 x IOUT_MAX_BUCKx,

Typical Load Efficiency EffIOUT_TYP VOUT_BUCKx = 1.0V, L = 1μH, 85 %
DCRL = 50mΩ, COUT = 22μF (Note 5)

IOUT = IOUT_MAX_BUCKx,
VOUT = 1.0V, L = 1μH,
Maximum Load Efficiency EFFIOUT_MAX 70 %
DCRL = 50mΩ, COUT = 22μF
(Note 5)

EN signal to LX switching with

Turn-On Delay Time tON_DLY_BUCKx 30 µs
bias ON
VOUT_BUCKx / VIN_BUCKx
Maximum Duty Cycle 90 %
expressed as %
BROWNOUT COMPARATOR
Normal-power mode, falling threshold,
75
BUCKx_BO_THR[1:0] = 0b00
Normal-power mode, falling threshold,
80
Output Brownout BUCKx_BO_THR[1:0] = 0b01
VBO_BUCKx %
Threshold Normal-power mode, falling threshold,
85
BUCKx_BO_THR[1:0] = 0b10
Normal-power mode, falling threshold,
90.7
BUCKx_BO_THR[1:0] = 0b11

Normal-power mode.
Output Brownout
VOUT_BUCKx = 1.0V -4.0 +4.0 %
Accuracy
(VOUT_BUCKx[7:0] = 0 x 40)

Output Brownout Threshold

VBO_BUCKx Falling threshold, low-power mode 86.0 %
(Low-Power Mode)
Low-power mode. VOUT_BUCKx = 1.0V
Output Brownout Accuracy -4 +4 %
(VOUT_BUCKx[7:0] = 0 x 40)
Output Brownout Hysteresis VBO_HYS_ 2-bit control over I2C. Max rising
5 20 %
Range BUCKx threshold limited to 96%
Brownout Voltage Hystere- Programmable with
5 %
sis Programming Step Size BUCKx_BO_HYS[1:0]
Output Brownout Hysteresis VBO_HYS_
5 %
(Low-Power Mode) BUCKx_LPM

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Buck Regulators (BUCK1/2 - 2A Output) (continued)

(VSYS = 3.6V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range are guaranteed
by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

BUCKx_BO_PR[1:0] = 0b00 (fast),

buck in normal-power mode, 100mV
under-drive with falling slew rate of 1.04
150mV/μs. Time from VOUT_BUCKx
falling to PGOOD pin falling

BUCKx_BO_PR[1:0] = 0b01 (med-

fast), buck in normal-power mode,
100mV under-drive with falling slew 1.14
rate of 150mV/μs. Time from VOUT_
BUCKx falling to PGOOD pin falling

BUCKx_BO_PR[1:0] = 0b10 (med-

Output Brownout Response slow), buck in normal-power mode,
tBO_BUCKx μs
Time 100mV under-drive with falling slew 1.30
rate of 150mV/μs. Time from VOUT_
BUCKx falling to PGOOD pin falling

BUCKx_BO_PR[1:0] = 0b11 (slow),

buck in normal-power mode, 100mV
under-drive with falling slew rate of 1.68
150mV/μs. Time from VOUT_BUCKx
falling to PGOOD pin falling

Buck in low-power mode, 100mV

under-drive with falling slew rate of
3.18
150mV/μs. Time from VOUT_BUCKx
falling to PGOOD pin falling

Normal-power mode,
13.4
BUCKx_BO_PR[1:0] = 0b00 (fast)
Normal-power mode,
10.4
IQNM_BO_ BUCKx_BO_PR[1:0] = 0b01 (med-fast)
Output Brownout Supply BUCKx Normal-power mode,
7.4 µA
Current BUCKx_BO_PR[1:0] = 0b10 (med-slow)
Normal-power mode,
4.4
BUCKx_BO_PR[1:0] = 0b11 (slow)
IQLPM_BO_
Low-power mode 1.3
BUCKx

www.maximintegrated.com Maxim Integrated │ 18

MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Buck Regulators (BUCK1/2 - 2A Output) (continued)

(VSYS = 3.6V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range are guaranteed
by design and characterization.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OV COMPARATOR
Rising edge, BUCKx_OV_THR = 1,
Output OV Trip Level VOUTBUCKx_OV 116.6 %
referenced to output voltage setting
Output OV Hysteresis BUCKx_OV_THR = 1 9.1 %
Rising edge, BUCKx_OV_THR = 0,
Output OV Trip Level VOUTBUCKx_OV 108.3 %
referenced to output voltage setting
Output OV Hysteresis BUCKx_OV_THR = 0 2.8 %
Output OV Trip Level
VOUTBUCKx_OV Rising edge, low-power mode 108.3 %
(Low-Power Mode)
Output OV hysteresis
Low-power mode 2.8 %
(Low-Power Mode)

Normal-power mode, 100mV over-

Output Over-Voltage drive with rising slew rate of 150mV/
tOV_BUCKx 1.68 μs
Response Time μs. Time from VOUT_BUCKx rising to
PGOOD pin falling (Note 5)

Output Over-Voltage
IQ_OV_BUCKx Normal-power mode 4.4 µA
Supply current

Low-power mode, 100mV over-drive

Output Over-Voltage
with rising slew rate of 150mV/μs.
Response Time tOV_BUCKx 3.18 μs
Time from VOUT_BUCKx rising to
(Low-Power Mode)
PGOOD pin falling (Note 5)

Output Over-Voltage Supply

IQ_OV_BUCKx Low-power mode 1.3 µA
Current (Low-Power Mode)

Note 5: Design guidance only and is not production tested.

Note 6: Individual buck Iq is not production tested. It is covered by a combined test by turning on all bucks.
Note 7: There is an n-channel MOSFET in series with the output active-discharge resistance. This NMOS requires VSYS > 1.2V to
be enhanced.
Note 8: The ramp down slew rate when the output voltage is decreased through I2C is a function of the negative current limit and
the output capacitance. With no load, forced PWM mode and 22μF output capacitor, the ramp-down slew rate is
dv/dt = i / C = 0.4A / 22μF = 18mV/μs.
Note 9: DVS and soft-start ramp rates can be expected to vary by up to 30%.

www.maximintegrated.com Maxim Integrated │ 19

MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Buck Regulators (BUCK3 - 3A Output)

(VSYS = 5.0V, TA = -40°C to +85°C, Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant
supply voltage range are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not
production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SUPPLY VOLTAGE AND CURRENT
Input Voltage Range VINBUCK3 2.6 5.5 V
Shutdown Supply IQSHDN_
(Note 10) 0.1 µA
Current BUCK3
IQ_SKIP_NM_
No switching, no load (Note 10) 26 40 µA
BUCK3
Supply Quiescent IQ_FPWM_
FPWM mode, no load (Note 10) 10 mA
Current BUCK3
IQ_SKIP_LPM_ Low-power mode (no switching),
10 19 µA
BUCK3 no load (Note 10)
OUTPUT VOLTAGE
I2C programmable in 10mV Steps
Output Voltage Range VOUT_BUCK3 0.26 1.52 V
(BUCK3VOUT[6:0] = 0x01 to 0x7F)

VOUT_ACC_ FPWM mode, normal mode, no load,

-2 +2
NM_BUCK3 TA = +25°C, VOUT_BUCK3 = 1.0V
Output Voltage Accuracy %
VOUT_ACC_ Low-power mode, no load, TA = +25°C,
-4 +4
LPM_BUCK3 VOUT_BUCK3 = 1.000V
PERFORMANCE PARAMETERS
VSYS = 3.3V 1.8 2 2.2
Switching Frequency fSW MHz
VSYS = 5V 1.8 2 2.2
VINBUCK3 = 2.6V to 5.5V,
Line Regulation 0.2 %/V
VOUT_BUCK3 = 1.0V
VOUT_BUCK3 = 1.0V, (Note 10),
Load Regulation 0.125 %/A
load = 0 to 1A, FPWM mode

Skip mode, VOUT = default, L = 1μH,

COUT = 28μF effective
45
∆IOUT = 20mA to 500mA, ∆t = 0.8μs
Load Transient Re- (Note 10) mV
sponse (Droop)
Skip mode, VOUT = default, L = 1μH,
COUT = 28μF effective 70
∆IOUT = 20mA to 3A, ∆t = 4.8μs (Note 10)
BUCK3SSRAMP = 0 2.5
Soft-Start Slew Rate mV/µs
BUCK3SSRAMP = 1 10
Output Voltage
Ramp-Up/Down Slew 10 mV/µs
Rate (DVS)

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Buck Regulators (BUCK3 - 3A Output) (continued)

(VSYS = 5.0V, TA = -40°C to +85°C, Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant
supply voltage range are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not
production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VSYS = VINBUCK3 = 5V, IOUT = 150mA 60 90
PMOS ON Resistance RON_PCH mΩ
VSYS = VINBUCK3 = 3.6V, IOUT = 150mA 60 90
VSYS = VINBUCK3 = 5V, IOUT = 150mA 35 60
NMOS ON Resistance RON_NCH mΩ
VSYS = VINBUCK3 = 3.6V, IOUT = 150mA 35 60

NMOS Zero-Crossing IZX_SKIP SKIP mode 20

mA
Threshold IZX_PWM PWM mode 20
Output Voltage Ripple In VOUT_BUCK3 = 1.0V, L = 1μH,
15 mV
Skip Mode COUT = 28μF effective, no load (Note 10)

VOUT_BUCK3 = 1.0V, L = 1μH,

Output Voltage Ripple In
COUT = 28μF effective, 5 mV
PWM Mode
ILOAD = 0.5 x IOUT_MAX_BUCK3 (Note 10)

IL_LX_25C VLXBUCK1 = 5.5V or 0V, TA = +25°C 0.1 1

LX Leakage VLXBUCK1 = 5.5V or 0V, TA = +85°C µA
IL_LX_85C 1
(Note 10)
Output Active Discharge RDISCHG_ Resistance from FBB3 to PGND3,
100 Ω
Resistance BUCK3 output disabled
Nominal Output
LNOM 1.0 µH
Inductance
Minimum Effective COUT_EFF_
0mA < IOUT < 3000mA 28 µF
Output Capacitance MIN
tON_DLY_
Turn-On Delay Time EN signal to LX switching with bias ON 200 µs
BUCK1
Low-power mode, IOUT = 0.5mA,
Light Load Efficiency EffLIGHT VOUT_BUCKx = 1.0V, L = 1μH, 75 %
DCRL = 50mΩ, COUT = 3 x 22μF (Note 10)
IOUT = 0.25 x IOUT_MAX_BUCKx,
Typical Load Efficiency EffIOUT_TYP VOUT_BUCKx = 1.0V, L = 1μH, 88 %
DCRL = 50mΩ, COUT = 3 x 22μF (Note 10)
IOUT = IOUT_MAX_BUCKx, VOUT = 1.0V,
Maximum Load
EFFIOUT_MAX L = 1μH, DCRL = 50mΩ, COUT = 3 x 22μF 77 %
Efficiency
(Note 10)

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Buck Regulators (BUCK3 - 3A Output) (continued)

(VSYS = 5.0V, TA = -40°C to +85°C, Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant
supply voltage range are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not
production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OUTPUT CURRENT
IOUT_MAX_
RMS, normal mode 3000
Maximum Output NM_BUCK3
mA
Current IOUT_MAX_
RMS, low-power mode 10
LPM_BUCK3
PMOS Peak Current
ILIMP TA = -40°C to +85°C, VSYS = 3.6V 3825 4250 4675 mA
Limit
NMOS Valley Current
ILIMV 3750 mA
Limit
NMOS (Negative)
ILIMN 2000 mA
Current Limit
BROWNOUT COMPARATOR
Normal-power mode, falling threshold,
77
BUCK3_BO_THR[1:0] = 0b00
Normal-power mode, falling threshold,
81
Output Brownout BUCK3_BO_THR[1:0] = 0b01
VBO_BUCK3 %
Threshold Normal-power mode, falling threshold,
85.7
BUCK3_BO_THR[1:0] = 0b10
Normal-power mode, falling threshold,
91
BUCK3_BO_THR[1:0] = 0b11
Output Brownout Ac- Normal-power mode. VOUT_BUCK3 = 1.0V
-4.5 +4.5 %
curacy (VOUT_BUCK3[7:0] = 0x4B)

Output Brownout
Threshold VBO_BUCKx Falling threshold, low-power mode 86.0 %
(Low-Power Mode)

Output Brownout Low-power mode, VOUT_BUCK3 = 1.0V

-4 +4 %
Accuracy (VOUT_BUCK3[7:0] = 0x4B)
Output Brownout VBO_HYS_ 2-Bit control over I2C. Max rising threshold
5 20 %
Hysteresis Range BUCKx limited to 96%
Brownout Voltage
Hysteresis Programming Programmable with BUCKx_BO_HYS[1:0] 5 %
Step Size

Output Brownout
VBO_HYS_
Hysteresis 5 %
(Low-Power Mode) BUCKx_LPM

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Buck Regulators (BUCK3 - 3A Output) (continued)

(VSYS = 5.0V, TA = -40°C to +85°C, Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant
supply voltage range are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not
production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
BUCKx_BO_PR[1:0] = 0b00 (fast), buck in
normal-power mode, 100mV under-drive
with falling slew rate of 150mV/μs. Time 1.04
from VOUT_BUCKx falling to PGOOD pin
falling
BUCKx_BO_PR[1:0] = 0b01 (med-fast),
buck in normal-power mode, 100mV under-
drive with falling slew rate of 150mV/μs. 1.14
Time from VOUT_BUCKx falling to PGOOD
pin falling
BUCKx_BO_PR[1:0] = 0b10 (med-slow),
Output Brownout buck in normal-power mode, 100mV
tBO_BUCKx μs
Response Time under-drive with falling slew rate of 1.30
150mV/μs. Time from VOUT_BUCKx falling
to PGOOD pin falling
BUCKx_BO_PR[1:0] = 0b11 (slow), buck
in normal-power mode, 100mV under-drive
with falling slew rate of 150mV/μs. Time 1.68
from VOUT_BUCKx falling to PGOOD pin
falling
Buck in Low-power mode, 100mV under-
drive with falling slew rate of 150mV/μs.
3.18
Time from VOUT_BUCKx falling to PGOOD
pin falling
Normal-power mode,
13.4
BUCKx_BO_PR[1:0] = 0b00 (fast)
Normal-power mode,
10.4
IQNM_BO_ BUCKx_BO_PR[1:0] = 0b01 (med-fast)
Output Brownout Supply BUCKx Normal-power mode,
7.4 µA
Current BUCKx_BO_PR[1:0] = 0b10 (med-slow)
Normal-power mode,
4.4
BUCKx_BO_PR[1:0] = 0b11 (slow)
IQLPM_BO_
Low-power mode 1.3
BUCKx

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Buck Regulators (BUCK3 - 3A Output) (continued)

(VSYS = 5.0V, TA = -40°C to +85°C, Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant
supply voltage range are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not
production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OV COMPARATOR
VOUTBUCK3_
Output OV Trip Level Rising edge, BUCK3_OV_THR = 1 117.1 %
OV
Output OV hysteresis BUCK3_OV_THR = 1 8.6 %
VOUTBUCKx_
Output OV Trip Level Rising edge, BUCK3_OV_THR = 0 108.5 %
OV
Output OV Hysteresis BUCK3_OV_THR = 0 3.9 %
Output OV Trip Level VOUTBUCK3_
Rising edge, low-power mode 108.3 %
(Low-Power Mode) OV
Output OV Hysteresis
Low-power mode 3.9 %
(Low-Power Mode)

Buck in normal-power mode, 100mV over-

Output Over-Voltage drive with rising slew rate of 150mV/μs.
tOV_BUCK3 1.68 μs
Response Time Time from VOUT_BUCK3 rising to PGOOD
pin falling (Note 10)

Output Over-Voltage
IQ_OV_BUCKx Buck in normal-power mode 4.4 µA
Supply current
Buck in low-power mode, 100mV over-drive
Output Over-Voltage
with rising slew rate of 150mV/μs. Time
Response Time tOV_BUCKx 3.18 μs
from VOUT_BUCKx rising to PGOOD pin
(Low-Power Mode)
falling (Note 10)

Output Over-Voltage
Supply current IQ_OV_BUCK3 Buck in low-power mode 1.3 µA
(Low-Power Mode)

Note 10: Design guidance only and is not production tested.

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Load Switch Driver (LSW1/2)

(VSYS = 3.6V, TA = -40°C to +85°C, Limits are 100% tested at TA = +25°C. Limits over the operating temperature range are guaran-
teed by design and characterization. Specifications marked "GBD" are guaranteed by design and not production tested. x is used to
represent multiple instances of similar resources, for this section x = 1, 2 unless specified for e.g., LSWx represents LSW1, LSW2.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLY
VINLSWx = VSYS = 5V, LSWxDRV_
Supply Current ISYS_LSW_SS FREQ=0b111 (800kHz), 68 µA
COUTLSWx = 20μF
Supply Voltage Range VSYS 2.6 5.5 V
VINLSWx = VSYS = 3.3V,
LSWxDRV_FREQ = 0b111 (1.6MHz), 43
COUTLSWx = 20μF
Supply Current ISYS_LSW_SS µA
VINLSWx = VSYS = 5V,
LSWxDRV_FREQ = 0b101 (400kHz), 20
COUTLSWx = 20μF

VSYS = 5.5V, VLSWx_DRV = 0V and 11V,

0.001 1
TA = +25°C
Leakage ILKG_LSWx_DRV µA
VSYS = 5.5V, VLSWx_DRV =0 V and 11V,
0.01
TA = +85°C
NMOS SWITCH DRIVER
Gate Drive Voltage VLSWx_DRV VSYS = 5V 8.5 11 V

VSYS = 3.3V, 1X gate drive frequency

Gate Drive Current ILSWx_DRV setting (LSWx_DRV_FREQ[2:0] = 0b101), 1.85 3.7 5.55 µA
COUTLSWx = 20μF

4x Gate Drive Oscillator LSWxDRV_FREQ[2:0] = 0b111,

fLSWx_DRV_4X 1600 kHz
Frequency VSYS = 3.3V, VSYS = 5V
2x Gate Drive Oscillator LSWx_DRV_FREQ[2:0] = 0b110,
fLSWx_DRV_2X 800 kHz
Frequency VSYS = 3.3V, VSYS = 5V
LSWx_DRV_FREQ[2:0] = 0b101
1x Gate Drive
fLSWx_DRV_1X (nominal gate drive strength), 200 400 600 kHz
Oscillator Frequency
VSYS = 3.3V, VSYS = 5V
0.5x Gate Drive LSWx_DRV_FREQ[2:0] = 0b100,
fLSWx_DRV_0.5X 200 kHz
Oscillator Frequency VSYS = 3.3V, VSYS = 5V
0.25x Gate Drive fLSWx_ LSWx_DRV_FREQ[2:0] = 0b011,
100 kHz
Oscillator Frequency DRV_0.25X VSYS = 3.3V, VSYS = 5V
0.125x Gate Drive fLSWx_ LSWx_DRV_FREQ[2:0] = 0b010,
25 50 75 kHz
Oscillator Frequency DRV_0.125X VSYS = 3.3V, VSYS = 5V
0.0625x Gate Drive fLSWx_ LSWx_DRV_FREQ[2:0] = 0b001,
25 kHz
Oscillator Frequency DRV_0.0625X VSYS = 3.3V, VSYS = 5V

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Load Switch Driver (LSW1/2) (continued)

(VSYS = 3.6V, TA = -40°C to +85°C, Limits are 100% tested at TA = +25°C. Limits over the operating temperature range are guaran-
teed by design and characterization. Specifications marked "GBD" are guaranteed by design and not production tested. x is used to
represent multiple instances of similar resources, for this section x = 1, 2 unless specified for e.g., LSWx represents LSW1, LSW2.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

0.03125x Gate Drive fLSWx_ LSWx_DRV_FREQ[2:0] = 0b000,
12.50 kHz
Oscillator Frequency DRV_0.03125X VSYS = 3.3V, VSYS = 5V
Output Active Discharge
RDISCHG_LSW 50 100 150 Ω
Resistance
Resistance from LSWx_DRV to FBLSWx,
74
Gate Drive Discharge VLSWx_DRV-FBLSWx = 4V
RLSW_GDRV_DIS Ω
Resistance Resistance from LSWx_DRV to FBLSWx,
100
VLSWx_DRV-FBLSWx = 3.3V
TIMING

Duration from MOSFET drive circuit being

enabled to the internal soft-start done cycles of
signal being asserted. Based on default fLSWx_
Soft-Start Done Time tSS_DONE_LSW 256
gate drive frequency (fLSWx_DRV_FREQ) DRV_
selected by LSWx_DRV_FREQ[2:0] to FREQ
program the default gate drive frequency

POWER-OK COMPARATOR

Rising edge, input to the load switch

0.85 x 0.90 x 0.95 x
Output Power-OK VLSWx_OUT_ is either one of the three internal buck
VIN_ VIN_ VIN_ V
Threshold POK_INT regulator outputs or VSYS as selected by
LSWx_INP_EXT LSWx LSWx LSWx

Output Power-OK
3 %
Hysteresis

VSYS = 3.3V, VINLSWx = 1.8V, LSWx is

Power-OK Response
enabled, 100mV under-drive with falling 1.20 μs
Time
slew rate of 150mV/μs

Power-OK Comparator VSYS = 3.3V, VINLSWx = 1.8V,

IQ_POK_LSWx 1.1 μA
Active Current LSWx is enabled

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Load Switch Driver (LSW3)

(VSYS = 3.6V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range are guaranteed
by design and characterization. Specifications marked "GBD" are guaranteed by design and not production tested. This section is
applicable when OTP_INRUSH_DISABLE = 1 and LSW_OTP_SEL = 1.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLY
Supply Voltage Range VSYS 2.6 5.5 V

VINLSW3 = VSYS = 3.3V, OTP_

INR_FREQ[2:0] = 0b111 (720kHz), 40
COUTLSW3 = 20μF
Supply Current ISYS_LSW_SS µA
VINLSW3 = VSYS = 5V,
OTP_INR_FREQ[2:0] = 0b111 (720kHz), 67
COUTLSW3 = 20μF

VSYS = 5.5V, VINR_DRV = 0V and 11V,

0.001 1
TA = +25°C
Leakage ILKG_LSW3_DRV µA
VSYS = 5.5V, VINR_DRV = 0V and 11V,
0.01
TA = +85°C
NMOS SWITCH DRIVER
Gate Drive Voltage VLSW3_DRV VSYS = 5V 8.5 11 V

VSYS = 3.3V, 1X gate drive frequency

Gate Drive Current ILSW3_DRV setting (OTP_INR_FREQ[2:0] = 0b101), 1.8 3 4.2 µA
COUTLSW3 = 20μF

4x Gate Drive Oscillator OTP_INR_FREQ[2:0] = 0b111,

fLSW3_DRV_4X 720 kHz
Frequency VSYS = 3.3V, VSYS = 5V
2x Gate Drive Oscillator OTP_INR_FREQ[2:0] = 0b110,
fLSW3_DRV_2X 360 kHz
Frequency VSYS = 3.3V, VSYS = 5V

OTP_INR_FREQ[2:0] = 0b101 (nominal

1x Gate Drive Oscillator
fLSW3_DRV_1X gate drive strength), VSYS = 3.3V, 120 180 240 kHz
Frequency
VSYS = 5V

0.5x Gate Drive OTP_INR_FREQ[2:0] = 0b100,

fLSW3_DRV_0.5X 90 kHz
Oscillator Frequency VSYS = 3.3V, VSYS = 5V
0.25x Gate Drive OTP_INR_FREQ[2:0] = 0b011,
fLSW3_DRV_0.25X 45 kHz
Oscillator Frequency VSYS = 3.3V, VSYS = 5V
0.125x Gate Drive fLSW3_ OTP_INR_FREQ[2:0] = 0b010,
15 23 32 kHz
Oscillator Frequency DRV_0.125X VSYS = 3.3V, VSYS = 5V
0.0625x Gate Drive fLSW3_ OTP_INR_FREQ[2:0] = 0b001,
11.25 kHz
Oscillator Frequency DRV_0.0625X VSYS = 3.3V, VSYS = 5V

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Load Switch Driver (LSW3) (continued)

(VSYS = 3.6V, TA = -40°C to +85°C, limits are 100% tested at TA = +25°C. Limits over the operating temperature range are guaranteed
by design and characterization. Specifications marked "GBD" are guaranteed by design and not production tested. This section is
applicable when OTP_INRUSH_DISABLE = 1 and LSW_OTP_SEL = 1.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

0.03125x Gate Drive fLSW3_ OTP_INR_FREQ[2:0] = 0b000,
5.625 kHz
Oscillator Frequency DRV_0.03125X VSYS = 3.3V, VSYS = 5V
Resistance from LSW3_DRV to
74
Gate Drive Discharge FBLSW3, VLSW3_DRV-FBLSW3 = 4V
RLSW_GDRV_DIS Ω
Resistance Resistance from LSWx_DRV to FBLS-
100
Wx, VLSWx_DRV-FBLSWx = 3.3V
TIMING
Duration from MOSFET drive circuit
being enabled to the internal soft-start
cycles of
done signal being asserted.
fLSW3_
Soft-Start Done Time tSS_DONE_LSW Based on default gate drive frequency 512
(fLSW3_DRV_FREQ) selected by (OTP_ DRV_
INR_FREQ[2:0], to program the default FREQ
gate drive frequency
POWER-OK COMPARATOR
Rising edge, input to the load switch
0.85 x 0.90 x 0.95 x
Output Power-OK VLSW3_OUT_ is either one of the four internal buck
VIN_ VIN_ VIN_ V
Threshold POK_INT regulator outputs or VSYS as selected
by LSW3_INP_EXT LSW3 LSW3 LSW3

Output Power-OK
3 %
Hysteresis
VSYS = 3.3V, VINLSWx = 1.8V, LSWx is
Power-OK Response
enabled, 100mV under-drive with falling 1.20 μs
Time
slew rate of 150mV/μs
Power-OK Comparator VSYS = 3.3V, VINLSWx = 1.8V, LSWx is
IQ_POK_LSWx 1.1 μA
Active Current enabled

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Linear Regulator

(VSYS = 3.6V, VIN_LDO = 3.6V, VOUT_LDO = 1.8V, CIN_LDO = 1μF, COUT_LDO = 2.2μF, limits are 100% production tested at
TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless
otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

GENERAL CHARACTERISTICS
Guaranteed by Output Voltage Accuracy tests
Input Voltage Range VIN_LDO 1.7 VSYS V
(Notes 11, 12)

Current measured into IN_LDO, LDO output

disabled, VSYS = 3.6V, VIN_LDO = 3.6V.
LDO Shutdown Production tested in combination with other
IIN_LDO <0.1 1 μA
IN_LDO Current blocks as shown in the OFF State Quiescent
Current parameter of the Electrical
Characteristics—Linear Regulator table

Current measured into IN_LDO, LDO output

disabled, VSYS = 3.6V, VIN_LDO = 3.6V.
LDO Shutdown SYS
ISYS Production tested in combination with other <0.1 μA
Current
blocks as shown in the global resources
"OFF State Quiescent Current" parameter

Normal mode of operation, current

measured into IN_LDO, LDO output enabled
LDO Normal Mode
and in regulation, VSYS = 3.6V, VIN_LDO =
Quiescent Supply
IIN_LDO 3.6V, VOUT_LDO = 2.5V, IOUT_LDO = 0mA. 16 20 μA
IN_LDO Current
Production tested in a combination with all
(Not in Dropout)
other blocks as shown in the global resources
"ON State Quiescent Current" parameter

Normal mode of operation, current

measured into IN_LDO, LDO output
enabled and in regulation, VSYS = 3.6V,
LDO Normal Mode
VIN_LDO = 3.6V, VOUT_LDO = 2.5V,
Quiescent Supply SYS ISYS 5 7 μA
IOUT_LDO = 0mA. Production tested in
Current (Not in Dropout)
combination with other blocks as shown in the
global resources "ON State Quiescent
Current" parameter

Normal mode of operation, current measured

LDO Normal Mode
into IN_LDO, LDO output enabled and in
Quiescent Supply
IIN_LDO regulation, VSYS = 3.6V, VIN_LDO = 2.0V, 20 μA
IN_LDO Current
VOUT_LDO_TARGET = 2.5V, IOUT_LDO = 0mA
(In Dropout)
(Note 13)

Normal mode of operation, current measured

LDO Normal Mode into IN_LDO, LDO output enabled and in
Quiescent Supply SYS ISYS regulation, VSYS = 3.6V, VIN_LDO = 2.0V, 5 μA
Current (In Dropout) VOUT_LDO_TARGET = 2.5V, IOUT_LDO = 0mA
(Note 13)

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Linear Regulator (continued)

(VSYS = 3.6V, VIN_LDO = 3.6V, VOUT_LDO = 1.8V, CIN_LDO = 1μF, COUT_LDO = 2.2μF, limits are 100% production tested at
TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless
otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Low-power mode of operation, current mea-

sured into IN_LDO, LDO output enabled and
LDO Low-Power Mode
in regulation, VSYS = 3.6V, VIN_LDO = 3.6V,
Quiescent Supply
IIN_LDO VOUT_LDO = 2.5V, IOUT_LDO = 0mA. 2 3 μA
IN_LDO Current
Production tested in combination with other
(Not in Dropout)
blocks as shown in the global resources
"DEVSLP State Quiescent Current" parameter

LDO Low-Power Mode Low-power mode of operation, current mea-

Quiescent Supply sured into IN_LDO, LDO output enabled and
ISYS 2 3 μA
SYS Current in regulation, VSYS = 3.6V, VIN_LDO = 3.6V,
(Not in Dropout) VOUT_LDO = 2.5V, IOUT_LDO = 0mA.

Low-power mode of operation, current mea-

LDO Low-Power Mode
sured into IN_LDO, LDO output enabled and
Quiescent Supply
IIN_LDO in regulation, VSYS = 3.6V, VIN_LDO = 2.0V, 1.5 μA
IN_LDO Current (In
VOUT_LDO_TARGET = 2.5V, IOUT_LDO = 0mA
Dropout)
(Note 13)

Low-power mode of operation, current mea-

LDO Low-Power Mode sured into IN_LDO, LDO output enabled and
Quiescent Supply SYS ISYS in regulation, VSYS = 3.6V, VIN_LDO = 2.0V, 2.5 μA
Current (In Dropout) VOUT_LDO_TARGET = 2.5V, IOUT_LDO = 0mA
(Note 13)

Maximum Output Normal-power mode (Note 14) 150

IOUT_LDO mA
Current Low-power mode (Note 14) 5

Normal-power mode, VOUT_LDO set for 3.2V

and loaded down to 90% of set output voltage 165 300
Output Current Limit (Note 15) mA
Low-power mode, VOUT_LDO set for 3.2V and
40
loaded down to 90% of set output voltage
Output Capacitance for ESR must be less than 200mΩ, ESL is less
CLDO_OUT 1.1 2.2 20 μF
Stability than 20nH
OUTPUT VOLTAGE RANGE
Minimum Programma-
TV_LDO[6:0] = 0b0000000 0.8 V
ble Output Voltage
Maximum Program-
TV_LDO[6:0] = 0b1111111 3.975 V
mable Output Voltage
Output DAC Bits 7 Bits
Output DAC LSB Size 25 mV

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Linear Regulator (continued)

(VSYS = 3.6V, VIN_LDO = 3.6V, VOUT_LDO = 1.8V, CIN_LDO = 1μF, COUT_LDO = 2.2μF, limits are 100% production tested at
TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless
otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

STATIC CHARACTERISTICS
VSYS = 5.5V, VIN_LDO = 1.7V, VOUT_LDO =
-2 +2
0.8V, IOUT_LDO = 150mA, normal-power mode
VSYS = 5.5V, VIN_LDO = 1.7V, VOUT_LDO =
-6.5 +6.5
0.8V, IOUT_LDO = 5mA, low-power mode
VSYS = 2.8V, VIN_LDO = 2.8V, VOUT_LDO =
-2 +2
2.5V, IOUT_LDO = 150mA, normal-power mode
Output Voltage
VSYS = 2.8V, VIN_LDO = 2.8V, VOUT_LDO = %
Accuracy -6.5 +6.5
2.5V, IOUT_LDO = 5mA, low-power mode

VSYS = 5.5V, VIN_LDO = 5.5V,

VOUT_LDO = 3.975V, IOUT_LDO = 0.1mA, -2 +2
normal-power mode

VSYS = 5.5V, VIN_LDO = 5.5V, VOUT_LDO =

-6.5 +6.5
3.975V, IOUT_LDO = 0.1mA, low-power mode

VSYS = 5.5V, VIN_LDO = 1.7V to 5.5V,

VOUT_LDO = 0.8V, IOUT_LDO = 0.1mA, 0.05
normal-power mode

VSYS = 5.5V, VIN_LDO = 1.7V to 5.5V,

VOUT_LDO = 0.8V, IOUT_LDO = 0.1mA, 0.05
low-power mode
Line Regulation %/V
VSYS = 5.5V, VIN_LDO = 4.4V to 5.5V,
VOUT_LDO = 3.975V, IOUT_LDO = 0.1mA, 0.05
normal-power mode

VSYS = 5.5V, VIN_LDO = 4.4V to 5.5V,

VOUT_LDO = 3.975V, IOUT_LDO = 0.1mA, 0.05
low-power mode

VSYS = 5.5V, VIN_LDO = 1.7V,

VOUT_LDO = 0.8V, IOUT_LDO = 0.1mA to 0.5
150mA, normal-power mode

VSYS = 5.5V, VIN_LDO = 1.7V,

VOUT_LDO = 0.8V, IOUT_LDO = 0.1mA to 5mA, 0.5
low-power mode
Load Regulation %
VSYS = 5.5V, VIN_LDO = 3.975V,
VOUT_LDO = 0.8V, IOUT_LDO = 0.1mA to 0.5
150mA, normal-power mode

VSYS = 5.5V, VIN_LDO = 3.975V,

VOUT_LDO = 0.8V, IOUT_LDO = 0.1mA to 5mA, 0.5
low-power mode

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Linear Regulator (continued)

(VSYS = 3.6V, VIN_LDO = 3.6V, VOUT_LDO = 1.8V, CIN_LDO = 1μF, COUT_LDO = 2.2μF, limits are 100% production tested at
TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless
otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Normal-power mode, f = 10Hz to 100kHz,

ILDO_OUT = 15mA, VSYS = 2.7V, 100
VIN_LDO = 1.7V, VLDO = 0.8V

Normal-power mode, f = 10Hz to 100kHz,

ILDO_OUT = 15mA, VSYS = 2.7V, 150
VIN_LDO = 1.7V, VLDO = 1.0V

Normal-power mode, f = 10Hz to 100kHz,

Output Noise ILDO_OUT = 15mA, VSYS = 2.7V, 200 μVRMS
VIN_LDO = 2.7V, VLDO = 2.0V

Normal-power mode, f = 10Hz to 100kHz,

ILDO_OUT = 15mA, VSYS = 3.6V, 300
VIN_LDO = 3.6V, VLDO = 3.0V

Normal-power mode, f = 10Hz to 100kHz,

ILDO_OUT = 15mA, VSYS = 5.5V, 400
VIN_LDO = 5.5V, VLDO = 3.975V

DYNAMIC CHARACTERISTICS

Normal-power mode, VSYS = 3.6V,

Power-Supply Rejection
PSRR VIN_LDO = 2.8V+20mVpp, f = 10Hz to 10kHz, 60 dB
Ratio
VOUT_LDO = 1.8V, IOUT_LDO = 15mA

Normal-power mode, VOUT_LDO = 1.2V,

IOUT_LDO = 1mA, VSYS = VIN_LDO = 3.6V to 5
3.2V to 3.6V with 5μs transition times
Line Transient mV
Normal-power mode, VOUT_LDO = 1.2V,
IOUT_LDO = 1mA, VSYS = 3.6V, VIN_LDO = 5
3.6V to 3.2V to 3.6V with 5μs transition times

Normal-power mode, VOUT_LDO = 2.5V,

IOUT_LDO = 1mA to 75mA to 1mA with 1µs ±5
transition times, COUT_LDO = 2.2µF
Load Transient %
Normal-power mode, VOUT_LDO = 2.5V,
IOUT_LDO = 1mA to 75mA to 1mA with 1µs ±3
transition times, COUT_LDO = 10µF

Output Over-Shoot
50 mV
During Startup
TIMING CHARACTERISTICS
Maximum Turn-On From the LDO receiving an enable signal to
20 μs
Delay when the output voltage starts to rise
Maximum Soft-Start VOUT_LDO from 10% to 90% of 2.5V final
40 μs
Time value

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—Linear Regulator (continued)

(VSYS = 3.6V, VIN_LDO = 3.6V, VOUT_LDO = 1.8V, CIN_LDO = 1μF, COUT_LDO = 2.2μF, limits are 100% production tested at
TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless
otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER STAGE CHARACTERISTCIS
Normal-power mode, VSYS = 3.6V, 3.3V
programmed output voltage, VIN_LDO = 3.1V, 100 200
IOUT_LDO = 150mA (Note 13)
Dropout Voltage VLDO_DO mV
Normal-power mode, VSYS = 3.6V, 1.8V
programmed output voltage, VIN_LDO = 1.7V, 100
IOUT_LDO = 150mA (Note 13)

Disabled Output Regulator disabled, active-discharge enabled

RAD_LDO 50 100 150 Ω
Impedance (ADE_LDO = 1) (Note 16)

Regulator disabled, active-discharge disabled

Disabled Output (ADE_LDO = 0), VSYS = VIN_LDO = 5.5V,
-1.0 ±0.1 +1.0 μA
Leakage Current VOUT_LDO = 5.5V and 0V, TA = +25°C
(Note 17)

POWER-OK COMPARATOR
Output Power-OK
Rising edge, VOUT_LDO = 2.0V 82.5 87.5 92.5 %
Trim Level
Output Power-OK
VOUT_LDO = 2.0V 3 %
Hysteresis

Note 11: When the input voltage is within the specified range, the LDO tries to regulate the output voltage. However, the regulator
may be in dropout. For example, if the output voltage is fixed at 1.85V and a 1.7V input is provided, the output is 1.7V
minus the dropout voltage (VLDO = VIN_LDO-VLDO_DO). To achieve the specified output voltage, the input voltage must
be the output voltage plus the dropout voltage (VIN_LDO ≥ VLDO + VLDO_DO_MAX).
Note 12: VIN_LDO must be lower than or equal to VSYS. The VSYS maximum operating voltage range is 5.5V. For example, if
VSYS is 4.2V, then the maximum voltage for VIN_LDO is 4.2V. Similarly, if VSYS is 5.5V, then the maximum voltage for
VIN_LDO is 5.5V.
Note 13: The dropout voltage is the difference between the input voltage and the output voltage, when the input voltage is inside
the specified "input voltage" range but below the "output voltage" set point. For example, if the output voltage set point
is 1.85V, the input voltage is 1.7V, and the actual output voltage is 1.65V, then the dropout voltage is 50mV (VLDO_DO =
VIN_LDO-VOUT_LDO).
Note 14: The "Maximum Output Current" is guaranteed by the "Output Voltage Accuracy" tests.
Note 15: Current limit is provided for thermal concerns as a system fail safe feature, minor (50mA) oscillations of current when the
LDO is at current limit are normal. Over process corner current limit is not expected to exceed 560mA.
Note 16: There is an n-channel MOSFET in series with the output active discharge resistance. This NMOS requires VSYS > 1.2V
to be enhanced.
Note 17: Guaranteed by design and characterization but not directly production tested. The ability to disconnect the active dis-
charge resistance is functionally checked in a production test.

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—I2C Interface

(TA = -40°C to +85°C (unless otherwise specified), VIO = 1.8V, V = 3.6V)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLY
VIO Voltage Range VIN_VIO_I2C 1.7 3.6 V
SDA AND SCL I/O STAGE
0.7 x
SCL, SDA Input HIGH Voltage VIH VIN_VIO_I2C = 1.7V to 3.6V VIN_VIO_ V
I2C

0.3 x
SCL, SDA Input LOW Voltage VIL VIN_VIO_I2C = 1.7V to 3.6V VIN_
VIO_I2C

0.1 x
SCL, SDA Input Hysteresis VHYS VIN_ V
VIO_I2C

SCL, SDA Input Leakage VIN_VIO_I2C = 3.6V,

II -10 +10 μA
Current VSCL = VSDA = 0V and 3.6V
SDA Output LOW Voltage VOL IOL = 20mA 0.4 V
SCL, SDA Pin Capacitance CI 10 pF
Output Fall Time from
tOF (Note 18) 120 ns
VIH to VIL
OTP_INT_PU[0] = 0b0 Open
RPU_SDA,
Internal Pullup Pulled up to VIN_VIO_I2C, kΩ
RPU_SCL 2.5 5.0 7.5
OTP_INT_PU[0] = 0b1
WATCHDOG TIMER
Watchdog Timer Period tWD 35 ms
I2C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST, AND FAST-MODE PLUS) (Note 18)
Clock Frequency fSCL 0 1000 kHz
Bus Free Time between
tBUF 0.5 μs
STOP and START Condition
Hold Time (REPEATED)
tHD;STA 0.26 μs
START Condition
SCL LOW Period tLOW 0.5 μs
SCL HIGH Period tHIGH 0.26 μs
Setup Time REPEATED
tSU_STA 0.26 μs
START Condition

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—I2C Interface (continued)

(TA = -40°C to +85°C (unless otherwise specified), VIO = 1.8V, V = 3.6V)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DATA Hold Time tHD_DAT Receive mode 0 μs
DATA Setup Time tSU_DAT 50 ns
Setup Time for STOP Condition tSU_STO 0.26 μs
Data Valid Time tVD_DAT Transmit mode 0.45 μs
Data Valid Acknowledge Time tVD_ACK 0.45 μs
Bus Capacitance CB 550 pF
Pulse Width of Suppressed
tSP 50 ns
Spikes
I2C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, CB = 100pF) (Note 18)
Clock Frequency fSCL 3.4 MHz
Hold Time (REPEATED)
tHD_STA 160 ns
START Condition
Setup Time REPEATED
tSU_STA 160 ns
START Condition
SCL LOW Period tLOW 160 ns
SCL HIGH Period tHIGH 60 ns
DATA Hold Time tHD_DAT 0 ns
DATA Setup Time tSU_DAT 10 ns
SCL Rise Time trCL TA = +25°C (Note 18) 10 40 ns

Rise Time of SCL Signal After

REPEATED START Condition trCL1 TA = +25°C (Note 18) 10 80 ns
and After Acknowledge Bit

SCL Fall Time tfCL TA = +25°C (Note 18) 10 40 ns

SDA Rise Time trDA TA = +25°C (Note 18) 10 80 ns
SDA Fall Time tfDA TA = +25°C (Note 18) 80 ns
Setup Time for STOP Condition tSU_STO 160 ns
Bus Capacitance CB 100 pF
Pulse Width of Suppressed
tSP 10 ns
Spikes

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MAX77752 Multichannel Integrated Power Management IC

Electrical Characteristics—I2C Interface (continued)

(TA = -40°C to +85°C (unless otherwise specified), VIO = 1.8V, V = 3.6V)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

I2C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, CB = 400pF) (Note 18)
Clock Frequency fSCL 1.7 MHz
Hold Time (REPEATED) START
tHD_STA 160 ns
Condition
Setup Time REPEATED START
tSU_STA 160 ns
Condition
SCL LOW Period tLOW 320 ns
SCL HIGH Period tHIGH 120 ns
DATA Hold Time tHD_DAT 0 ns
DATA Setup Time tSU_DAT 10 ns
SCL Rise Time trCL TA = +25°C (Note 18) 20 80 ns

Rise Time of SCL Signal after

REPEATED START Condition trCL1 TA = +25°C (Note 18) 20 160 ns
and after Acknowledge bit

SCL Fall Time tfCL TA = +25°C (Note 18) 20 80 ns

SDA Rise Time trDA TA = +25°C (Note 18) 20 160 ns
SDA Fall Time tfDA TA = +25°C (Note 18) 160 ns
Setup Time for STOP Condition tSU_STO 160 ns
Bus Capacitance CB 400 pF
Pulse Width of Suppressed
tSP 10 ns
Spikes

Note 18: Minimum typical and maximum values are guaranteed by design. Not production tested.

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MAX77752 Multichannel Integrated Power Management IC

Pin Configuration

LSW_DRV1

LSW_DRV2
FBLSW2
TOP VIEW

PGND3
PGND3
FBB3
INB3
INB3
LX3
LX3
30 29 28 27 26 25 24 23 22 21

FBLSW1 31 20 DGND

FBB2 32 19 BLD_IO

INB2 33 18 GND
LX2 34 17 EREG_EN2

PGND2 35 MAX77752 16 LP_MODE

PGND1 36 15 LP_ACK

LX1 37 14 EREG_POK

INB1 38 13 RESET_L
+
FBB1 39 12 LP_REQ

SDA 40 11 INR_OUT
1 2 3 4 5 6 7 8 9 10
SCL
IN_LDO
OUT_LDO
SYS
IN_PHUP
PGOOD
EREG_EN1
WP_L
INR_DRV
TQFN IN_SNS
5mm x 5mm

Pin Description
PIN NAME FUNCTION TYPE
TOP

External Inrush FET Gate Drive. Inrush MOSFET Gate Driver. When using the
inrush control feature, connect INR_DRV to the gate of an external NMOS.
If the inrush feature is not required, this pin can also be configured as LSW3_DRV Analog
9 INR_DRV
using LSW_OTP_SEL = 1. If either use cases do not apply, leave INR_DRV Output
unconnected or connect to ground ONLY after ensuring that the inrush controller is
disabled by the appropriate OTP option.

Input Voltage Sense (Preswitch). Input Voltage Sense. When using the inrush control
Power
10 IN_SNS feature, connect IN_SNS to the drain of an external n-channel MOSFET. When the
Input
inrush control feature is not needed, connect IN_SNS to VSYS.
Inrush Control Output Sense. This pin must be connected to the source of the inrush control
MOSFET. If the inrush controller is not required, this pin can also be configured as FBLSW3 Power
11 INR_OUT
by setting LSW_OTP_SEL = 1. If either use cases do not apply, then this pin must be con- Input
nected to the SYS node.

System Power Input. SYS is the voltage sense input for the inrush controller, system
voltage monitors, and other analog circuits. Connect SYS to the same power source as that
meant for the voltage regulators in the PMIC.
When using the inrush control feature, connect SYS to the source of an external Power
4 SYS
n-channel MOSFET whose drain is connected to the main power input. When the Input
inrush control feature is not needed, connect SYS to IN_SNS.
Regardless of the inrush controller configuration, SYS must connect to the buck regulator
power inputs (INB1, INB2, INB3).

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MAX77752 Multichannel Integrated Power Management IC

Pin Description (continued)

PIN NAME FUNCTION TYPE
Ground. GND carries ground current for "quiet" control circuits. GND also carries the
18 GND Ground
current for the OTP programming circuit when the programming sequence is executed.

Write Protect (Open Drain, Active Low) to memory. Connect this pin to the appropriate pin on
Digital
8 WP_L the memory. An optional 100kΩ internal pullup resistor is available which is pulled up to an
Output
internal VIN_VIO node.

Low-Power Mode Acknowledge from controller.

Connect LP_ACK to the appropriate pin on the controller.
LP_ACK acknowledges the LP_REQ output signal in master mode
(OTP_SLP_MSTRSLV = 0) by asserting high, which initiates the transition to DevSlp state. Digital
15 LP_ACK
LP_ACK initiates the transition to DevSlp state independently in slave mode Input
(OTP_SLP_MSTRSLV = 1) by asserting high.
An optional 100kΩ internal pullup resistor is available which is pulled up to an internal
VIN_VIO node.

Reset Output (Open Drain, Active Low) to controller.

Digital
13 RESET_L Connect to the reset input of the controller. An optional 100kΩ internal pullup
Output
resistor is available which is pulled up to an internal node.

Power Good Output (Open Drain, Active High). PGOOD indicates the status of all
regulators controlled by the PMIC (internal and external) and asserts LOW if any
regulator's individual Power-OK (POK) signal is deasserted. Additionally, it also asserts Digital
6 PGOOD
low if the system voltage (VSYS) falls below the brownout threshold. Output
Connect PGOOD to the appropriate pin on the controller. An optional 100kΩ internal
pullup resistor is available which is pulled up to an internal node.

External Regulator #1 Enable Output.

Digital
7 EREG_EN1 EREG_EN1 is an open-drain output with optional internal pullup resistor.
Output
EREG_EN1 is typically used to drive the enable pin of an external regulator.

External Regulator #2 Enable Output.

Digital
17 EREG_EN2 EREG_EN2 is an open-drain output with optional internal pullup resistor. EREG_EN2 is
Output
typically used to drive the enable pin of an external regulator.

External Regulator Power-OK Input.

EREG_POK is a digital input. In the typical application, EREG_POK is derived from the Digital
14 EREG_POK
POK outputs of the external regulators that are enabled/disabled by EREG_EN1 and Input
EREG_EN2.

Low-Power Mode Input to PMIC from Connector in Master Mode (OTP_SLP_MSTRSLV = 0).
When in slave mode (OTP_SLP_MSTRSLV = 1), it is recommended to connect LP_MODE
Digital
16 LP_MODE to ground or to a power supply such that it is logic high.
Input
Open-Drain Output. An optional 100kΩ internal pullup resistor is available which is pulled up
to an internal node.

Open-Drain (Active High) Output.

Low-power mode request to controller in master mode in alternate mode
Digital
12 LP_REQ (OTP_SLP_MSTRSLV = 0).
Output
Open-Drain Output.
An optional 100kΩ internal pullup resistor is available which is pulled up to an internal node.

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MAX77752 Multichannel Integrated Power Management IC

Pin Description (continued)

PIN NAME FUNCTION TYPE
20 DGND Digital Ground. DGND carries ground current for digital circuits such as the I2C. Ground

BLD_IO Pin is a Dedicated Open-Drain Input/Output Pin.

In an application, this active-low input discharges the supply rail during a powerup cycle.
Analog
19 BLD_IO This pin also senses the voltage on the pin it is connected to, and the function is to
I/O
discharge a rail lower than 100mV. Connect this pin to GND when this feature is not
required in the system.

IN_PHUP is a Dedicated Analog Input Pin. This pin is connected to the output of the power
Power
5 IN_PHUP holdup IC. In case of a power-fail event, the voltage on this pin drives the internal logic block
Input
to sustain the holdup function by maintaining the logic levels of the appropriate pins.

LDO

Input Power for LDO (150mA). Bypass with a 2.2µF ceramic capacitor to GND with the
following parasitic constraints (including capacitor and PCB parasitics) of ESR<100mΩ and
Power
2 IN_LDO ESL<30nH.
Input
If the LDO is not used, it is recommended to connect IN_LDO to OUT_LDO and connect
them to ground.

150mA PMOS LDO Output. Bypass with a 2.2µF capacitor to GND. Power
3 OUT_LDO
If the LDO is not used, it is recommended to either ground OUT_LDO or leave it unconnected. output
BUCK

BUCK1 Power Input. INB1 is the shared drain connection of BUCK1's main power FET.
Power
38 INB1 Connect both INB1 pins together and to the power input to the system. INB1 is a critical
Input
discontinuous current node that requires careful PCB layout.

BUCK1 Switching Node.

Connect the required inductor between LX and the output capacitor. Power
37 LX1
Both LX1 pins must be connected together. LX1 is a critical node that requires careful PCB I/O
layout.

BUCK1 Power Ground are Internally Combined. PGND1 is the source connection of
36 PGND1 BUCK1's synchronous rectifier. PGND1 is a critical discontinuous current node that requires Ground
careful PCB layout.

BUCK1 Output Voltage Feedback Node.

Connect FBB1 to the local output capacitor at the buck output.
Analog
39 FBB1 In addition to setting the output-voltage regulation threshold, FBB1 can also be programmed
Input
to discharge the output capacitor when the converter is shutdown. FBB1 is a critical analog
input that requires careful PCB layout.

BUCK2 Power Input. INB2 is the shared drain connection of BUCK2's main power FET.
Power
33 INB2 Connect both INB2 pins together and to the power input to the system. INB2 is a critical
Input
discontinuous current node that requires careful PCB layout.

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MAX77752 Multichannel Integrated Power Management IC

Pin Description (continued)

PIN NAME FUNCTION TYPE

BUCK2 Switching Node.

Power
34 LX2 Connect the required inductor between LX and the output capacitor.
I/O
LX2 is a critical node that requires careful PCB layout.

BUCK2 Power Ground are Internally Combined. PGND2 is the source connection of
35 PGND2 BUCK2's synchronous rectifier. PGND2 is a critical discontinuous current node that Ground
requires careful PCB layout.

BUCK2 Output Voltage Feedback Node.

Connect FBB2 to the local output capacitor at the buck output.
Analog
32 FBB2 In addition to setting the output-voltage regulation threshold, FBB2 can also be programmed
Input
to discharge the output capacitor when the converter is shutdown. FBB2 is a critical analog
input that requires careful PCB layout.

BUCK3 Power Input. INB3 is the drain connection of BUCK3's main power FET. Connect to
Power
26,27 INB3 the power input to the system. INB3 is a critical discontinuous current node that requires
Input
careful PCB layout.

BUCK3 Switching Node.

Power
24,25 LX3 Connect the required inductor between LX and the output capacitor.
I/O
LX3 is a critical node that requires careful PCB layout.

BUCK3 Output Voltage Feedback Node.

Connect FBB3 to the local output capacitor at the Buck output.
Analog
21 FBB3 In addition to setting the output voltage regulation threshold, FBB3 may also be programmed
Input
to discharges the output capacitor when the converter is shutdown. FBB3 is a critical analog
input that requires careful PCB layout.

BUCK3 Power Ground. PGND2 is the shared source connection of BUCK3's synchronous
22, 23 PGND3 rectifier. Connect both PGND3 pins together. PGND3 is a critical discontinuous current Ground
node that requires careful PCB layout.

I2C

Serial Interface Data Bidirectional Open Drain.

An optional 5kΩ internal pullup resistor is available which is pulled up to an internal
Digital
40 SDA VIN_VIO_I2C node.
I/O
If the part is in Off state due to HICCUP_CNT_EXPIRE = 1, the I2C power switches from
VFBB1 to VIN_PHUP. Otherwise, the pin is in Hi-Z state during Off condition.

Serial Interface Port 0 Clock Input. Open-Drain Output.

An optional 5kΩ internal pullup resistor is available which is pulled up to an internal
Digital
1 SCL VIN_VIO_I2C node.
Input
If the part is in Off state due to HICCUP_CNT_EXPIRE = 1, the I2C power switchs from
VFBB1 to VIN_PHUP. Otherwise, the pin is in Hi-Z state during Off condition.

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MAX77752 Multichannel Integrated Power Management IC

Pin Description (continued)

PIN NAME FUNCTION TYPE
LOAD SWITCH

Gate Drive for Load Switch 1. Connect to the gate of an external n-channel MOSFET
Analog
30 LSW_DRV1 used as the load switch.
Output
If the load switch is not used, LSW_DRV1 must be left unconnected.

Gate Drive for LSW2. Connect to the gate of an external n-channel MOSFET used
Analog
28 LSW_DRV2 as the load switch.
Output
If the load switch is not used, LSW_DRV2 must be left unconnected.
Feedback Input for Load-Switch Controller 1. FBLSW1 is an analog input to the load-switch
controller which is used to control soft-start of the load switch and is the input to the output
Analog
31 FBLSW1 voltage monitor.
Input
Connect FBLSW1 to the output (source-side of n-channel MOSFET) of the load switch.
If the load switch is not used, FBLSW1 can be left unconnected or tied to ground.
Feedback Input for Load-Switch Controller 2. FBLSW2 is an analog input to the load-switch
controller which is used to control soft-start of the load switch and is the input to the output
Analog
29 FBLSW2 voltage monitor.
Input
Connect FBLSW2 to the output (source-side of n-channel MOSFET) of the load switch.
If the load switch is not used, FBLSW2 can be left unconnected or tied to ground.

Detailed Description— 2) Check the values of CID0, CID1, CID2, CID3, and
CID4. Consider reporting these values if the product
Software Recommendations has some form of serial number checking utility. If the
Advice for optimizing software is provided throughout this SBT bits do not read an appropriate value, then flag
data sheet within the context of the hardware descrip- the product as bad and do not ship it. Only values
tions. This section is dedicated to software recommen- of 0b011 and 0b101 should be shipped as production
dations and provides system level software guidance in units. If the DRV bits do not match with what was in-
order to optimally utilize the features of this device. tended for the given product, then flag that product as
OFF to ON Software Initialization bad and do not ship it. This device has many OTP op-
tions and the DRV bits are set differently for each set
The system processor typically runs a set of initialization
of options. If parts got mixed up in the warehouse (i.e.,
code each time a transition from the OFF to the ON state
A version confused for C version), then this step helps
occurs, the reset output is deasserted (RESET_L = 1), catch that mistake.
and the PGOOD is asserted (PGOOD = 1).
3) Set/Clear the mask bits as deemed appropriate for the
The following are recommended software steps within this target platform.
initialization code:
1) Read the interrupt bits:
1) Interrupt bits set at this point in time can indicate an
issue that previously caused a shutdown.

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MAX77752 Multichannel Integrated Power Management IC

Typical Application Circuits

20mΩ
3.3V
VIN VSYS
10µF
6.3V MAX77752
(0603)
SYS IN_B1 VSYS
INR_OUT
INRUSH 1.0µH
INR_DRV CONTROLLER BUCK1 LX1 VBUCK1
4.7µF 22µF
IN_SNS (2A) 6.3V 6.3V 22µF
PGND1 (0603) (0603) 6.3V
VIN IN_PHUP 0603
10µF FBB1
6.3V
IN_B2 VSYS
(0603) BLD_IO
1.0µH
AGND BUCK2 LX2 VBUCK2
4.7µF 22µF
(2A) 6.3V 6.3V 22µF
DGND
PGND2 (0603) (0603) 6.3V
0603
FBB2
SCL SCL
INB3 VSYS
SDA SDA
1.0µH
PG PGOOD BUCK3 LX3 VBUCK3
4.7µF 22µF
(3A) 6.3V 6.3V 22µF
NC WP_L PGND3 (0603) (0603) 6.3V
GLOBAL 0603
RESOURCES FBB3
RESET_L RESET_L AND
I2C IN_LDO VSYS
GPO GPO
LDO
OUT_LDO VOUT_LDO
(150mA) 2.2µF 2.2µF
EREG_EN1 EREG_EN1 6.3V 6.3V
(GPO) (0402) (0402)
VBUCKx
EREG_EN2 EREG_EN2
(GPO) LSW_DRV1

EREG1_POK EREG_POK LOAD SWITCH FBLSW1 VLSW1

DRIVERS VBUCKx
NC LP_MODE
LSW_DRV2
HOST LP_ACK
FBLSW2 VLSW1

GND PGND

Ordering Information
PART NUMBER TEMP RANGE PIN-PACKAGE TOP MARKING CID4
MAX77752AETL+ -40°C to +85°C 40 TQFN MAX77752AETL+ 0x07
MAX77752BETL+ -40°C to +85°C 40 TQFN MAX77752BETL+ 0x0D
MAX77752CETL+ -40°C to +85°C 40 TQFN MAX77752CETL+ 0x14
MAX77752DETL+ -40°C to +85°C 40 TQFN MAX77752DETL+ 0x15
+Denotes a lead(Pb)-free/RoHS-compliant package.
For a copy of the register map and for further questions, contact [email protected].

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MAX77752 Multichannel Integrated Power Management IC

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 12/17 Initial release —
Added conditions statement to the Electrical Characteristics—Current Sense Amplifier
1 1/18 14
table
Removed SSD and NAND from Pin Description table, added new part variant to
2 1/18 38, 42
Ordering Information table
3 7/18 Updated Ordering Information table 42

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2018 Maxim Integrated Products, Inc. │ 43