TRIBHUVAN UNIVERSITY

INSTITUTE OF ENGINEERING
THAPATHALI CAMPUS

Digital Logic-EX152
Unit 5 : Sequential Logic Circuit
Presented By
Er. Ganesh Kumal
Department of Electronics & Computer Engineering
IOE ,Thapathali Campus

22 June, 2024
 Contents
5.1 Latches and Flip-Flops
5.2 Excitation tables
5.3 Characteristics equations
5.4 Flip-flop timing diagram
5.5 Flip-flop as state machine
5.6 Flip-flop conversions
5.7 Flip-flop classification as triggering
5.8 Flip-flop application

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 Sequential circuit
• Combinational circuit with feedback element
(memory).
• Outputs depend upon present inputs and
previous outputs (present states).
Memory elements are
devices capable of storing
binary information. The
binary information stored
in the memory elements at
any given time defines the
Figure 5.1: Block diagram of sequential circuit. state of the sequential
circuit.
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 Basic Flip-Flop (Latch)
• Single bit storage device (memory unit).
• It latches ‘0’ or ‘1’.
• Basic Flip-flop circuit can be constructed from two
NAND gates or two NOR gates.
• The cross-coupled connection from the output of one
gate to the input of the other gate constitutes a
feedback path.
• Each flip-flop has two outputs ( Q and Q’ ) and two
inputs Set (S) and Reset (R).
• This type of flip-flop is sometimes called a direct-
coupled RS flip-flop, or RS latch.

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Basic Flip-Flop with NOR Gates

When,
S=0, R=0 ; No change state
S=0, R=1 ; Reset
S=1, R=0 ; Set
Figure 5.2: NOR Latch S=1, R=1; Invalid

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Basic Flip-Flop with NAND Gates

Figure 5.3: NAND latch

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 Clock Pulse
• In the latches and flip-flips, we use the additional
signal called clock.
• Digital circuits are invariably controlled by
a clock and events take place at discrete points in
time.
• The clock is a circuit that provides a sequence of
pulses to trigger each internal operation.

Figure 5.4: Perfect idealized clock

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 Positive and Negative Edge Triggering
• Depending on which portion of the clock
signal the latch or flip-flop responds to, we
can classify them into two types:
1. Level Triggering
i. Positive level triggering
ii. Negative level triggering
2. Edge triggering
i. Positive (rising) edge triggering
ii. Negative (falling) edge triggering

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 CONT…

Edge Triggering

Level Triggering
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 Flip-Flop
• Sequential circuit.
• Single bit memory element (storage device).
• Bi-stable device (either ‘1’ or ‘0’).
• Example: S-R flip-flop, D-flip-flop, J-K flip-flop,
T-flip-flop.

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 Clocked RS Flip-Flop
Inputs Outputs

CP S R Q Q’
CP
X 0 0 No change

1 0 1 0 1
(a) Block diagram
1 1 0 1 0

1 1 1 Invalid

(c) Truth table

(b) Logic diagram Figure 5.5: RS Flip-Flop

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Operation of S-R flip-flop
S R Q(t) Q (t +1)
•When CP=0, flip-flop 0 0 0 0
remains in previous state 0 0 1 1
•When CP=1 and 0 1 0 0
i. S = 0, R = 0 ; flip-flop 0 1 1 0
holds the data (No 1 0 0 1
change). 1 0 1 1
ii. S = 0, R = 1 ; flip-flop 1 1 0 X (Indeterminate)
reset irrespective of 1 1 1 X (Indeterminate)
Q Figure: Characteristic table
iii. S = 1, R = 0; flip-flop
set irrespective of
Q.
iv. S =1, R =1; flip-flop is
invalid state
Characteristic equation
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Clocked RS Flip-Flop

Indeterminate

Indeterminate

Figure 5.6: RS flip-flop by NOR latch

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 Timing diagram of S-R F/F

Figure: Level Triggering

Figure: Edge Triggering

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 D Flip-Flop
• One way to eliminate the undesired condition of
the indeterminate state in the RS flip-flop is to
ensure that input S and R are never equal to 1 at
the same time.
• This is done in the D flip-flop as shown in figure
6.6.
• S input is inverted and given to R input to make D
flip-flop from S-R flip-flop.
• Used in registers, shift registers and some of the
counters.
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 D Flip-Flop
S Operation:
As long as CP=0, the output
of gate 3 and 4 are high and
the circuit cannot change the
R state regardless of the value
of D.
When CP=1, next state of D
flip-flop is always equal to
data input, D.
Invalid state is removed in D
flip-flop.
Figure 5.7: D Flip-Flop Advantage: Invalid state is
never happened.
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Figure: Timing diagram of D flip-flop (positive edge triggering)

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 Clocked J-K Flip-Flop
•J-K flip-flop is a refinement of the R-S flip-flop.
•The indeterminate state of the R-S flip-flop is defined in the J-K
flip-flop (when S=1 and R= 1).
•We consider the inputs of S-R flip-flop as S = JQ’ and R = KQ.
Inputs Outputs

CP J K Q Q’

X 0 0 No change
CP 1 0 1 0 1

1 1 0 1 0

1 1 1 Toggle
(a) Logic diagram (b) Truth table
Figure 5.8: J- K Flip - Flop
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 4/27 Th
• 2,5,11,26,36

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 J-K Flip-Flop

Figure 5.9: J-K Flip-Flop

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 Race around condition

How to avoid race around condition??

i. Using Master-Slave J-K flip-flop.
ii. Using the Edge triggering flip-
flop
iii. T/2 < propagation delay for
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Figure: Time diagram of Edge triggered J-K flip-flop

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 J-K Master Slave F/F
• Master-Slave J-K flip-flop is constructed from two
separate flip-flops. One circuit serves as a master
and the other as a slave and the overall circuit is
referred to as a master slave flip-flop.
• The master section is basically a gated latch and
slave is also the same except that it is clocked an
inverted clock pulse and is controlled by outputs
of master section rather than by external J-K
inputs.
• Characteristic table is same as J-K Flip-flop.
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 (a) Block diagram

(b) Logic diagram

Figure 5.10: Master Slave J-K flip-flop.

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 T Flip-Flop
• It is obtained by connecting J and K inputs
together; so only one input denoted by ‘T’.
•There is only two input conditions
J=K=1
J=K=0
• T flip-flop is used for counter.
Q(t) T Q(t + 1)
0 0 0 (a) Block diagram
0 1 1 K
1 0 1
1 1 0
(C) Characteristic table

(b) Logic diagram

Figure 5.11: T Flip-Flop
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Characteristic Table

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 Excitation Table
A table that lists required inputs for a given change of state
( present to next state) is called an excitation table.

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 Flip-Flop Conversion
• Steps:
i. Identify desired flip-flop and available (given) flip-
flop.
ii. Make the characteristic table of desired flip-flop.
iii. Fill the excitation table of available flip-flop for each
combination of present state and next state.
iv. Get the simplified expression for each excitation
input of given flip-flop.
o If necessary use k-map for simplification.
v. Draw the circuit.
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 S-R Flip-Flop to Other Flip-Flop Conversion
S-R F/F to D F/F S-R Flip-Flop to J-K Flip-Flop
S-R F/F to J-K F/F o Desired flip-flop J-K
S-R F/F to T F/F o Available flip-flop S-R
Conversion Table KQ(t) For S
J 00 01 11 10
J-K Inputs P.S N.S S-R Inputs 0 0 X 0 0
J K Q(t) Q(t+1) S R
1 1 X 0 1
0 0 0 0 0 X
0 0 1 1 X 0
S = JQ(t)
0 1 0 0 0 X
0 1 1 0 0 1 KQ(t) For R
00 01 11 10
1 0 0 1 1 0 J
1 0 1 1 X 0 0 X 0 1 X

1 1 0 1 1 0 1 0 0 1 0
1 1 1 0 0 1
R = KQ(t)
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 S

Figure: Realization of J-K by S-R flip-flop

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 J-K Flip-Flop to T Flip-Flop
Given flip-flop = J-K
Desired flip-flop = T For J
Conversion Table Q(t)
T 0 1
T F/F
P.S N.S J-K Inputs 0 0 X
Input
T Q(t) Q(t+1) J K 1 X
1
0 0 0 0 X
0 1 1 X 0 J=T
1 0 1 1 X Q(t)
1 1 0 X 1 T 0 1
0 X 0

X 1
1

K=T

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flip-flop by J-K flip-flop 31
 D Flip-Flop to S-R Flip-Flop
Given flip-flop = D SR
Desired flip-flop = S-R 00 01 11 10
Q(t)
0 0 0 X 1
Conversion Table
S-R Inputs P.S N.S D F/F input 1 1 0 X 1
S R Q(t) Q(t + 1) D
D = S + R’Q(t)
0 0 O 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 0
1 0 0 1 1
1 0 1 1 1
1 1 0 Invalid X
1 1 1 Invalid X

Figure: Conversion of D flip-flop to S-R

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 4/29 TH
• 5,48

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Unit 5 End !!!

Any Queries ??

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