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Analog IC Unit 5 Notes

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Analog IC Unit 5 Notes

Uploaded by

Anandakumar A
Copyright
© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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UNIT – V

Faults in Logic Circuits:


• Faults in logic circuits in analog IC design can occur due to various
reasons, including manufacturing defects, process variations,
environmental conditions. Here are some common faults found in analog
IC logic circuits:
1) Stuck-at Faults: These faults occur when a transistor or a node in the circuit
is stuck at a particular logic level regardless of the input conditions. Stuck-at
faults can be caused by manufacturing defects such as oxide shorts.

2) Transition Faults: Transition faults occur due to the inability of a signal to


transition from one logic level to another within the expected time window.
These faults can be caused by timing violations, inadequate drive strength

3) Crosstalk: Crosstalk occurs when signals in adjacent lines interface with


each other, leading to errors in logic levels. Crosstalk can be induced by
capacitive between neighboring lines.
4) Noise-induced Errors: Noise from various sources such as power supply
fluctuations, electromagnetic interference. Noise margins need to be carefully
considered to ensure reliable operation.
5) Temperature variations: Analog ICs are often subject to temperature
variations which can affect the characteristics of the transistors and passive
components.
6) Aging Effects: Overtime, analog ICs may experience performance
degradation due to aging effects such as bias drift, oxide degradation and
electromigration.

Design for testability:

• Design for testability(DFT) refers to the design techniques that make test
generation and test application cost effective.
• DFT methods for digital circuits:
▪ Ad-hoc methods
▪ Structured methods:
❖ Scan
❖ Partial Scan
❖ Boundary Scan

Ad Hoc Techniques:

• One way to increase the testability is to make nodes more accessible at


some cost by physically inserting more access circuits to the original
design.

Ad hoc testing design techniques:

✓ Partition-and-Mux Technique
✓ Initialize Sequential Circuit
✓ Disable Internal Oscillators
✓ Avoid Asynchronous logic
✓ Avoid Delay-Dependent logic

Partition-and-mux Technique:
• Since the sequence of many serial gates, functional blocks, or logic
circuits are difficult to test, such circuits can be partitioned.
• Muxes can be inserted such that some of the primary inputs can be fed to
partitioned parts through multiplexers.
• With this design technique, the number of accessible nodes can be
increased and the number of test pattern can be reduced.
• Circuit partitioning and addition of multiplexers may increase the chip
area and circuit delay.

Initialize Sequential Circuit:

• When the sequential circuit is powered up, its initial state can be random,
unknown state.
• In this case, it is not possible to start the test sequence correctly.
• The state of a sequential circuit can be brought to known state through
initialization.
• The initialization can be easily done by connecting asynchronous preset.
Disable Internal Oscillators and Clocks:

• To avoid synchronization problems during testing, internal oscillators and


clock should be disabled.

Avoid Asynchronous Logic:

• The redundant node cannot be observed since the primary output value cannot
be made dependent on the value of redundant node.

Avoid Delay Dependent Logic:

• Chains of inverters can be used to design in delay times and use AND
operation of their outputs.
• The use of delay-dependent logic should be avoided in design for testability.

Level-Sensitive Scan Design:

• Scan design techniques involves modifying the registers to allow them to be


chained into a long shift register, called Scan chain.
• This approach was introduced by Eichelberger. It is a latch-based design used
at IBM.
• It guarantees race-free and hazard-free system operations as well as testing.
• Level-sensitive scan design is part of an integrated circuit manufacturing test
process.
• It is a DFT scan design method which uses separate system and scan clocks to
distinguish between normal and test mode.

Advantages:

✓ Correct operation independent


✓ FSM is reduced to combinational logic

Boundary Scan:

• It is a method for testing interconnects on printed circuit boards.


• It is also widely used as debugging method .

Partial Scan:

• It is mainly used to test the circuit in which some of the flip-flop are
stitched into scan path.
• The partial scan chain includes flip-flops from status registers, counters.
• A drawback to partial-scan is if a complete scan-path exists, automatic test
pattern generation is simplified and there is no need for an automatic test
pattern.

Advantages:

• The gate overhead is significantly lower for partial-scan.


• It design improve the fault coverage and fault efficiency to adequately high
levels.

Disadvantages:

• It is very small for the full-scan.

Built-in-self-test:(BIST)

• It is a structural test method that adds logic to an IC.


• It consists of a repair and redundancy capability.
• In this technology, each die has spare circuits.
• If a circuit is bad, the defective circuit is disconnected and replaced with a
good one.
• Memory BIST is also used to obtain known good memory stacks for 2.5D/3D
devices
• Logic BIST, or LBIST, uses a Pseudo-Random Pattern Generator to generate
input patterns that are applied to internal scan chains.
• Then, a Multi-Input Signature Register determines whether the signature is
correct or not to tell if all tests passed.

Advantages:

✓ Cost reduction
✓ Time efficiency
✓ Scalability

Disadvantages:

✓ Complexity
✓ Limited fault coverage

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