Y-Chart + D. Gajaski to design most of the logic chips target chip. + Architecture of the processor is defined. + It ismapped onto the chip surface by floor planning 2. The Finite state machine (FSM) is defined for design evolution + Thatare structurally implemented with functional module st as Register, ALU. + These modules are geometrically placed onto the chip suri using CAD tool for automatic module placement followed routing to reduced the area, delay.Y-Chart 3. Module description is defined then individual modules are implemented with leaf cell.(Chips are described in terms of logic gates). + Cell placement and routing is used to interconnect and placed in to proper location. 4. At the last, the detailed Boolean description of leaf cell is defined. + Transistor level implementation of leaf cell is performed and finally mask is generated.VLSI Design Flow: Full-custom Tesecbporhuarh Shorterdesign for performan: time until —ejimproyement lore opportunity for performance improvement Critical Performance Longer design ‘ime atl = ——! erin Design Time FIGURFE 1.4. Impact of different VLSI design styles upon the design cycle time : achievable circuit performance.Critical Performance Cont Longer design time for Missed technol window = Tower performance in next generation Production Production > Progressive performance improvement of a VLSI product for each ng generation of manufacturing technology > Shorter design cycle times are essential for economic viability.Critical Path > The critical path is the longest path in the circuit that limits the clock speed. ~ The critical path is defined as the path between an input and an output with the maximum delay > Any further delay in this path slows down the entire operation of the design Critical Path Short Bath — supine Critical (Long) Path:(t,, = 26,4 sp + 4a or 3 Short Path: £, sateTiming Analysis Timing analysis basically means > Measuring the speed of the circuit. e.g.. clock speed > Estimation of critical delay > Slack determination > Critical path identification The main aspects of timing analysis are to ensure that » the circuit meets the timing specifications > there are no functional violations due to timing error (e.g., 0Worst Case Timing Analys In order to identify the worst delay. we need to define two important values: Arrival Time at a node (AT): And Required Arrival Time at node (RAT): y Arrival Time at a node (AT): The longest path from the source to the node. After that we need to compute ATs at each node using below expression AT(v) ca AAT(u)+1(u,v)) where F/(v) is the fan in nodes, and r(v,v) is the delay between w and v i ag ae aay ‘se ¥ r coeWorst Case Timing Analys > Required Arrival Time at node (RAT): the latest time the signal is allowed to leave the node to make it to the sink in time. aren CBee") — where FO(v) are the fanout nodes, and a(w,v) is the delay between w and v Slack at node n is defined as: Slack(n) = RAT(n) — AT(n) <2 3 o(0.2) — Ig a’ 1) J (0.25) (0.1) Combinational circuit as DAG (Direct Aeyelic Graph) a-= KX a v (0) (0.1) (0.2) Le Bor (0) (0.3) (0.25) NX QeCompute AATs at each node: LA 100) GN LOD where FJ(v) is the fanin nodes, and ‘(,v) is the delay between and v (AATS of inputs are given) Be taser AATsO ATS; Bb en ay (0.3) (0.25) an \ : EE —en Oe | AaTs 06 ats 3g mm OoExpected gate Wire RATS delay delay Compute RATs at each node: RAT(V) =) RATs at w = (5.9 - 0) -0.2 = where FO(v) are the es nodes. Oo (u,v) is the delay RATS atz=(5.3-2)- 0.256305 between 1 and v RATs at y = (5.3-2) -0.2 = 3.1 RATS at x = (3.05-2) -0.3=0-75 RATs at c = (3.05-2) -0.1 =0.95 RATS at b = (0.75-1) -0.1 RATS at a = (3.1-2) -0.1! wv RaTs at s = -0.35 SL K-06 G- 0.» rar o7s #Q- 02) N\ \ (€O— 01 —> 2) RAT 0.95 RAT 3.05 (RATS of outputs are given) RAT 0.95 (0.15) © (0.1)Compute slacks at each node: slack(v) = RAT(v)— AAT(v) (0.15) Aa R31 (0) (0.1) $0.1 (0.2) or 6G Be 0) Rhos als See Bee BI 08) S358 gos OQ p) S035 $035 y= ~0f-? - ow is” A34 e R095” R305 $0.38 $5.35The worst path is shown using blue line = a (a) — (0.15) —>f y) 7K Rees (o.1) BS 0.2) $2 Noy £2 & ME $035 %) 55 35 $-0.35 a] Bhs A34 R095 R3.05 $0.35 $70.35Overview of Design Hierarchy > Use divide and conquer techniques. > Dividing a module into several sub-modules > Till the complexity of smaller part become manageable. 16 bit adder 4 bit adder Half adderEa earners er onyLevel of AbstractionRegularity, Modularity and Locality Regularity: indicates that the decomposition process must not produce a large number of blocks, and the blocks need to be similar as much as possible. = Anarray structure normally has a good regularity Modularity: It means that the functional blocks must have well-defined interfaces and functionality. — Modular design allows different modules to be designed concurrently and also enables design reuse. Locality Hierarchical decomposition must also consider the locality of the functional blocks — The decomposition should be such that the blocks, exch: frequently, must be close to each other in order to reduce the lengthDesign Style Depending on the application, Cost of production and volume of production. There are different VLSI design style that are followed to implement a chip Each of the design style has its own advantages and disadvantag s and it is chosen based on the target application. The commonly used design style are Field Programmable Gate Array (FPGA) Design Gate Array Design Standard Cell based Design Semi-custom Design Full custom design Design Style fimFPGA ee + Fully fabricated IC chip in which the », interconnections can be programmed tog implement different functions. a =. a + Has thousand of logic gates to implement any logic fimetion. a a + The three main components are + VO buffer, Array of CLBs (Configurable logic blocks), Programmable interconnects + Used for fast prototyping, cost effective chip design especially for low volume applicationFPGA First behavioral netlist is written to describe the functionality of the design (HDL) The netlist is synthesized to come up with the gate level design. Map the logic blocks into available logic cells. The process mapping. s called as technology Followed by placement and routing to configure CLBs and defined interconnections. Generate the bit stream and download the bit stream into FPGA chip. (Xilinx) rca The FPGA chip can function as desired as long as power is ON reprogrammed.Gate Array Design + The transistors are fabricated in the s fabricated. icon wafer but the interconnects are not The metal mask layers are customized to define the interconnections between the transistor for a targeted functionality. + The GA can be categorized as hanneled (ii) Channel-less (iii) Structured poBSooSSoooooR COLLET rg (i) Rows of transistors and channels Gate Areay Design LOLI feoielsielsiee(ersing a atPee 5 Peer Be er ear ere ens Me g (ii) There are no channels between the rows of transistors iI eI iI eI I eI eI eI eI | eI | eI iI eI I BI i g i g lolelelolelolelolloleoLeTe SoDu SSOUROOUOOO ‘SESSION! Arrays ‘Channet-less ——___ (iii) Either channel or channel less can be used but the only difference is that it includes custom blocks.Standard Cell based design —_§{_§$§|__S Uses the pre-designed, pre-tested, and pre characterized standard cells. The standard cells includes basic logic gates such a stndardcetare AND, OR. NAND. ete. Some mega cells such as multiplexer. full adder, . decoder, ete = Sequential elements such as D-FE. register. ete LO buffer and some special cells. — All these standard cells are designed. tested and characterized and put it in a database, called standard cell library Standard cells are placed in a row to build the Integrated circuit chip This design styles also includes already designed mega modules fixed blocks,Full Custom Design + Designers do not used pre-designed standard cell library. Instead, they design the entire chip from the scratch. As each and every parts are designed. The chips are highly optimized for area, power and delay + Superior to any other design style. + But cycle time is very high compared to other design + Mainly used for high performance and high volume productionSemi Custom Design + Almost all the basic building blocks are used from the standard library. Only few cells are designed from the beginning which are not available in the standard cell library or to be optimized for a specific target This approach is faster compared to full custom design but slower than standard cell based design. Performance wise it is better than standard cell based design but inferior to the full custom design.Design Quality Testability- Designed chips are inserted into PCB or multi chip modules for system applications. + Fabricated chip should be fully testable to ensure that all the chips passing the specified chip test can be inserted in the system. Yield and Manufacturability- Once the test process is assumed to be flawless, the chip yield can be calculated + Number of good tested chips by total no. of tested chip. Reliability- Electromigration. Hot carrier induced aging. oxide breakdown. power and ground bouncing, on-chip noise and crosstalk Technology Updatability-The chip products have to be at: updated to new design rules. + Even without any changes in the chip’s functionality‘ Packaging The integrated circuits (ICs) are fabricated on a wafer in a batch. The bunch of wafers, processed simultaneously, is called a /ot. From the processed water individual ICs called die are separated out by cutting the wafers. A die is then packaged in a plastic or ceramic compound structure to form an IC chip. Packaging Lot Wafer, Die FIGURE 1.11 A schematic of lot, wafer, die, and IC chipCont... In addition to protection. the package serves the following important functions: > it provides electrical signal exchange between the core die and the outside environment: > itacts as a medium for heat dissipation: > it provides power to the die. > But with circuits approaching higher frequencies. > the function of a package is not just limited to the above-mentioned functions. = Cont.Types of IC Packages The IC packages are mainly classified into two types: > Pin-through-hole (PTH) package pins are extended in the vertical direction so that they can be inserted through holes in the cireuit board > Surface-mount technology (SMT) package pins are extended in the horizontal direction so that they can be mounted on the surface of the circuit board. (a (b) FIGURE 1.12 IC package: (a) PH; (b) SMTCMOS Integrated Circuit Almost 90° of the integrated circuits fabricated today use the CMOS technology. CMOS. has outperformed the BJT due to their following superior performances > Low power dissipation U > Low area due to less device requirement > Easy scaling down of MOS device dimensions > Low fabrication cost Digital Logic Design + Digital logic circuit design using CMOS transistors, which are most popular because of Jow power dissipation and less area requirement compared to any other logic circuits. + CMOS logic is a combination of nMOS and pMOS logic. The nMOS and pMOS transistors are both functionally and structurally comple vos wear ci to each other. = + Hence, the combination of nMOS and pMOS is known as complementary MOS or CMOS. oa }CMOS Logic Design + The Inverter: vy, + When the input 4 is 0, ¥ = the nMOS > OFF and ; : — the pMOS transistor is ON —————— — Thus, the output ¥ is pulled ae to Lbeesuse it is connected to Ti + Conversely, when 4 is 1, eee a — the nMOS>ON, fre off = and the pMOS> OFF, ie — and ¥ is pulled down to “f MEDD) PLCMOS Logic Design + The 2-i/p CMOS NAND Gate: + Two series NMOS and two parallel PMOS — Ifeither input A or B is 0.> at least one of the NUOS> OFF — Atleast on of the pMOS transistor is ON. — Thus, the output Y is pulled up to 1 @- + Conversely, when both the inputs 4 and B are | — Both nMOS>ON, 7 — and Both pMOS>OFF. | 7, Cs MOS Logic Design — and J is pulled down to ‘0.” + k-input NAND gates are constructed using k series | nMOS transistors and k parallel pMOS transistors.CMOS Logic Gates The inverter and NAND gates are examples of static CMOS logic gates. also called complementary CMOS gates. In general, a static CMOS gate has an nMOS pull-down network to connect the output to 0 (GND) and pMOS pull-up network to connect the output to | (VDD). The pull-up and pull-down networks in the inverter each consist ofa single transistor. The NAND gate u: pullup network. ‘Two or more transistors in series are ON only if all of the series transistors are ON. ‘Two or more transistors in parallel are ON if any of the parallel transistors are ON. 's a series pull-down network and a parallel EMOS Logie GatesBy using combinations of constructions as shown in Fig.. CMOS combinational gates can be constructed. FIGURE 1.15 Connection and behavior of series and parallel trans|Transmission Gate + By combining an nMOS and a pMOS transistor in parallel, we obtain a switeh that turns on when a | is applied to g in which 0s and Is are both passed in an acceptable fashion. + This a transmission gate or pass gate. + Ina circuit where only a 0 or a 1 has to be passed. the appropriate transistor (n or p) can be deleted. reverting to a single nMOS or pMOS device. Input Output g=0,gb=1 : ae a-7o-b Sea Goes — 0 0 strong 0 : - x g=1,gb=0 3 aetna g=1,9b=0 1 -0-0- strong 1> For any gate it is measured between 50% of input transition to the corresponding 50% of output transition. > This is the time required for a signal to propagate through a gate or net (wire). > For gates, it is the time it takes for a event at the gate input to affect the gate output. > For net it is the delay between the time a signal is first applied to the net and the time it reaches other devices connected to that net. Dee Propaeton Dey > Itis taken as the average of rise time and fall time i.e. tha= (teen *tera)/2. “where ty and tp, are the time taken to switeh from high to low and"Zs The propagation delay times fp and ppp are” Ye a = v boar = t)~ te = Z in tory = t3— th ee —_ v The average propagation delay fpy = v that (tone orn) 2. You awPropagation Delay | Switching Characteristics > Rise time (tise) > The rise time t,;,. is defined here as the time required for the output voltage to rise from the V9», level to Voge, level. > Fall time (tay) > The fall time t,,y is defined here as the time required for the output voltage to drop from the Voos, level to Vio», level. > The voltage levels Vjo0, and Vooo, are defined as Viow = Vou +0-1-(Vou - Vox) Vooss = Vor. +9.9+(Vow ~ Vor)Thus, the output rise and fall times are San = by - U4Ibs cal, ao: Toes pe con [8 ) | (Vas—Vqn) Voc- Vor Die pS (2 ) s—\qn) Vos es) wa mash, ° in ot rae ane op te given > gate widtte = pret ote oy da U - pen emits 1 te lox = Em tow gale onde fheiceor