MVME162P2

VME Embedded Controller

Installation and Use

V162P2A/IH2

Edition of November 2000

 © Copyright 2000 Motorola, Inc.
All rights reserved.
Printed in the United States of America.
Motorola® and the Motorola logo are registered trademarks of Motorola, Inc.
MC68040™ and MC68060™ are trademarks of Motorola, Inc.
IndustryPack™ and IP™ are trademarks of GreenSpring Computers, Inc.
All other products mentioned in this document are trademarks or registered trademarks of
their respective holders.
 Safety Summary
The following general safety precautions must be observed during all phases of operation, service, and repair of this
equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result
in personal injury or damage to the equipment.
The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user
of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the
equipment in your operating environment.

Ground the Instrument.

To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the
equipment is supplied with a three-conductor AC power cable, the power cable must be plugged into an approved
three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground
(safety ground) at the power outlet. The power jack and mating plug of the power cable meet International
Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.

Do Not Operate in an Explosive Atmosphere.

Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes.
Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage.

Keep Away From Live Circuits Inside the Equipment.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other
qualified service personnel may remove equipment covers for internal subassembly or component replacement or any
internal adjustment. Service personnel should not replace components with power cable connected. Under certain
conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, such personnel should
always disconnect power and discharge circuits before touching components.

Use Caution When Exposing or Handling a CRT.

Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent
CRT implosion, do not handle the CRT and avoid rough handling or jarring of the equipment. Handling of a CRT
should be done only by qualified service personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.

Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local
Motorola representative for service and repair to ensure that all safety features are maintained.

Observe Warnings in Manual.

Warnings, such as the example below, precede potentially dangerous procedures throughout this manual. Instructions
contained in the warnings must be followed. You should also employ all other safety precautions which you deem
necessary for the operation of the equipment in your operating environment.

To prevent serious injury or death from dangerous voltages, use extreme

caution when handling, testing, and adjusting this equipment and its
Warning components.
 Flammability
All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating
of 94V-0 by UL-recognized manufacturers.

EMI Caution

This equipment generates, uses and can radiate electromagnetic energy. It

! may cause or be susceptible to electromagnetic interference (EMI) if not
Caution installed and used with adequate EMI protection.

Lithium Battery Caution

This product contains a lithium battery to power the clock and calendar circuitry.

Danger of explosion if battery is replaced incorrectly. Replace battery only

! with the same or equivalent type recommended by the equipment
Caution manufacturer. Dispose of used batteries according to the manufacturer’s
instructions.

Il y a danger d’explosion s’il y a remplacement incorrect de la batterie.

! Remplacer uniquement avec une batterie du même type ou d’un type
Attention équivalent recommandé par le constructeur. Mettre au rebut les batteries
usagées conformément aux instructions du fabricant.

Explosionsgefahr bei unsachgemäßem Austausch der Batterie. Ersatz nur

! durch denselben oder einen vom Hersteller empfohlenen Typ. Entsorgung
Vorsicht gebrauchter Batterien nach Angaben des Herstellers.
 CE Notice (European Community)
Motorola Computer Group products with the CE marking comply with the EMC Directive
(89/336/EEC). Compliance with this directive implies conformity to the following
European Norms:
EN55022 “Limits and Methods of Measurement of Radio Interference Characteristics
of Information Technology Equipment”; this product tested to Equipment Class B
EN50082-1:1997 “Electromagnetic Compatibility—Generic Immunity Standard, Part
1. Residential, Commercial and Light Industry”
System products also fulfill EN60950 (product safety) which is essentially the requirement
for the Low Voltage Directive (73/23/EEC).
Board products are tested in a representative system to show compliance with the above
mentioned requirements. A proper installation in a CE-marked system will maintain the
required EMC/safety performance.
In accordance with European Community directives, a “Declaration of Conformity” has
been made and is on file within the European Union. The “Declaration of Conformity” is
available on request. Please contact your sales representative.

Notice
While reasonable efforts have been made to assure the accuracy of this document,
Motorola, Inc. assumes no liability resulting from any omissions in this document, or from
the use of the information obtained therein. Motorola reserves the right to revise this
document and to make changes from time to time in the content hereof without obligation
of Motorola to notify any person of such revision or changes.
Electronic versions of this material may be read online, downloaded for personal use, or
referenced in another document as a URL to the Motorola Computer Group website. The
text itself may not be published commercially in print or electronic form, edited, translated,
or otherwise altered without the permission of Motorola, Inc.
It is possible that this publication may contain reference to or information about Motorola
products (machines and programs), programming, or services that are not available in your
country. Such references or information must not be construed to mean that Motorola
intends to announce such Motorola products, programming, or services in your country.
 Limited and Restricted Rights Legend
If the documentation contained herein is supplied, directly or indirectly, to the U.S.
Government, the following notice shall apply unless otherwise agreed to in writing by
Motorola, Inc.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in
subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov.
1995) and of the Rights in Noncommercial Computer Software and Documentation clause
at DFARS 252.227-7014 (Jun. 1995).
Motorola, Inc.
Computer Group
2900 South Diablo Way
Tempe, Arizona 85282
 Contents

About This Manual

Summary of Changes .................................................................................................xvi
Overview of Contents ................................................................................................xvi
Comments and Suggestions ......................................................................................xvii
Conventions Used in This Manual...........................................................................xviii

CHAPTER 1 Hardware Preparation and Installation

Introduction................................................................................................................1-1
Getting Started ...........................................................................................................1-1
Overview of Installation Procedure ....................................................................1-1
Equipment Required ...........................................................................................1-2
Guidelines for Unpacking ...................................................................................1-3
ESD Precautions .................................................................................................1-3
Preparing the Board ...................................................................................................1-4
MVME162P2 Configuration ..............................................................................1-5
VME System Controller (J1) ..............................................................................1-7
IP Bus Strobe (J11) .............................................................................................1-7
SCSI Termination (J12) ......................................................................................1-8
IP Bus Clock (J13) ..............................................................................................1-9
SRAM Backup Power Source (J14) .................................................................1-10
Flash Write Protection (J16) .............................................................................1-11
EPROM/Flash Configuration (J20) ..................................................................1-11
MC2 DRAM Size (S3) .....................................................................................1-15
General-Purpose Readable Switch (S4 Pin 5) ..................................................1-16
IP DMA Snoop Control (S5 Pins 1/2) ..............................................................1-18
IP Reset Mode (S5 Pin 3) .................................................................................1-19
Flash Write Enable Mode (S5 Pin 4) ................................................................1-20
MCECC DRAM Size (S6)................................................................................1-21
Installation Instructions............................................................................................1-22
IP Installation on the MVME162P2 .................................................................1-23
MVME162P2 Installation.................................................................................1-23
System Considerations......................................................................................1-25
Serial Connections ............................................................................................1-27

vii
CHAPTER 2 Startup and Operation
Introduction ............................................................................................................... 2-1
Front Panel Switches and Indicators .................................................................. 2-1
Initial Conditions ....................................................................................................... 2-2
Applying Power ......................................................................................................... 2-3
Pre-Startup Checklist................................................................................................. 2-4
Bringing up the Board ............................................................................................... 2-5
Autoboot ............................................................................................................. 2-9
ROMboot.......................................................................................................... 2-10
Network Boot ................................................................................................... 2-11
Restarting the System .............................................................................................. 2-12
Reset ................................................................................................................. 2-12
Abort................................................................................................................. 2-13
Break ................................................................................................................ 2-13
Diagnostic Facilities ................................................................................................ 2-14

CHAPTER 3 162Bug Firmware

Introduction ............................................................................................................... 3-1
162Bug Overview...................................................................................................... 3-1
162Bug Implementation ............................................................................................ 3-3
Memory Requirements ....................................................................................... 3-4
Using 162Bug ............................................................................................................ 3-5
Debugger Commands ................................................................................................ 3-6
Modifying the Environment ...................................................................................... 3-8
CNFG - Configure Board Information Block .................................................... 3-9
ENV - Set Environment........................................................................................... 3-11
Configuring the 162Bug Parameters ................................................................ 3-11
Configuring the IndustryPacks ......................................................................... 3-19

CHAPTER 4 Functional Description

Introduction ............................................................................................................... 4-1
Summary of Features................................................................................................. 4-1
Processor and Memory ....................................................................................... 4-3
I/O Implementation ............................................................................................ 4-3
ASICs ................................................................................................................. 4-4
Block Diagram........................................................................................................... 4-4
Functional Description .............................................................................................. 4-6
Data Bus Structure.............................................................................................. 4-6

viii
 Microprocessor ...................................................................................................4-6
MC68xx040 Cache ......................................................................................4-6
No-VMEbus-Interface Option ............................................................................4-7
Memory Options .................................................................................................4-7
DRAM .........................................................................................................4-7
SRAM..........................................................................................................4-8
About the Battery.........................................................................................4-9
EPROM and Flash Memory ......................................................................4-11
Battery-Backed-Up RAM and Clock................................................................4-12
VMEbus Interface and VMEchip2 ...................................................................4-12
I/O Interfaces ....................................................................................................4-12
Serial Communications Interface ..............................................................4-13
IndustryPack (IP) Interfaces ......................................................................4-13
Ethernet Interface ......................................................................................4-14
SCSI Interface............................................................................................4-15
SCSI Termination ......................................................................................4-15
Local Resources................................................................................................4-15
Programmable Tick Timers .......................................................................4-16
Watchdog Timer ........................................................................................4-16
Software-Programmable Hardware Interrupts...........................................4-16
Local Bus Timeout ....................................................................................4-16
Local Bus Arbiter..............................................................................................4-17
Connectors ........................................................................................................4-18
Remote Status and Control ........................................................................4-18

CHAPTER 5 Pin Assignments

Connector Pin Assignments .......................................................................................5-1
Remote Reset Connector - J2.....................................................................................5-2
IndustryPack A and B Connectors .............................................................................5-2
Ethernet Connector - J9 .............................................................................................5-4
Serial Connector - J17................................................................................................5-4
SCSI Connector - J23.................................................................................................5-5
VMEbus Connectors (P1, P2)....................................................................................5-5

APPENDIX A Specifications
Board Specifications .................................................................................................A-1
Cooling Requirements ..............................................................................................A-2
Special Considerations for Elevated-Temperature Operation ...........................A-3
EMC Regulatory Compliance...................................................................................A-4

ix
APPENDIX B Troubleshooting
Solving Startup Problems ......................................................................................... B-1

APPENDIX C Network Controller Data

Network Controller Modules Supported .................................................................. C-1

APPENDIX D Disk/Tape Controller Data

Controller Modules Supported ................................................................................. D-1
Default Configurations ............................................................................................. D-2
IOT Command Parameters ....................................................................................... D-5

APPENDIX E Related Documentation

MCG Documents .......................................................................................................E-1
Manufacturers’ Documents .......................................................................................E-2
Related Specifications ...............................................................................................E-3

x
 List of Figures

Figure 1-1. MVME162P2 Board Layout ...................................................................1-6

Figure 2-1. MVME162P2/Firmware System Startup ................................................2-3
Figure 4-1. MVME162P2 Block Diagram.................................................................4-5

xi
xii
 List of Tables

Table 1-1. Startup Overview ......................................................................................1-1

Table 1-2. MVME162P2 Configuration Settings ......................................................1-5
Table 1-3. EPROM/Flash Mapping — 128K x 8 EPROMs ....................................1-13
Table 1-4. EPROM/Flash Mapping — 256K x 8 EPROMs ....................................1-13
Table 1-5. EPROM/Flash Mapping — 512K x 8 EPROMs ....................................1-14
Table 1-6. EPROM/Flash Mapping — 1M x 8 EPROMs........................................1-14
Table 1-7. EPROM/Flash Mapping —
1M x 8 EPROMs, Onboard Flash Disabled .....................................................1-14
Table 1-8. MC2 DRAM Size Settings .....................................................................1-16
Table 1-9. Switch S5 Snoop Control Encoding .......................................................1-18
Table 1-10. MCECC DRAM Size Settings..............................................................1-22
Table 2-1. MVME162P2 Front Panel Controls .........................................................2-1
Table 2-2. Software-Readable Switches ....................................................................2-6
Table 3-1. Memory Offsets with 162Bug ..................................................................3-4
Table 3-2. Debugger Commands ...............................................................................3-6
Table 3-3. ENV Command Parameters....................................................................3-11
Table 4-1. MVME162P2 Features .............................................................................4-1
Table 4-2. Local Bus Arbitration Priority ................................................................4-17
Table 5-1. Remote Reset Connector J2 Pin Assignments..........................................5-2
Table 5-2. IndustryPack Interconnect Signals............................................................5-3
Table 5-3. DB15 Ethernet Connector Pin Assignments.............................................5-4
Table 5-4. Serial Connector Pin Assignments ...........................................................5-4
Table 5-5. SCSI Connector J23 Pin Assignments......................................................5-6
Table 5-6. VMEbus Connector P1 Pin Assignments .................................................5-7
Table 5-7. VMEbus Connector P2 Pin Assignment...................................................5-8
Table A-1. MVME162P2 Specifications .................................................................A-1
Table B-1. Troubleshooting MVME162P2 Boards ................................................. B-1
Table E-1. Motorola Computer Group Documents ................................................. E-1
Table E-2. Manufacturers’ Documents .................................................................... E-2
Table E-3. Related Specifications ............................................................................ E-3

xiii
xiv
About This Manual
MVME162P2 VME Embedded Controller Installation and Use provides
instructions for hardware preparation and installation; a board-level
hardware overview; and firmware-related general information and startup
instructions for the MVME162P-242 series of embedded controllers,
known collectively as the ‘‘MVME162P2’’ because they are equipped
with the “Petra” chip and accommodate up to two IP modules.
The “Petra” chip that distinguishes MVME162P2 embedded controllers is
an application-specific integrated circuit (ASIC) which combines the
functions previously covered by the MC2 chip, the IP2 chip, and the
MCECC chip in a single ASIC. As of the publication date, the information
presented in this manual applies to the following MVME162P2 models:

Model Number Characteristics

MVME162P-242L 25MHz 68LC040, 16MB SDRAM w/parity, 4 SIO, 2 DMA IP
MVME162P-242LE 25MHz 68LC040, 16MB SDRAM w/ECC, 4 SIO, 2 DMA IP, Ethernet
MVME162P-242LSE 25MHz 68LC040, 16MB SDRAM w/ECC, 4 SIO, 2 DMA IP,
SCSI/Ethernet
MVME162P-242 25MHz 68040, 16MB SDRAM w/parity, 4 SIO, 2 DMA IP
MVME162P-242E 25MHz 68040, 16MB SDRAM w/ECC, 4 SIO, 2 DMA IP, Ethernet
MVME162P-242SE 25MHz 68040, 16MB SDRAM w/ECC, 4 SIO, 2 DMA IP,
SCSI/Ethernet

If the part number of your board includes a "PA" (for example:

MVME162PA-242L), your board is equipped with a second-generation
Petra ASIC. All other particulars of the board remain the same.
This manual is intended for anyone who designs OEM systems, adds
capability to an existing compatible system, or works in a lab environment
for experimental purposes. A basic knowledge of computers and digital
logic is assumed. To use this manual, you may also wish to become
familiar with the publications listed in the Related Documentation section
in Appendix E.

xv
Summary of Changes
This is the second edition of MVME162P2 Installation and Use. It
supersedes the June 2000 edition and incorporates the following updates.

Date Description of Change

October 2000 In the description of the snoop control switch on page 1-18, entries in the table
concerning boards equipped with the MC68060 processor have been corrected.
October 2000 Several jumper drawings and configuration descriptions in Chapters 1 and 2
have been updated to reflect the current board layout and shipping
configuration.
October 2000 In the descriptions of the MC2 and MCECC DRAM size switches on pages
1-15 and 1-21, the importance of executing env;d after modifying switch
settings has been emphasized.

Overview of Contents
Chapter 1, Hardware Preparation and Installation, provides unpacking
instructions, hardware preparation guidelines, and installation instructions
for the MVME162P2 VME Embedded Controller.
Chapter 2, Startup and Operation, provides information on powering up
the MVME162P2 VME Embedded Controller after its installation in a
system and describes the functionality of the switches, status indicators,
and I/O ports.
Chapter 3, 162Bug Firmware, describes the basics of 162Bug and its
architecture, describes the monitor (interactive command portion of the
firmware) in detail, and gives information on using the debugger and
special commands.
Chapter 4, Functional Description, describes the MVME162P2 VME
Embedded Controller on a block diagram level.
Chapter 5, Pin Assignments, summarizes the pin assignments for the
various groups of interconnect signals on the MVME162P2.

xvi
 Appendix A, Specifications, lists the general specifications for the
MVME162P2 Embedded Controller. Subsequent sections of the appendix
detail cooling requirements and EMC regulatory compliance.
Appendix B, Troubleshooting, includes simple troubleshooting steps to
follow in the event that you have difficulty with your MVME162P2 VME
Embedded Controller.
Appendix C, Network Controller Data, describes the VMEbus network
controller modules that are supported by the 162Bug firmware.
Appendix D, Disk/Tape Controller Data, describes the VMEbus disk/tape
controller modules that are supported by the 162Bug firmware.
Appendix E, Related Documentation, provides all documentation related
to the MVME162P2.

Comments and Suggestions

Motorola welcomes and appreciates your comments on its documentation.
We want to know what you think about our manuals and how we can make
them better. Mail comments to:
Motorola Computer Group
Reader Comments DW164
2900 S. Diablo Way
Tempe, Arizona 85282
You can also submit comments to the following e-mail address:
[email protected]
In all your correspondence, please list your name, position, and company.
Be sure to include the title and part number of the manual and tell how you
used it. Then tell us your feelings about its strengths and weaknesses and
any recommendations for improvements.

xvii
Conventions Used in This Manual
The following typographical conventions are used in this document:
bold
is used for user input that you type just as it appears; it is also used for
commands, options and arguments to commands, and names of
programs, directories and files.
italic
is used for names of variables to which you assign values. Italic is also
used for comments in screen displays and examples, and to introduce
new terms.
courier
is used for system output (for example, screen displays, reports),
examples, and system prompts.
<Enter>, <Return> or <CR>
<CR> represents the carriage return or Enter key.
CTRL
represents the Control key. Execute control characters by pressing the
Ctrl key and the letter simultaneously, for example, Ctrl-d.
A character precedes a data or address parameter to specify the numeric
format, as follows:
$ Specifies a hexadecimal character
0x Specifies a hexadecimal number
% Specifies a binary number
& Specifies a decimal number
An asterisk (∗) following a signal name for signals that are level significant
denotes that the signal is true or valid when the signal is low. An asterisk
(∗) following a signal name for signals that are edge significant denotes
that the actions initiated by that signal occur on high to low transition.

xviii
 1Hardware Preparation and
Installation 1
Introduction
This chapter provides unpacking instructions, hardware preparation
guidelines, and installation instructions for the MVME162P2 VME
Embedded Controller.

Getting Started
This section supplies an overview of startup procedures applicable to the
MVME162P2. Equipment requirements, directions for unpacking, and
ESD precautions that you should take complete the section.

Overview of Installation Procedure

The following table lists the things you will need to do to use this board
and tells where to find the information you need to perform each step. Be
sure to read this entire chapter, including all Cautions and Warnings,
before you begin.
Table 1-1. Startup Overview
What you need to do... Refer to...
Unpack the hardware. Guidelines for Unpacking on page 1-3.
Reconfigure jumpers or switches Preparing the Board on page 1-4.
on the MVME162P2 board as
necessary.
Ensure that IP modules are IP Installation on page 1-23.
properly installed on the
MVME162P2 board.
Install the MVME162P2 board in MVME162P2 Installation on page 1-23.
a chassis.
Connect a display terminal. Serial Connections on page 1-27.

1-1
 Hardware Preparation and Installation
1

Table 1-1. Startup Overview (Continued)

What you need to do... Refer to...
Connect any other equipment you Connector Pin Assignments in Chapter 5.
will be using. For more information on optional devices and equipment, refer
to the documentation provided with the equipment.
Power up the system. Applying Power on page 2-3.
Solving Startup Problems on page B-1.
Note that the firmware initializes Bringing Up the Board on page 2-5.
and tests the board. You may also wish to obtain the 162Bug Firmware User’s
Manual, listed in the Related Documentation appendix.
Initialize the system clock. Debugger Commands on page 3-6.
Examine and/or change Modifying the Environment on page 3-8.
environmental parameters.
Program the board as needed for Programmer’s Reference Guide, listed in the Related
your applications. Documentation appendix.

Equipment Required
The following equipment is necessary to complete an MVME162P2
system:
❏ VME system enclosure
❏ System console terminal
❏ Operating system (and / or application software)
❏ Disk drives (and / or other I/O) and controllers

1-2 Computer Group Literature Center Web Site

 Getting Started
1

Guidelines for Unpacking

Note If the shipping carton is damaged upon receipt, request that the
carrier’s agent be present during the unpacking and inspection of
the equipment.
Unpack the equipment from the shipping carton. Refer to the packing list
and verify that all items are present. Save the packing material for storing
and reshipping of equipment.

Avoid touching areas of integrated circuitry; static discharge can damage

! circuits.
Caution
ESD Precautions
This section applies to all hardware installations you may perform that
involve the MVME162P2 board.
Use ESD Motorola strongly recommends the use of an antistatic wrist strap and a
conductive foam pad when you install or upgrade the board. Electronic
components can be extremely sensitive to ESD. After removing the board
from the chassis or from its protective wrapper, place the board flat on a
Wrist Strap grounded, static-free surface, component side up. Do not slide the board
over any surface.
If no ESD station is available, you can avoid damage resulting from ESD
by wearing an antistatic wrist strap (available at electronics stores). Place
the strap around your wrist and attach the grounding end (usually a piece
of copper foil or an alligator clip) to an electrical ground. An electrical
ground can be a piece of metal that literally runs into the ground (such as
an unpainted metal pipe) or a metal part of a grounded electrical appliance.
An appliance is grounded if it has a three-prong plug and is plugged into a
three-prong grounded outlet. You cannot use the chassis in which you are
installing the MVME162P2 itself as a ground, because the enclosure is
unplugged while you work on it.

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 Hardware Preparation and Installation
1

Turn the system’s power off before you perform these procedures. Failure
! to turn the power off before opening the enclosure can result in personal
Warning injury or damage to the equipment. Hazardous voltage, current, and energy
levels are present in the chassis. Hazardous voltages may be present on
power switch terminals even when the power switch is off. Never operate
the system with the cover removed. Always replace the cover before
powering up the system.

Preparing the Board

To produce the desired configuration and ensure proper operation of the
MVME162P2, you may need to reconfigure hardware to some extent
before installing the board.
Most options on the MVME162P2 are under software control: By setting
bits in control registers after installing the module in a system, you can
modify its configuration. (The MVME162P2 registers are described in
Chapter 3 under ENV – Set Environment, and/or in the MVME1X2P2 VME
Embedded Controller Programmer's Reference Guide as listed under
“Related Documentation” in Appendix E.)
Some options, though, are not software-programmable. Such options are
either set by configuration switches or are controlled through physical
installation or removal of header jumpers on the base board.

1-4 Computer Group Literature Center Web Site

 Preparing the Board
1

MVME162P2 Configuration
Figure 1-1 illustrates the placement of the jumper headers, connectors,
configuration switches, and various other components on the
MVME162P2. Manually configurable jumper headers and configuration
switches on the MVME162P2 are listed in the following table.

Table 1-2. MVME162P2 Configuration Settings

Function Factory Default

VME System Controller (J1) on page 1-7 2-3

IP Bus Strobe (J11) on page 1-7 No Jumper

SCSI Termination (J12) on page 1-8 Jumper On

IP Bus Clock (J13) on page 1-9 1-2

SRAM Backup Power Source (J14) on page 1-10 1-3, 2-4

Flash Write Protection (J16) on page 1-11 Jumper On

EPROM/Flash Configuration (J20) on page 1-11 5-6, 9-11, 8-10

MC2 DRAM Size (S3) on page 1-15 Off-Off-Off

General-Purpose Readable Switch (S4 Pin 5) on page 1-16 On

IP DMA Snoop Control (S5 Pins 1/2) on page 1-18 On-On

IP Reset Mode (S5 Pin 3) on page 1-19 On

Flash Write Enable Mode (S5 Pin 4) on page 1-20 On

MCECC DRAM Size (S6) on page 1-21 On-Off-On

J15 (also J24, if present) is a PLD programming header for lab or factory
use. It has no user function.

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 Computer Group Literature Center Web Site
P1 P2
A1 A32 A1 A32
B1 B32 B1 B32
C1 C32 C1 C32
L11
L10
J8 J6
R58 R75 R101
J11 J16
2 XU2 2
1 1

Figure 1-1. MVME162P2 Board Layout

16 15
XU1
J20
6 5
2 1
J14
S4 2 1
BT1
J5 J7 S6 S5 S3
J13
40 1
3
J4 59 2 1
40 1
J3
59 2 R157
J1
Hardware Preparation and Installation

19 3 1
J2
20 J12 R245
1 2
9 1
J15
10 2 J17
DS2 DS4
J23
S1 S2
DS1 DS3
FUSES SCON J9
MVME162

FAIL RUN

ABORT

RESET
ETHERNET PORT SCSI INTERFACE CONSOLE 1 2 3 4

1-6
2783 0700
1
 Preparing the Board
1

VME System Controller (J1)

The MVME162P2 board is factory-configured in "automatic" system
controller mode with a jumper across J1 pins 2-3. In this configuration, the
MVME162P2 determines whether it is the system controller by its position
on the bus. If the board is located in the first slot from the left, it configures
itself as the system controller. When the board is operating as system
controller, the SCON LED is turned on.
If you want the MVME162P2 to function as system controller in all cases,
move the jumper to pins 1-2. If the MVME162P2 is not to be system
controller under any circumstances, remove the jumper from J1.

Note On MVME162P2 boards without the optional VMEbus interface

(i.e., with no VMEchip2 ASIC), the jumper may be installed or
removed with no effect on normal operation.

J1 J1 J1

3 2 1 3 2 1 3 2 1

System Controller Auto System Controller Not System Controller

(factory configuration)

IP Bus Strobe (J11)

Some IP bus implementations make use of the Strobe∗ signal (pin AA19
on the Petra ASIC) as an input to the IP modules from the Petra IP2 sector.
Other IP interfaces require that the strobe be disconnected.
With a jumper installed between J11 pins 1-2, a programmable frequency
source is connected to the Strobe∗ signal on the IP bus (for details, refer to
the Petra/IP2 chip programming model in the Programmer’s Reference
Guide).

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If the jumper is removed from J11, the strobe line is available for a
sideband type of messaging between IP modules. The Strobe∗ signal is not
connected to any active devices on the board, but it may be connected to a
pull-up resistor.

J11 J11

2 2

1 1

IP Strobe disconnected IP Strobe connected

(Factory configuration)

SCSI Termination (J12)

The MVME162P2 provides terminators for an SCSI bus. The SCSI
terminators are enabled/disabled by a jumper on header J12. The SCSI
terminators may be configured as follows.

J12 J12

1 2 1 2

Onboard SCSI Bus Terminators disabled Onboard SCSI Bus Terminators enabled
(Factory configuration)

Note If the MVME162P2 is to be located at either end of an SCSI bus,

the SCSI bus terminators must be enabled.

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IP Bus Clock (J13)

J13 selects the speed of the IP bus clock. The IP bus clock speed may be
8MHz or it may be set synchronous to the processor bus clock (25MHz for
the MC68040 and MC68LC040). The default factory configuration has a
jumper installed on pins 1-2, denoting an 8MHz clock.
If the jumper is installed on J13 pins 2-3, the IP bus clock speed matches
that of the processor bus clock (25MHz), allowing the IP module to pace
the MPU. Whether the setting is 8MHz or the processor bus clock speed,
all IP ports operate at the same speed.

The setting of the IP32 bit in the Control/Status registers (Petra IP2 sector,
! register at offset $1D, bit 0) must correspond to that of the jumper. The bit
Caution is cleared (0) for 8MHz, or set (1) to match the processor bus clock speed.
If the jumper and the CSR bit are not configured the same, the board may
not run properly.

J13 J13

1 2 3 1 2 3

Bus Clock = 8MHz Bus Clock = Processor Bus Clock

(Factory configuration) (from MPU Bus Clock)

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SRAM Backup Power Source (J14)

Header J14 determines the source for onboard static RAM backup power.
The MVME162P2 is factory-configured to use VMEbus +5V standby
voltage as a backup power source for the SRAM (i.e., jumpers are installed
across pins 1-3 and 2-4). To select the onboard battery as the backup
power source, install the jumpers across pins 3-5 and 4-6.

Note For MVME162P2s without the optional VMEbus interface (i.e.,

without the VMEchip2 ASIC), you must select the onboard
battery as the backup power source.

Removing all jumpers may temporarily disable the SRAM. Do not remove
! all jumpers from J14, except for storage.
Caution

J14 J14 J14

6 5 6 5 6 5

2 1 2 1 2 1

Primary Source Onboard Battery Backup Power Disabled Primary Source VMEbus +5V STBY
Secondary Source Onboard Battery (For storage only) Secondary Source VMEbus +5V STBY
(Factory configuration)

J14 J14

6 5 6 5

2 1 2 1

Primary Source VMEbus +5V STBY Primary Source Onboard Battery

Secondary Source Onboard Battery Secondary Source VMEbus +5V STBY

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Flash Write Protection (J16)

When the Flash write-enable jumper is installed (factory configuration),
Flash memory can be written to via the normal software routines. When
the jumper is removed, Flash memory is not writable.

J16 J16

2 2

1 1

Flash write-protected Flash write-enabled

(Factory configuration)

EPROM/Flash Configuration (J20)

The MVME162P2 can be ordered with 2MB of Flash memory and two
EPROM sockets ready for the installation of the EPROMs, which may be
ordered separately. The EPROM locations are standard JEDEC 32-pin DIP
sockets. The EPROM sockets accommodate four jumper-selectable
densities (128 Kbit x 8; 256 Kbit x 8; 512 Kbit x 8 — the default
configuration; 1 Mbit x 8) and also permit disabling of the Flash memory.
Header J20 provides eight jumper locations to configure the EPROM
sockets.

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J20 J20

16 15 16 15

J20

16 15

2 1 2 1

CONFIGURATION 1: 128K x 8 EPROMs CONFIGURATION 3: 512K x 8 EPROMs

(FACTORY DEFAULT)

J20 J20

16 15 16 15
2 1

CONFIGURATION 2: 256K x 8 EPROMs

2 1 2 1

CONFIGURATION 4: 1M x 8 EPROMs CONFIGURATION 5: 1M x 8 EPROMs

ONBOARD FLASH DISABLED

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The next five tables show the address range for each EPROM socket in all
five configurations. GPI3 (S4, switch segment 5) is a control bit in the
MC2 General-Purpose Inputs register in the Petra ASIC that determines
whether reset code is fetched from Flash memory or from EPROMs. (For
particulars on GPI3, refer to the Programmer’s Reference Guide.)

Table 1-3. EPROM/Flash Mapping — 128K x 8 EPROMs

GPI3 Address Range Device Accessed

$FF800000 - $FF81FFFF EPROM A (XU1)
Set to OFF 1 $FF820000 - $FF83FFFF EPROM B (XU2)
$FFA00000 - $FFBFFFFF Onboard Flash
$FF800000 - $FF9FFFFF Onboard Flash
Set to ON 0 $FFA00000 - $FFA1FFFF EPROM A (XU1)
$FFA20000 - $FFA3FFFF EPROM B (XU2)

Table 1-4. EPROM/Flash Mapping — 256K x 8 EPROMs

GPI3 Address Range Device Accessed

$FF800000 - $FF83FFFF EPROM A (XU1)
Set to OFF 1 $FF840000 - $FF87FFFF EPROM B (XU2)
$FFA00000 - $FFBFFFFF Onboard Flash
$FF800000 - $FF9FFFFF Onboard Flash
Set to ON 0 $FFA00000 - $FFA3FFFF EPROM A (XU1)
$FFA40000 - $FFA7FFFF EPROM B (XU2)

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Table 1-5. EPROM/Flash Mapping — 512K x 8 EPROMs

GPI3 Address Range Device Accessed

$FF800000 - $FF87FFFF EPROM A (XU1)
Set to OFF 1 $FF880000 - $FF8FFFFF EPROM B (XU2)
$FFA00000 - $FFBFFFFF Onboard Flash
$FF800000 - $FF9FFFFF Onboard Flash
Set to ON 0 $FFA00000 - $FFA7FFFF EPROM A (XU1)
$FFA80000 - $FFAFFFFF EPROM B (XU2)

Table 1-6. EPROM/Flash Mapping — 1M x 8 EPROMs

GPI3 Address Range Device Accessed

$FF800000 - $FF8FFFFF EPROM A (XU1)
Set to OFF 1 $FF900000 - $FF9FFFFF EPROM B (XU2)
$FFA00000 - $FFBFFFFF Onboard Flash
$FF800000 - $FF9FFFFF Onboard Flash
Set to ON 0 $FFA00000 - $FFAFFFFF EPROM A (XU1)
$FFB00000 - $FFBFFFFF EPROM B (XU2)

Table 1-7. EPROM/Flash Mapping — 1M x 8 EPROMs, Onboard Flash

Disabled

GPI3 Address Range Device Accessed

$FF800000 - $FF8FFFFF EPROM A (XU1)
Set to OFF 1 $FF900000 - $FF9FFFFF EPROM B (XU2)
Not used Onboard Flash
Not used Onboard Flash
Set to ON 0 $FF800000 - $FF8FFFFF EPROM A (XU1)
$FF900000 - $FF9FFFFF EPROM B (XU2)

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MC2 DRAM Size (S3)

MVME162P2 boards use SDRAM (Synchronous DRAM) in place of
DRAM. The MVME162P2’s 16/32MB synchronous SDRAM is
configurable to emulate either of the following memory models:
❏ 1MB, 4MB, 8MB, or 16MB shared parity-protected DRAM
❏ 4MB, 8MB, 16MB, or 32MB ECC-protected DRAM
The two memory controllers modeled in the Petra ASIC duplicate the
functionality of the “parity memory controller” found in MC2 ASICs as
well as that of the “single-bit error correcting/double-bit error detecting”
memory controller found in MCECC ASICs. Board firmware will
initialize the memory controller as appropriate.
If the Petra ASIC is supporting MVME1X2P4 functionality, firmware will
enable the parity (MC2) memory controller model. If the Petra ASIC is
supporting MVME162P2 functionality, firmware will enable either the
parity or the MCECC memory controller model, depending on the board
configuration. Board configuration is a function of switch settings and
resistor population options.
S3 comes into play in the MC2 memory controller model. S3 is a four-
segment slide switch whose lower three segments establish the size of the
parity DRAM (segment 4 is not used.) Refer to the illustration and table
below for specifics.
.

S3
ON OFF

MC2 DRAM SIZE

16MB
(factory configuration)

2734 0004

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Table 1-8. MC2 DRAM Size Settings

S3 S3 S3 MC2 DRAM
Segment 1 Segment 2 Segment 3 Size
ON ON ON 1MB
OFF ON ON 4MB
OFF ON OFF 8MB
OFF OFF ON Disabled
OFF OFF OFF 16MB

Notes As shown in the table, the Petra/MC2 interface supports parity

DRAM emulations up to 16MB. For sizes beyond 16MB, it is
necesary to use the MCECC memory model.
For access to the MCECC registers, you must first disable the
MC2 interface by setting S3 to 001 (Off/Off/On). Further
details on selecting the MCECC emulation can be found
under MCECC DRAM Size (S6).
If you modify the switch settings, you will need to execute env;d
<CR> so that the firmware recognizes the new memory defaults.

General-Purpose Readable Switch (S4 Pin 5)

Switch S4 is similar in function to the general-purpose readable jumper
headers found on earlier MVME162/172 series boards. S4 provides eight
software-readable switch segments. These switches can be read as bits in
a register (at address $FFF4202C) in the MC2 General-Purpose Inputs
register in the Petra ASIC (refer to the Programmer’s Reference Guide for
details). Bit GPI7 is associated with switch segment 1; bit GPI0 is
associated with switch segment 8. The bit values are read as a 0 when the
switch is on, and as a 1 when the switch is off. The MVME162P2 is
shipped from the factory with S4 set to all 0s (all switches set to ON), as
diagrammed below.

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If the MVME162Bug firmware is installed, four bits are user-definable

(i.e., switch segments 1-4). If the MVME162Bug firmware is not installed,
seven bits are user-definable (i.e., segments 1-4 and segments 6-8).

Note Switch segment 5 (GPI3) is reserved to select either the Flash

memory map (switch set to ON) or the EPROM memory map
(switch set to OFF). GPI3 is not user-definable.

S4
162 BUG Installed (default) User Code Installed
OFF ON

GPI7 1 USER-DEFINABLE USER-DEFINABLE

GPI6 USER-DEFINABLE USER-DEFINABLE

GPI5 USER-DEFINABLE USER-DEFINABLE

GPI4 USER-DEFINABLE USER-DEFINABLE

GPI3 5 ON=FLASH; OFF=EPROM ON=FLASH; OFF=EPROM

GPI2 REFER TO DEBUG MANUAL REFER TO DEBUG MANUAL

GPI1 REFER TO DEBUG MANUAL REFER TO DEBUG MANUAL

GPI0 8 REFER TO DEBUG MANUAL REFER TO DEBUG MANUAL

Flash Selected
(factory configuration) 2735 0004

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IP DMA Snoop Control (S5 Pins 1/2)

Segments 1 and 2 of switch S5 define the state of the snoop control bus
when an IP DMA controller is local bus master. As shown in Table 1-9, S5
segment 1 controls Snoop Control signal 1 on the MC680x0 processor. S5
segment 2 controls Snoop Control signal 0. Setting a segment to ON
produces a logical 0; setting it to OFF produces a logical 1.

S5
ON OFF

Snoop inhibited
(factory configuration)
1

2736 0004 (1-3)

S5 varies in function according to the type of processor installed. For

MVME162P2 boards with an MC68040 processor, setting segments 1 and
2 of switch S5 to OFF or leaving both segments set to ON (the factory
configuration) inhibits snooping. Enabling snooping requires one of two
possible ON/OFF combinations, according to the operation desired.
MVME172P2 boards with an MC68060 processor have different snoop
functionality.
The following table lists the snoop operations represented by the settings
of S5 with both types of processor. For further details, refer to the
MC68040 or MC68060 microprocessor user’s manuals listed in the
Related Documentation appendix.
Table 1-9. Switch S5 Snoop Control Encoding
S5-1 S5-2 Requested Snoop Operation
(SC1) (SC0) MC68040 MC68060
On On Snoop disabled Snoop enabled
On Off Source dirty, sink byte/word/longword Snoop disabled
Off On Source dirty, invalidate line Snoop enabled
Off Off Snoop disabled (Reserved) Snoop disabled

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IP Reset Mode (S5 Pin 3)

Segment 3 of switch S5 defines the IP controller model (IP1 or IP2) to be
emulated when the board comes up. With S5 segment 3 set to ON (the
factory configuration), the board initializes in IP2 mode. With S5 segment
3 set to OFF, the board initializes in IP1 mode.

S5
ON OFF

IP2 reset mode

(factory configuration )

2736 0004 (2-3)

In IP2 mode, IP resets occur only in response to a direct software write or

to a power-up reset; the IP reset control bit is not self-clearing.
In IP1 mode, the IP reset control bit clears itself after after a 1msec
interval. IP resets may occur in response to a software write, a power-up
reset, or a local bus reset. For details, refer to the Programmer’s Reference
Guide listed under “Related Documentation” in Appendix E.

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Flash Write Enable Mode (S5 Pin 4)

Segment 4 of switch S5 defines the Flash memory controller model (MC1
or MC2) to be emulated when enabling or disabling Flash memory
accesses on the MVME162P2 board. With S5 segment 4 set to ON (the
factory configuration), the board initializes in MC2 mode. With S5
segment 4 set to OFF, the board initializes in MC1 mode.

S5
ON OFF

4 MC2 Flash write enable mode

(factory configuration )

2736 0004 (3-3)

In MC2 mode, writes to Flash memory are enabled or inhibited by a

control bit at memory location $FFF42042. With the control bit set to 1,
Flash memory is write-enabled.
In MC1 mode, writes to Flash memory are enabled by a memory access to
any location in the range $FFFCC000-$FFFCFFF. Writes to Flash
memory are disabled by a memory access to any location in the range
$FFFC8000-$FFFCBFFF. For details, refer to the Programmer’s
Reference Guide listed under “Related Documentation” in Appendix E.

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MCECC DRAM Size (S6)

MVME1X2P2 boards use SDRAM (Synchronous DRAM) in place of
DRAM. The MVME162P2’s 16/32MB synchronous SDRAM is
configurable to emulate either of the following memory models:
❏ 1MB, 4MB, 8MB, or 16MB shared parity-protected DRAM
❏ 4MB, 8MB, 16MB, or 32MB ECC-protected DRAM
The two memory controllers modeled in the Petra ASIC duplicate the
functionality of the “parity memory controller” found in MC2 ASICs as
well as that of the “single-bit error correcting/double-bit error detecting”
memory controller found in MCECC ASICs. Board firmware will
initialize the memory controller as appropriate.
If the Petra ASIC is supporting MVME1X2P4 functionality, firmware will
enable the parity (MC2) memory controller model. If the Petra ASIC is
supporting MVME1X2P2 functionality, firmware will enable either the
parity or the MCECC memory controller model, depending on the board
configuration. Board configuration is a function of switch settings and
resistor population options.
S6 comes into play in the MCECC memory controller model. S6 is a four-
segment slide switch whose lower three segments establish the size of the
ECC DRAM (segment 4 is not used.) Refer to the illustration and table
below for specifics.

S6
ON OFF

16MB MCECC DRAM

(factory configuration )

2737 0004

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Table 1-10. MCECC DRAM Size Settings

S6 S6 S6 MCECC
Segment 1 Segment 2 Segment 3 DRAM Size
ON ON ON 4MB
ON ON OFF 8MB
ON OFF ON 16MB
ON OFF OFF 32MB
OFF ON ON 64MB

Notes For the MCECC memory model to be enabled, the MC2

emulation must be disabled. You disable the MC2 memory
model by setting the MC2 DRAM size select switch (S3) to
110 (Off/Off/On). Refer to MC2 DRAM Size (S3) for further
details.
The factory default setting for S6 is 16MB (On/Off/On). If
you modify the switch settings, you will need to execute
env;d <CR> so that the firmware recognizes the new
memory defaults.

Installation Instructions
This section covers:
❏ Installation of IndustryPacks (IPs) on the MVME162P2
❏ Installation of the MVME162P2 in a VME chassis
❏ System considerations relevant to the installation. Ensure that an
EPROM device is installed as needed. Before installing
IndustryPacks, ensure that the serial ports and all header jumpers
and configuration switches are set as appropriate.

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IP Installation on the MVME162P2

The MVME162P2 accommodates up to two IndustryPack (IP) modules.
Install the IP modules on the MVME162P2 as follows:
1. Each IP module has two 50-pin connectors that plug into two
corresponding 50-pin connectors on the MVME162P2: J5/J6, J7/J8.
See Figure 2-1 for the MVME162P2 connector locations.
– Orient the IP module(s) so that the tapered connector shells mate
properly. Plug IP_a into connectors J5 and J6; plug IP_b into J7
and J8. If a double-sized IP is used, plug IP_ab into J5, J6, J7,
and J8.
2. Two additional 50-pin connectors (J3 and J4) are provided behind
the MVME162P2 front panel for external cabling connections to the
IP modules. There is a one-to-one correspondence between the
signals on the cabling connectors and the signals on the associated
IP connectors (i.e., J4 has the same IP_a signals as J5; J3 has the
same IP_b signals as J7.
– Connect user-supplied 50-pin cables to J3 and J4 as needed.
(Because of the varying requirements for each different kind of
IP, Motorola does not supply these cables.)
– Bring the IP cables out the narrow slots in the MVME162P2
front panel and attach them to the appropriate external
equipment, depending on the nature of the particular IP(s).

MVME162P2 Installation
With EPROM and IP modules installed and headers or switches properly
configured, proceed as follows to install the MVME162P2 in a VME
chassis:
1. Turn all equipment power OFF and disconnect the power cable
from the AC power source.

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Inserting or removing modules while power is applied could result in

! damage to module components.
Caution

Dangerous voltages, capable of causing death, are present in this

! equipment. Use extreme caution when handling, testing, and adjusting.
Warning
2. Remove the chassis cover as instructed in the user’s manual for the
equipment.
3. Remove the filler panel from the card slot where you are going to
install the MVME162P2.
– If you intend to use the MVME162P2 as system controller, it
must occupy the leftmost card slot (slot 1). The system controller
must be in slot 1 to correctly initiate the bus-grant daisy-chain
and to ensure proper operation of the IACK daisy-chain driver.
– If you do not intend to use the MVME162P2 as system
controller, it can occupy any unused double-height card slot.
4. Slide the MVME162P2 into the selected card slot. Be sure the
module is seated properly in the P1 and P2 connectors on the
backplane. Do not damage or bend connector pins.
5. Secure the MVME162P2 in the chassis with the screws provided,
making good contact with the transverse mounting rails to minimize
RF emissions.
6. On the chassis backplane, remove the INTERRUPT ACKNOWLEDGE
(IACK) and BUS GRANT (BG) jumpers from the header for the card
slot occupied by the MVME162P2.

Note Some VME backplanes (e.g., those used in Motorola "Modular

Chassis" systems) have an autojumpering feature for automatic
propagation of the IACK and BG signals. Step 6 does not apply
to such backplane designs.
7. Connect the appropriate cable(s) to the panel connectors for the
serial ports, SCSI port, and LAN Ethernet port.

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– Note that some cables are not provided with the MVME162P2
and must be made or purchased by the user. (Motorola
recommends shielded cable for all peripheral connections to
minimize radiation.)
8. Connect the peripheral(s) to the cable(s).
9. Install any other required VMEmodules in the system.
10. Replace the chassis cover.
11. Connect the power cable to the AC power source and turn the
equipment power ON.

System Considerations
The MVME162P2 draws power from VMEbus backplane connectors P1
and P2. P2 is also used for the upper 16 bits of data in 32-bit transfers, and
for the upper 8 address lines in extended addressing mode. The
MVME162P2 may not operate properly without its main board connected
to VMEbus backplane connectors P1 and P2.
Whether the MVME162P2 operates as a VMEbus master or as a VMEbus
slave, it is configured for 32 bits of address and 32 bits of data (A32/D32).
However, it handles A16 or A24 devices in the address ranges indicated in
the VMEchip2 chapter of the Programmer’s Reference Guide. D8 and/or
D16 devices in the system must be handled by the MC680x0/MC68LC0x0
software. For specifics, refer to the memory maps in the Programmer’s
Reference Guide.
The MVME162P2 contains shared onboard DRAM whose base address is
software-selectable. Both the onboard processor and offboard VMEbus
devices see this local DRAM at base physical address $00000000, as
programmed by the MVME162Bug firmware. This may be changed via
software to any other base address. Refer to the Programmer’s Reference
Guide for more information.
If the MVME162P2 tries to access offboard resources in a nonexistent
location and is not system controller, and if the system does not have a
global bus timeout, the MVME162P2 waits forever for the VMEbus cycle
to complete. This will cause the system to lock up. There is only one

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situation in which the system might lack this global bus timeout: when the
MVME162P2 is not the system controller and there is no global bus
timeout elsewhere in the system.
Multiple MVME162P2s may be installed in a single VME chassis. In
general, hardware multiprocessor features are supported.

Note If you are installing multiple MVME162P2s in an MVME945

chassis, do not install an MVME162P2 in slot 12. The height of
the IP modules may cause clearance difficulties in that slot
position.
Other MPUs on the VMEbus can interrupt, disable, communicate with,
and determine the operational status of the processor(s). One register of the
GCSR (global control/status register) set in the VMEchip2 ASIC includes
four bits that function as location monitors to allow one MVME162P2
processor to broadcast a signal to any other MVME162P2 processors. All
eight registers of the GCSR set are accessible from any local processor as
well as from the VMEbus.
The following circuits are protected by solid-state fuses that open during
overload conditions and reset themselves once the overload is removed:
❏ IndustryPack +5V (R58)
❏ IndustryPack +12V (R75)
❏ IndustryPack –12V (R101)
❏ Remote reset connector +5V (R90)
❏ SCSI terminator +5V (R157)
❏ LAN AUI +12V (R245)
The FUSES LED illuminates to indicate that all fuses are functioning
correctly. If a solid-state fuse opens, you will need to remove power for
several minutes to let the fuse reset to a closed or shorted condition.

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Serial Connections
The MVME162P2 uses two Zilog Z85230 serial port controllers to
implement the four serial communications interfaces. Each interface
supports:
❏ CTS, DCD, RTS, and DTR control signals
❏ TXD and RXD transmit/receive data signals
Because the serial clocks are omitted in the MVME162P2 implementation,
serial communications are strictly asynchronous. The Z85230s are
interfaced as DTE (data terminal equipment) with EIA-232-D signal
levels. The serial ports are routed to four RJ-45 connectors on the front
panel. The MVME162P2 hardware supports asynchronous serial baud
rates of 110b/s to 38.4Kb/s.
For the pin assignments of the RJ-45 connectors on the front panel, refer
to Chapter 5, Pin Assignments. For additional information on the
MVME162P2 serial communications interface, refer to the Z85230 Serial
Communications Controller Product Brief listed under Manufacturer’s
Documents in Appendix E, Related Documentation. For additional
information on the EIA-232-D interface, refer to the EIA-232-D Standard.

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 2Startup and Operation
2
Introduction
This chapter provides information on powering up the MVME162P2 VME
Embedded Controller after its installation in a system, and describes the
functionality of the switches, status indicators, and I/O ports.
For programming information, consult the MVME1X2P2 VME Embedded
Controller Programmer’s Reference Guide.

Front Panel Switches and Indicators

There are two switches (ABORT and RESET) and four LEDs (FAIL, RUN,
FUSES, SCON) located on the MVME162P2 front panel.
Table 2-1. MVME162P2 Front Panel Controls
Control/Indicator Function
Abort Switch (ABORT) Sends an interrupt signal to the processor. The interrupt is normally
used to abort program execution and return control to the debugger
firmware located in the MVME162P2 Flash memory.
The interrupter connected to the Abort switch is an edge-sensitive
circuit, filtered to remove switch bounce.
Reset Switch (RESET) Resets all onboard devices. Also drives a SYSRESET∗ signal if the
MVME162P2 is system controller. SYSRESET∗ signals may be
generated by the Reset switch, a power-up reset, a watchdog
timeout, or by a control bit in the Local Control/Status Register
(LCSR) in the VMEchip2 ASIC. For further details, refer to
Chapter 4, Functional Description.

2-1
 Startup and Operation

Table 2-1. MVME162P2 Front Panel Controls

2
Control/Indicator Function
FAIL LED (DS1, red) Board failure. Lights if a fault occurs on the MVME162P2 board.
RUN LED (DS2, green) CPU activity. Indicates that one of the local bus masters is
executing a local bus cycle.
FUSES LED (DS3, green) Fuse OK. Indicates that +5Vdc, +12Vdc, and –12Vdc power is
available to the LAN and SCSI interfaces and IP connectors.
SCON LED (DS4, green) System controller. Lights when the VMEchip2 ASIC is functioning
as VMEbus system controller.

Initial Conditions
After you have verified that all necessary hardware preparation has been
done, that all connections have been made correctly, and that the
installation is complete, you can power up the system. Applying power to
the system (as well as resetting it) triggers an initialization of the
MVME162P2’s MPU, hardware, and firmware along with the rest of the
system.
The Flash-resident firmware initializes the devices on the MVME162P2
board in preparation for booting the operating system. The firmware is
shipped from the factory with a set of defaults appropriate to the board. In
most cases there is no need to modify the firmware configuration before
you boot the operating system. For specifics in this regard, refer to Chapter
3 and to the user documentation for the MVME162Bug firmware.

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 Applying Power

Applying Power 2
When you power up (or when you reset) the system, the firmware executes
some self-checks and proceeds to the hardware initialization. The system
startup flows in a predetermined sequence, following the hierarchy
inherent in the processor and the MVME162P2 hardware. The figure
below charts the flow of the basic initialization sequence that takes place
during system startup.

STARTUP Power-up/reset initialization

INITIALIZATION Initialization of devices on the MVME162P2

module/system

POST Power-On Self-Test diagnostics

BOOTING Firmware-configured boot mechanism,

if so configured. Default is no boot.

MONITOR Interactive, command-driven on-line

debugger, when terminal connected.

Figure 2-1. MVME162P2/Firmware System Startup

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 Startup and Operation

2 Pre-Startup Checklist
Before you power up the MVME162P2 system, be sure that the following
conditions exist:
1. Jumpers and/or configuration switches on the MVME162P2 VME
Embedded Controller and associated equipment are set as required
for your particular application.
2. The MVME162P2 board is installed and cabled up as appropriate
for your particular chassis or system, as outlined in Chapter 1.
3. The terminal that you plan to use as the system console is connected
to the console port (serial port 1) on the MVME162P2 module.
4. The terminal is set up as follows:
– Eight bits per character
– One stop bit per character
– Parity disabled (no parity protection)
– Baud rate 9600 baud (the default baud rate of many serial ports
at power-up)
5. Any other device that you wish to use, such as a host computer
system and/or peripheral equipment, is cabled to the appropriate
connectors.
After you complete the checks listed above, you are ready to power up the
system.

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 Bringing up the Board

Bringing up the Board 2

The MVME162P2 comes with MVME162Bug firmware installed. For the
firmware to operate properly with the board, you must follow the steps
below.

Inserting or removing boards with power applied may damage board

! components.
Caution
Turn all equipment power OFF. Refer to MVME162P2 Configuration on
page 1-5 and verify that jumpers and switches are configured as necessary
for your particular application.
1. Configuration switch S4 on the MVME162P2 contains eight
segments, which all affect the operation of the firmware. They are
read as a register (at location $FFF4202C) in the Petra MC2 sector.
(The MVME1X2P2 VME Embedded Controller Programmer’s
Reference Guide has additional information on the Petra MC2
emulation.) The bit values are read as a 0 when the corresponding
switch segment is set to ON, or as a 1 when that segment is set to
OFF.
The default configuration for S4 has S4 set to all 0s (all switch
segments set to ON). The 162Bug firmware reserves/defines the four
lower order bits (GPI0 to GPI3, switch segments 5-8). Table 2-2
describes the bit assignments on S4.
2. Configure header J1 as appropriate for the desired system controller
functionality (always system controller, never system controller, or
self-regulating) on the MVME162P2.
3. Header J11 enables or disables the IP bus strobe function on the
MVME162P2. The factory configuration puts no jumper on J11,
disabling the Strobe∗ signal to the Petra/IP2 chip. Verify that this
setting is appropriate for your application.

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 Startup and Operation

2 Table 2-2. Software-Readable Switches

Bit No. S4 Segment Function
GPI0 8 When set to 1 (high), instructs the debugger to use local static RAM for
its work page (variables, stack, vector tables, etc.).
GPI1 7 When set to 1 (high), instructs the debugger to use the default
setup/operation parameters in ROM instead of the user setup/operation
parameters in NVRAM. The effect is the same as pressing the RESET
and ABORT switches simultaneously.
This feature can be helpful in the event the user setup is corrupted or
does not meet a sanity check. Refer to the ENV command description
for the Flash/ROM defaults.
GPI2 6 Reserved for future use.
GPI3 5 When set to 0 (low), informs the debugger that it is executing out of
Flash memory. When set to 1 (high), it informs the debugger that it is
executing out of the PROM.
GPI4 4 Open to your application.
GPI5 3 Open to your application.
GPI6 2 Open to your application.
GPI7 1 Open to your application.

4. Header J12 enables/disables the SCSI terminators provided on the

MVME162P2. If the board is to be located at either end of an SCSI
bus, the SCSI bus terminators must be enabled. The factory
configuration has a jumper installed on J12, enabling SCSI
termination. Verify that this setting is appropriate for your
application.
5. Header J13 configures the IP bus clock for either 8MHz or the
processor bus clock speed (25MHz for the MC68040 and
MC68LC040). The factory configuration has a jumper installed on
J13 pins 1-2, denoting an 8MHz clock. Verify that this setting is
appropriate for your application.
6. The jumpers on header J14 establish the SRAM backup power
source on the MVME162P2. The factory configuration uses
VMEbus +5V standby voltage as the primary and secondary power

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 Bringing up the Board

source (the onboard battery is disconnected). Verify that this

configuration is appropriate for your application. 2
7. Header J16 defines the state of Flash memory write protection. The
factory configuration has the jumper installed, permitting writes to
Flash. Verify that this setting is appropriate for your application.
8. The EPROM/Flash configuration header, J20, should be jumpered
between pins 5-6, 9-11, and 8-10. This sets it up for a 512Kbit x 8
EPROM density, the factory default.
9. Verify that the settings of configuration switches S3 (MC2 DRAM
size), S5 (IP DMA snoop control, IP Reset mode, and Flash Write
Enable mode), and S6 (MCECC DRAM size) are appropriate for
your memory controller emulation.
10. Refer to the setup procedure for your particular chassis or system for
details concerning the installation of the MVME162P2.

11. Connect the terminal to be used as the 162Bug system console to the
default EIA-232-D port at Serial Port 1 on the front panel of the
MVME162P2. Set the terminal up as follows:
– Eight bits per character
– One stop bit per character
– Parity disabled (no parity)
– Baud rate 9600 baud (the power-up default)
After power-up, you can reconfigure the baud rate of the debug port
by using the 162Bug Port Format (PF) command.

Note Whatever the baud rate, some form of hardware handshaking

— either XON/XOFF or via the RTS/CST line — is desirable
if the system supports it. If you get garbled messages and
missing characters, you should check the terminal to make
sure that handshaking is enabled.
12. If you have equipment (such as a host computer system and/or a
serial printer) to connect to the other EIA-232-D port connectors,
connect the appropriate cables and configure the port(s) as detailed

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 Startup and Operation

in Step 11 above. After power-up, you can reconfigure the port(s)

2 by programming the MVME162P2 Z85230 Serial Communications
Controllers (SCCs) or by using the 162Bug PF command.
13. Power up the system. 162Bug executes some self-checks and
displays the debugger prompt 162-Bug> if the firmware is in Board
mode.
However, if the ENV command has placed 162Bug in System
mode, the system performs a self-test and tries to autoboot. Refer to
the ENV and MENU commands (Table 3-2).
If the confidence test fails, the test is aborted when the first fault is
encountered. If possible, an appropriate message is displayed, and
control then returns to the menu.
14. Before using the MVME162P2 after the initial installation, set the
date and time using the following command line structure:
162-Bug> SET [mmddyyhhmm]|[<+/-CAL>;C]
For example, the following command line starts the real-time clock
and sets the date and time to 10:37 a.m., November 7, 2000:
162-Bug> SET 1107001037
The board’s self-tests and operating systems require that the real-
time clock be running.

Note If you wish to execute the debugger out of Flash and Flash
does not contain 162Bug, you may copy the EPROM version
of 162Bug to Flash memory. To copy the EPROM version of
162Bug to Flash memory, first verify that a jumper is in place
on J16 to enable Flash writes, set switch S4 segment 5 to ON,
and make sure that 162Bug is in Bug mode. Then copy the
EPROM contents to Flash memory with the PFLASH
command as follows:
162-Bug> PFLASH FF800000:80000 FFA00000

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 Bringing up the Board

Then remove the jumper from J16 (if you wish to disable 2
subsequent Flash writes) and slide switch S4 segment 5 back to
OFF. (162Bug always executes from memory location FF800000;
the setting of S4 determines whether that location is in EPROM
or Flash.)

Autoboot
Autoboot is a software routine that is contained in the 162Bug
Flash/EPROM to provide an independent mechanism for booting an
operating system. This autoboot routine automatically scans for controllers
and devices in a specified sequence until a valid bootable device
containing a boot media is found or the list is exhausted. If a valid bootable
device is found, a boot from that device is started. The controller scanning
sequence goes from the lowest controller Logical Unit Number (LUN)
detected to the highest LUN detected. Controllers, devices, and their LUNs
are listed in Appendix D.
At power-up, Autoboot is enabled and (provided that the drive and
controller numbers encountered are valid) the following message is
displayed upon the system console:
Autoboot in progress... To abort hit <BREAK>

A delay follows this message so that you can abort the Autoboot process if
you wish. Then the actual I/O begins: the program designated within the
volume ID of the media specified is loaded into RAM and control passes
to it. If you want to gain control without Autoboot during this time,
however, you can press the <BREAK> key or the software ABORT or
RESET switches.

The Autoboot process is controlled by parameters contained in the ENV

command. These parameters allow the selection of specific boot devices
and files, and allow programming of the Boot delay. Refer to the ENV
command description in Chapter 3 for more details.

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 Startup and Operation

2 Although you can use streaming tape to autoboot, the same

! power supply must be connected to the tape drive, the
Caution controller, and the MVME162P2. At power-up, the tape
controller will position the streaming tape to the load point
where the volume ID can correctly be read and used.
However, if the MVME162P2 loses power but the controller
does not, and the tape happens to be at load point, the
necessary command sequences (attach and rewind) cannot be
given to the controller and the autoboot will not succeed.

ROMboot
As shipped from the factory, 162Bug occupies an EPROM installed in
XU2. This leaves the remaining EPROM socket (XU1) and the Flash
memory available for your use.

Note You may wish to contact your Motorola sales office for
assistance in using these resources.
The ROMboot function is configured/enabled via the ENV command
(refer to Chapter 3) and is executed at power-up (optionally also at reset).
You can also execute the ROMboot function via the RB command,
assuming there is valid code in the memory devices (or optionally
elsewhere on the board or VMEbus) to support it. If ROMboot code is
installed, a user-written routine is given control (if the routine meets the
format requirements).
One use of ROMboot might be resetting the SYSFAIL∗ line on an
unintelligent controller module. The NORB command disables the
function.
For a user’s ROMboot module to gain control through the ROMboot
linkage, four conditions must exist:
❏ Power has just been applied (but the ENV command can change this
to also respond to any reset).

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 Bringing up the Board

❏ Your routine is located within the MVME162P2 Flash/PROM

memory map (but the ENV command can change this to any other 2
portion of the onboard memory, or even offboard VMEbus
memory).
❏ The ASCII string "BOOT" is found in the specified memory range.
❏ Your routine passes a checksum test, which ensures that this routine
was really intended to receive control at powerup.
For complete details on using the ROMboot function, refer to the
Debugging Package for Motorola 68K CISC CPUs User’s Manual.

Network Boot
Network Auto Boot is a software routine in the 162Bug Flash/EPROM
which provides a mechanism for booting an operating system using a
network (local Ethernet interface) as the boot device. The Network Auto
Boot routine automatically scans for controllers and devices in a specified
sequence until a valid bootable device containing boot media is found or
until the list is exhausted. If a valid bootable device is found, a boot from
that device is started. The controller scanning sequence goes from the
lowest controller Logical Unit Number (LUN) detected to the highest LUN
detected. (Refer to Appendix C for default LUNs.)
At power-up, Network Boot is enabled and (provided that the drive and
controller numbers encountered are valid) the following message is
displayed upon the system console:
Network Boot in progress... To abort hit <BREAK>

After this message, there is a delay to let you abort the Auto Boot process
if you wish. Then the actual I/O is begun: the program designated within
the volume ID of the media specified is loaded into RAM and control
passes to it. If you want to gain control without Network Boot during this
time, however, you can press the <BREAK> key or use the software
ABORT or RESET switches.

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 Startup and Operation

Network Auto Boot is controlled by parameters contained in the NIOT

2 and ENV commands. These parameters allow the selection of specific
boot devices, systems, and files, and allow programming of the Boot delay.
Refer to the ENV command description in Chapter 3 for more details.

Restarting the System

You can initialize the system to a known state in three different ways:
Reset, Abort, and Break. Each method has characteristics which make it
more suitable than the others in certain situations.
A special debugger function is accessible during resets. This feature
instructs the debugger to use the default setup/operation parameters in
ROM instead of your own setup/operation parameters in NVRAM. To
activate this function, you press the RESET and ABORT switches at the
same time. This feature can be helpful in the event that your
setup/operation parameters are corrupted or do not meet a sanity check.
Refer to the ENV command description in Chapter 3 for the ROM
defaults.

Reset
Powering up the MVME162P2 initiates a system reset. You can also
initiate a reset by pressing and quickly releasing the RESET switch on the
MVME162P2 front panel, or reset the board in software.
For details on resetting the MVME162P2 board through software, refer to
the MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide.
Both “cold” and “warm” reset modes are available. By default, 162Bug is
in “cold” mode. During cold resets, a total system initialization takes place,
as if the MVME162P2 had just been powered up. All static variables
(including disk device and controller parameters) are restored to their
default states. The breakpoint table and offset registers are cleared. The
target registers are invalidated. Input and output character queues are
cleared. Onboard devices (timer, serial ports, etc.) are reset, and the two
serial ports are reconfigured to their default state.

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 Restarting the System

During warm resets, the 162Bug variables and tables are preserved, as well
as the target state registers and breakpoints. 2
Note that when the MVME162P2 comes up in a cold reset, 162Bug runs
in Board mode. Using the Environment (ENV) or MENU commands can
make 162Bug run in System mode. Refer to Chapter 3 for specifics.
You will need to reset your system if the processor ever halts, or if the
162Bug environment is ever lost (vector table is destroyed, stack
corrupted, etc.).

Abort
Aborts are invoked by pressing and releasing the ABORT switch on the
MVME162P2 front panel. When you invoke an abort while executing a
user program (running target code), a snapshot of the processor state is
stored in the target registers. This characteristic makes aborts most
appropriate for terminating user programs that are being debugged.
If a program gets caught in a loop, for instance, aborts should be used to
regain control. The target PC, register contents, etc., help to pinpoint the
malfunction.
Pressing and releasing the ABORT switch generates a local board condition
which may interrupt the processor if enabled. The target registers,
reflecting the machine state at the time the ABORT switch was pressed, are
displayed on the screen. Any breakpoints installed in your code are
removed and the breakpoint table remains intact. Control returns to the
debugger.

Break
Pressing and releasing the <BREAK> key on the terminal keyboard
generates a "power break”. Breaks do not produce interrupts. The only
time that breaks are recognized is while characters are being sent or
received by the console port. A break removes any breakpoints in your
code and keeps the breakpoint table intact. If the function was entered
using SYSCALL, Break also takes a snapshot of the machine state. This
machine state is then accessible to you for diagnostic purposes.

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 Startup and Operation

In many cases, you may wish to terminate a debugger command before its
2 completion (for example, during the display of a large block of memory).
Break allows you to terminate the command.

Diagnostic Facilities
The 162Bug package includes a set of hardware diagnostics for testing and
troubleshooting the MVME162P2. To use the diagnostics, switch
directories to the diagnostic directory.
If you are in the debugger directory, you can switch to the diagnostic
directory with the debugger command Switch Directories (SD). The
diagnostic prompt 162-Diag> appears. Refer to the Debugging Package
for Motorola 68K CISC CPUs User’s Manual for complete descriptions of
the diagnostic routines available and instructions on how to invoke them.
Note that some diagnostics depend on restart defaults that are set up only
in a particular restart mode. The documentation for such diagnostics
includes restart information.

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 3162Bug Firmware
3
Introduction
The 162Bug firmware is the layer of software just above the hardware. The
firmware supplies the appropriate initialization for devices on the
MVME162P2 board upon power-up or reset.
This chapter describes the basics of 162Bug and its architecture, describes
the monitor (interactive command portion of the firmware) in detail, and
gives information on using the debugger and special commands. A list of
162Bug commands appears at the end of the chapter.
For complete user information about 162Bug, refer to the Debugging
Package for Motorola 68K CISC CPUs User’s Manual and to the
MVME162Bug Diagnostics User’s Manual, listed under Related
Documentation.

162Bug Overview
The firmware for the M68000-based (68K) series of board and system
level products has a common genealogy, deriving from the Bug firmware
currently used on all Motorola M68000-based CPUs. The M68000
firmware version implemented on the MVME162P2 MC68040- or
MC68LC040-based embedded controller is known as MVME162Bug, or
162Bug. It includes diagnostics for testing and configuring IndustryPack
modules.
162Bug is a powerful evaluation and debugging tool for systems built
around MVME162P2 CISC-based microcomputers. Facilities are
available for loading and executing user programs under complete
operator control for system evaluation. The 162Bug firmware provides a
high degree of functionality, user friendliness, portability, and ease of
maintenance.

3-1
 162Bug Firmware

162Bug includes:
❏ Commands for display and modification of memory

3 ❏ Breakpoint and tracing capabilities

❏ A powerful assembler/disassembler useful for patching programs
❏ A “self-test at power-up” feature which verifies the integrity of the
system
In addition, the TRAP #15 system calls make various 162Bug routines that
handle I/O, data conversion, and string functions available to user
programs.
162Bug consists of three parts:
❏ A command-driven user-interactive software debugger, described
in this chapter. It is referred to here as “the debugger” or “162Bug”.
❏ A command-driven diagnostic package for the MVME162P2
hardware, referred to here as “the diagnostics”.
❏ A user interface or debug/diagnostics monitor that accepts
commands from the system console terminal.
When using 162Bug, you operate out of either the debugger directory or
the diagnostic directory.
❏ If you are in the debugger directory, the debugger prompt 162-Bug>
is displayed and you have all of the debugger commands at your
disposal.
❏ If you are in the diagnostic directory, the diagnostic prompt 162-
Diag> is displayed and you have all of the diagnostic commands at
your disposal as well as all of the debugger commands.
Because 162Bug is command-driven, it performs its various operations in
response to user commands entered at the keyboard. When you enter a
command, 162Bug executes the command and the prompt reappears.
However, if you enter a command that causes execution of user target code
(for example, GO), then control may or may not return to 162Bug,
depending on the outcome of the user program.

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 162Bug Implementation

If you have used one or more of Motorola’s other debugging packages, you
will find the CISC 162Bug very similar. Some effort has also been made
to improve the consistency of interactive commands. For example,
delimiters between commands and arguments may be commas or spaces 3
interchangeably.

162Bug Implementation
Physically, 162Bug is contained in a single 27C040 DIP EPROM installed
in socket XU2, providing 512KB (128K longwords) of storage.
Optionally, the 162Bug firmware can be loaded and executed in a
28F016SA Flash memory chip. The executable code is checksummed at
every power-on or reset firmware entry, and the result (which includes a
precalculated checksum contained in the memory devices) is tested for an
expected zero. Users are cautioned against modification of the memory
devices unless precautions for re-checksumming are taken.

Note MVME162P2 boards ordered without the VMEbus interface

are shipped with Flash memory blank (the factory uses the
VMEbus to program the Flash memory with debugger code).
To use the 162Bug package, be sure that switch S4 segment
5 is configured to select the EPROM memory map.
If you subsequently wish to run the debugger from Flash
memory, you must first initialize Flash memory with the
PFLASH command, then reconfigure S4. Refer to Step 14
(Note) under Bringing up the Board on page 2-5 for further
details.

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 162Bug Firmware

Memory Requirements
The program portion of 162Bug is approximately 512KB of code,
consisting of download, debugger, and diagnostic packages and contained
3 entirely in Flash memory or EPROM.
The 162Bug firmware executes from address $FF800000 whether in Flash
or EPROM. If you set switch S4 segment 5 to ON, the address spaces of the
Flash and EPROM are swapped. For MVME162P-242 series boards
(MVME162P2), the factory ship configuration except in the no-VMEbus
case has switch S4 segment 5 set to OFF (162Bug operating out of Flash).
The 162Bug initial stack completely changes 8KB of SRAM memory at
addresses $FFE0C000 through $FFE0DFFF, at power-up or reset.
.

Table 3-1. Memory Offsets with 162Bug

Type of Memory Present Default DRAM Default SRAM
Base Address Base Address
4/8/16/32MB synchronous DRAM (SDRAM). Appears $00000000 $FFE00000
as parity memory at 1/8/16MB, ECC at 32MB. (onboard SRAM)

The synchronous DRAM can be modeled as ECC or parity type, as

indicated above.
The 162Bug requires 2KB of NVRAM for storage of board configuration,
communication, and booting parameters. This storage area begins at
$FFFC16F8 and ends at $FFFC1EF7.
162Bug requires a minimum of 64KB of contiguous read/write memory to
operate. The ENV command controls where this block of memory is
located. Regardless of where the onboard RAM is located, the first 64KB
is used for 162Bug stack and static variable space and the rest is reserved
as user space. Whenever the MVME162P2 is reset, the target PC is
initialized to the address corresponding to the beginning of the user space,
and the target stack pointers are initialized to addresses within the user
space, with the target Interrupt Stack Pointer (ISP) set to the top of the user
space.

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 Using 162Bug

Using 162Bug
162Bug is command-driven; it performs its various operations in response
to commands that you enter at the keyboard. When the 162-Bug> prompt 3
appears on the terminal screen, the debugger is ready to accept debugger
commands. When the 162-Diag> prompt appears on the screen, the
debugger is ready to accept diagnostics commands.
To switch from one mode to the other, enter SD (Switch Directories). To
examine the commands in the directory that you are currently in, use the
Help command (HE).
What you key in is stored in an internal buffer. Execution begins only after
the carriage return is entered. This allows you to correct entry errors, if
necessary, with the control characters described in the Debugging Package
for Motorola 68K CISC CPUs User’s Manual, Chapter 1.
After the debugger executes the command you have entered, the prompt
reappears. However, if the command causes execution of user target code
(for example GO), then control may or may not return to the debugger,
depending on what the user program does.
For example, if a breakpoint has been specified, then control returns to the
debugger when the breakpoint is encountered during execution of the user
program. Alternatively, the user program could return to the debugger by
means of the System Call Handler routine RETURN (described in the
Debugging Package for Motorola 68K CISC CPUs User’s Manual,
Chapter 5, listed in Appendix E, Related Documentation).
A debugger command is made up of the following parts:
❏ The command name, either uppercase or lowercase (e.g., MD or
md).
❏ A port number (if the command is set up to work with more than one
port).
❏ Any required arguments, as specified by the command.
❏ At least one space before the first argument. Precede all other
arguments with either a space or a comma.

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 162Bug Firmware

❏ One or more options. Precede an option or a string of options with

a semicolon (;). If no option is entered, the command’s default
option conditions are used.
3
Debugger Commands
The 162Bug debugger commands are summarized in the following table.
The commands are described in detail in the Debugging Package for
Motorola 68K CISC CPUs User’s Manual.
Table 3-2. Debugger Commands
Command Description
AB Automatic Bootstrap Operating System
NOAB No Autoboot
AS One Line Assembler
BC Block of Memory Compare
BF Block of Memory Fill
BH Bootstrap Operating System and Halt
BI Block of Memory Initialize
BM Block of Memory Move
BO Bootstrap Operating System
BR Breakpoint Insert
NOBR Breakpoint Delete
BS Block of Memory Search
BV Block of Memory Verify
CM Concurrent Mode
NOCM No Concurrent Mode
CNFG Configure Board Information Block
CS Checksum
DC Data Conversion
DMA DMA Block of Memory Move
DS One Line Disassembler
DU Dump S-records
ECHO Echo String
ENV Set Environment to Bug/Operating System

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 Debugger Commands

Table 3-2. Debugger Commands (Continued)

Command Description
GD Go Direct (Ignore Breakpoints)
GN Go to Next Instruction 3
GO Go Execute User Program
GT Go to Temporary Breakpoint
HE Help
IOC I/O Control for Disk
IOI I/O Inquiry
IOP I/O Physical (Direct Disk Access)
IOT I/O "Teach" for Configuring Disk Controller
IRQM Interrupt Request Mask
LO Load S-records from Host
MA Macro Define/Display
NOMA Macro Delete
MAE Macro Edit
MAL Enable Macro Expansion Listing
NOMAL Disable Macro Expansion Listing
MAW Save Macros
MAR Load Macros
MD Memory Display
MENU Menu
MM Memory Modify
MMD Memory Map Diagnostic
MS Memory Set
MW Memory Write
NAB Automatic Network Boot Operating System
NBH Network Boot Operating System and Halt
NBO Network Boot Operating System
NIOC Network I/O Control
NIOP Network I/O Physical
NIOT Network I/O Teach
NPING Network Ping
OF Offset Registers Display/Modify
PA Printer Attach

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 162Bug Firmware

Table 3-2. Debugger Commands (Continued)

Command Description
NOPA Printer Detach
3 PF Port Format
NOPF Port Detach
PFLASH Program FLASH Memory
PS Put RTC Into Power Save Mode for Storage
RB ROMboot Enable
NORB ROMboot Disable
RD Register Display
REMOTE Connect the Remote Modem to CSO
RESET Cold/Warm Reset
RL Read Loop
RM Register Modify
RS Register Set
SD Switch Directories
SET Set Time and Date
SYM Symbol Table Attach
NOSYM Symbol Table Detach
SYMS Symbol Table Display/Search
T Trace
TA Terminal Attach
TC Trace on Change of Control Flow
TIME Display Time and Date
TM Transparent Mode
TT Trace to Temporary Breakpoint
VE Verify S-Records Against Memory
VER Display Revision/Version
WL Write Loop

Modifying the Environment

You can use the factory-installed debug monitor, 162Bug, to modify
certain parameters contained in the MVME162P2’s Non-Volatile RAM
(NVRAM), also known as Battery Backed-Up RAM (BBRAM).

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 Modifying the Environment

❏ The Board Information Block in NVRAM contains various entries

that define operating parameters of the board hardware. Use the
162Bug command CNFG to change those parameters.
❏ Use the 162Bug command ENV to change configurable 162Bug 3
parameters in NVRAM.
The CNFG and ENV commands are both described in the Debugging
Package for Motorola 68K CISC CPUs User’s Manual, listed in Appendix
E, Related Documentation. Refer to that manual for general information
about their use and capabilities.
The following paragraphs present supplementary information on CNFG
and ENV that is specific to the 162Bug firmware, along with the
parameters that you can modify with the ENV command.

CNFG - Configure Board Information Block

Use this command to display and configure the Board Information Block
which resides within the NVRAM. The board information block contains
various elements that correspond to specific operational parameters of the
MVME162P2 board. (Note that although no memory mezzanine is
present on MVME1X2P2 series boards, the on-board memory is modeled
as such for backward compatibility.)
The board structure for the MVME162P2 is as follows:
162-Bug>cnfg
Board (PWA) Serial Number = " "
Board Identifier = " "
Artwork (PWA) Identifier = " "
MPU Clock Speed = " "
Ethernet Address = 0001AF200000
Local SCSI Identifier = " "
Parity Memory Mezzanine Artwork (PWA) Identifier = " "
Parity Memory Mezzanine (PWA) Serial Number = " "
Static Memory Mezzanine Artwork (PWA) Identifier = " "
Static Memory Mezzanine (PWA) Serial Number = " "
ECC Memory Mezzanine #1 Artwork (PWA) Identifier = " "
ECC Memory Mezzanine #1 (PWA) Serial Number = " "
ECC Memory Mezzanine #2 Artwork (PWA) Identifier = " "

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 162Bug Firmware

ECC Memory Mezzanine #2 (PWA) Serial Number = " "

Serial Port 2 Personality Artwork (PWA) Identifier = " "
Serial Port 2 Personality Module (PWA) Serial Number = " "
IndustryPack A Board Identifier = " "
3
IndustryPack A (PWA) Serial Number = " "
IndustryPack A Artwork (PWA) Identifier = " "
IndustryPack B Board Identifier = " "
IndustryPack B (PWA) Serial Number = " "
IndustryPack B Artwork (PWA) Identifier = " "
IndustryPack C Board Identifier = " "
IndustryPack C (PWA) Serial Number = " "
IndustryPack C Artwork (PWA) Identifier = " "
IndustryPack D Board Identifier = " "
IndustryPack D (PWA) Serial Number = " "
IndustryPack D Artwork (PWA) Identifier = " "
162-Bug>

The parameters that are quoted are left-justified character (ASCII) strings
padded with space characters, and the quotes (") are displayed to indicate
the size of the string. Parameters that are not quoted are considered data
strings, and data strings are right-justified. The data strings are padded
with zeros if the length is not met.
The Board Information Block is factory-configured before shipment.
There is no need to modify block parameters unless the NVRAM is
corrupted.
Refer to the MVME1X2P2 VME Embedded Controller Programmer’s
Reference Guide for the actual location and other information about the
Board Information Block. Refer to the Debugging Package for Motorola
68K CISC CPUs User's Manual for a CNFG description and examples.

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 ENV - Set Environment

ENV - Set Environment

Use the ENV command to view and/or configure interactively all 162Bug
operational parameters that are kept in Non-Volatile RAM (NVRAM). 3
Refer to the Debugging Package for Motorola 68K CISC CPUs User’s
Manual for a description of the use of ENV. Additional information on
registers in the MVME162P2 that affect these parameters appears in your
MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide.
Listed and described below are the parameters that you can configure
using ENV. The default values shown are those that were in effect when
this document was published.

Note In the event of difficulty with the MVME162P2, you may

wish to use env;d <CR> to restore the factory defaults as a
troubleshooting aid (see Appendix B).

Configuring the 162Bug Parameters

The parameters that can be configured using ENV are:

Table 3-3. ENV Command Parameters

ENV Parameter and Options Default Meaning of Default
Bug or System environment [B/S] B Bug mode
Field Service Menu Enable [Y/N] N Do not display field service menu.
Remote Start Method Switch B Use both methods [Global Control and Status
[G/M/B/N] Register (GCSR) in the VMEchip2, and
Multiprocessor Control Register (MPCR) in
shared RAM] to pass and execute cross-loaded
programs.
Probe System for Supported I/O Y Accesses will be made to the appropriate
Controllers [Y/N] system buses (e.g., VMEbus, local MPU bus)
to determine presence of supported controllers.

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 162Bug Firmware

Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default
Negate VMEbus SYSFAIL∗ N Negate VMEbus SYSFAIL∗ after successful
3 Always [Y/N] completion or entrance into the bug command
monitor.
Local SCSI Bus Reset on N No local SCSI bus reset on debugger startup.
Debugger Startup [Y/N]
Local SCSI Bus Negotiations A Asynchronous negotiations.
Type [A/S/N]
Industry Pack Reset on Debugger Y IP modules are reset on debugger startup.
Startup [Y/N]
Ignore CFGA Block on a Hard Y Configuration Area (CFGA) Block contents
Disk Boot [Y/N] are disregarded at boot (hard disk only).
Auto Boot Enable [Y/N] N Auto Boot function is disabled.
Auto Boot at power-up only [Y/N] Y Auto Boot is attempted at power-up reset only.
Auto Boot Controller LUN 00 Specifies LUN of disk/tape controller module
currently supported by the Bug. Default is $0.
Auto Boot Device LUN 00 Specifies LUN of disk/tape device currently
supported by the Bug. Default is $0.
Auto Boot Abort Delay 15 The time in seconds that the Auto Boot
sequence will delay before starting the boot.
The delay gives you the option of stopping the
boot by use of the Break key. The time span is
0-255 seconds.
Auto Boot Default String You may specify a string (filename) to pass on
[Y(NULL String)/(String)] to the code being booted. Maximum length is
16 characters. Default is the null string.
ROM Boot Enable [Y/N] N ROMboot function is disabled.
ROM Boot at power-up only Y ROMboot is attempted at power-up only.
[Y/N]
ROM Boot Enable search of N VMEbus address space will not be accessed by
VMEbus [Y/N] ROMboot.
ROM Boot Abort Delay 00 The time in seconds that the ROMboot
sequence will delay before starting the boot.
The delay gives you the option of stopping the
boot by use of the Break key. The time span is
0-255 seconds.

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 ENV - Set Environment

Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default
ROM Boot Direct Starting FF800000 First location tested when the Bug searches for
Address a ROMboot module. 3
ROM Boot Direct Ending Address FFDFFFFC Last location tested when the Bug searches for
a ROMboot module.
Network Auto Boot Enable [Y/N] N Network Auto Boot function is disabled.
Network Auto Boot at power-up Y Network Auto Boot is attempted at power-up
only [Y/N] reset only.
Network Auto Boot Controller 00 Specifies LUN of a disk/tape controller module
LUN currently supported by the Bug. Default is $0.
Network Auto Boot Device LUN 00 Specifies LUN of a disk/tape device currently
supported by the Bug. Default is $0.
Network Auto Boot Abort Delay 5 The time in seconds that the Network Boot
sequence will delay before starting the boot.
The delay gives you the option of stopping the
boot by use of the Break key. The time span is
0-255 seconds.
Network Autoboot Configuration 00000000 The address where the network interface
Parameters Pointer (NVRAM) configuration parameters are to be saved in
NVRAM; these are the parameters necessary
to perform an unattended network boot.
Memory Search Starting Address 00000000 Where the Bug begins to search for a work
page (a 64KB block of memory) to use for
vector table, stack, and variables. This must be
a multiple of the debugger work page, modulo
$10000 (64KB). In a multi-controller
environment, each MVME162P2 board could
be set to start its work page at a unique address
to allow multiple debuggers to operate
simultaneously.

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 162Bug Firmware

Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default
Memory Search Ending Address 00100000 Top limit of the Bug’s search for a work page.
3 If no 64KB contiguous block of memory is
found in the range specified by Memory
Search Starting Address and Memory Search
Ending Address parameters, the bug will place
its work page in the onboard static RAM on the
MVME162P2. Default Memory Search Ending
Address is the calculated size of local memory.
Memory Search Increment Size 00010000 Multi-CPU feature used to offset the location
of the Bug work page. This must be a multiple
of the debugger work page, modulo $10000
(64KB). Typically, Memory Search Increment
Size is the product of CPU number and size of
the Bug work page. Example: first CPU $0 (0 x
$10000), second CPU $10000 (1 x $10000),
etc.
Memory Search Delay Enable N No delay before the Bug begins its search for a
[Y/N] work page.
Memory Search Delay Address FFFFD20F Default address is $FFFFD20F. This is the
MVME162P2 GCSR GPCSR0 as accessed
through VMEbus A16 space; it assumes the
MVME162P2 GRPAD (group address) and
BDAD (board address within group) switches
are set to "on". This byte-wide value is
initialized to $FF by MVME162P2 hardware
after a System or Power-On reset. In a multi-
162P2 environment, where the work pages of
several Bugs reside in the memory of the
primary (first) MVME162P2, the non-primary
CPUs will wait for the data at the Memory
Search Delay Address to be set to $00, $01, or
$02 (refer to the Memory Requirements section
in Chapter 3 for the definition of these values)
before attempting to locate their work page in
the memory of the primary CPU.
Memory Size Enable [Y/N] Y Memory is sized for Self-Test diagnostics.
Memory Size Starting Address 00000000 Default Starting Address is $0.

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 ENV - Set Environment

Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default
Memory Size Ending Address 00100000 Default Ending Address is the calculated size
of local memory. 3
Note
Memory Configuration Defaults.
The default configuration for Dynamic RAM mezzanine boards will position the mezzanine with
the largest memory size to start at the address selected with the ENV parameter "Base Address of
Dynamic Memory". The Base Address parameter defaults to 0. The smaller sized mezzanine will
follow immediately above the larger in the memory map. If mezzanines of the same size and type
are present, the first (closest to the board) is mapped to the selected base address. If mezzanines of
the same size but different type (parity and ECC) are present, the parity type will be mapped to the
selected base address and the ECC type mezzanine will follow. The SRAM does not default to a
location in the memory map that is contiguous with Dynamic RAM.
Base Address of Dynamic 00000000 Beginning address of Dynamic Memory
Memory (Parity and/or ECC type memory). Must be a
multiple of the Dynamic Memory board size,
starting with 0. Default is $0.
Size of Parity Memory 00100000 The size of the Parity type dynamic RAM
mezzanine, if any. The default is the calculated
size of the Dynamic memory mezzanine board.
Size of ECC Memory Board 0 00000000 The size of the first ECC type memory
mezzanine. The default is the calculated size of
the memory mezzanine.
Size of ECC Memory Board 1 00000000 The size of the second ECC type memory
mezzanine. The default is the calculated size of
the memory mezzanine.
Base Address of Static Memory FFE00000 The beginning address of SRAM. The default
is FFE00000 for the onboard 128KB SRAM,
or E1000000 for the 2MB SRAM mezzanine.
If only 2MB SRAM is present, it defaults to
address 00000000.
Size of Static Memory 00080000 The size of the SRAM type memory present.
The default is the calculated size of the
onboard SRAM or an SRAM type mezzanine.

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 162Bug Firmware

Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default
ENV asks the following series of questions to set up the VMEbus interface for the MVME162
3 series modules. You should have a working knowledge of the VMEchip2 as given in the
MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide in order to perform
this configuration. Also included in this series are questions for setting ROM and Flash access
time.
The slave address decoders are used to allow another VMEbus master to access a local resource of
the MVME162P2. There are two slave address decoders set. They are set up as follows:
Slave Enable #1 [Y/N] Y Yes, set up and enable Slave Address Decoder
#1.
Slave Starting Address #1 00000000 Base address of the local resource that is
accessible by the VMEbus. Default is the base
of local memory, $0.
Slave Ending Address #1 000FFFFF Ending address of the local resource that is
accessible by the VMEbus. Default is the end
of calculated memory.
Slave Address Translation 00000000 This register allows the VMEbus address and
Address #1 the local address to differ. The value in this
register is the base address of the local resource
that is associated with the starting and ending
address selection from the previous questions.
Default is 0.
Slave Address Translation Select 00000000 This register defines which bits of the address
#1 are significant. A logical "1" indicates
significant address bits, logical "0" is non-
significant. Default is 0.
Slave Control #1 03FF Defines the access restriction for the address
space defined with this slave address decoder.
Default is $03FF.
Slave Enable #2 [Y/N] N Do not set up and enable Slave Address
Decoder #2.
Slave Starting Address #2 00000000 Base address of the local resource that is
accessible by the VMEbus. Default is 0.
Slave Ending Address #2 00000000 Ending address of the local resource that is
accessible by the VMEbus. Default is 0.
Slave Address Translation 00000000 Works the same as Slave Address Translation
Address #2 Address #1. Default is 0.

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 ENV - Set Environment

Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default
Slave Address Translation Select 00000000 Works the same as Slave Address Translation
#2 Select #1. Default is 0. 3
Slave Control #2 0000 Defines the access restriction for the address
space defined with this slave address decoder.
Default is $0000.
Master Enable #1 [Y/N] Y Yes, set up and enable Master Address
Decoder #1.
Master Starting Address #1 02000000 Base address of the VMEbus resource that is
accessible from the local bus. Default is the
end of calculated local memory (unless
memory is less than 16MB; then this register is
always set to 01000000).
Master Ending Address #1 EFFFFFFF Ending address of the VMEbus resource that is
accessible from the local bus. Default is the
end of calculated memory.
Master Control #1 0D Defines the access characteristics for the
address space defined with this master address
decoder. Default is $0D.
Master Enable #2 [Y/N] N Do not set up and enable Master Address
Decoder #2.
Master Starting Address #2 00000000 Base address of the VMEbus resource that is
accessible from the local bus. Default is
$00000000.
Master Ending Address #2 00000000 Ending address of the VMEbus resource that is
accessible from the local bus. Default is
$00000000.
Master Control #2 00 Defines the access characteristics for the
address space defined with this master address
decoder. Default is $00.
Master Enable #3 [Y/N] Depends on Yes, set up and enable Master Address
calculated Decoder #3. This is the default if the board
size of local contains less than 16MB of calculated RAM.
RAM Do not set up and enable the Master Address
Decoder #3. This is the default for boards
containing at least 16MB of calculated RAM.

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 162Bug Firmware

Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default
Master Starting Address #3 00000000 Base address of the VMEbus resource that is
3 accessible from the local bus. If enabled, the
value is calculated as one more than the
calculated size of memory. If not enabled, the
default is $00000000.
Master Ending Address #3 00000000 Ending address of the VMEbus resource that is
accessible from the local bus. If enabled, the
default is $00FFFFFF, otherwise $00000000.
Master Control #3 00 Defines the access characteristics for the
address space defined with this master address
decoder. If enabled, the default is $3D,
otherwise $00.
Master Enable #4 [Y/N] N Do not set up and enable Master Address
Decoder #4.
Master Starting Address #4 00000000 Base address of the VMEbus resource that is
accessible from the local bus. Default is $0.
Master Ending Address #4 00000000 Ending address of the VMEbus resource that is
accessible from the local bus. Default is $0.
Master Address Translation 00000000 This register allows the VMEbus address and
Address #4 the local address to differ. The value in this
register is the base address of the VMEbus
resource that is associated with the starting and
ending address selection from the previous
questions. Default is 0.
Master Address Translation Select 00000000 This register defines which bits of the address
#4 are significant. A logical "1" indicates
significant address bits, logical "0" is non-
significant. Default is 0.
Master Control #4 00 Defines the access characteristics for the
address space defined with this master address
decoder. Default is $00.
Short I/O (VMEbus A16) Enable Y Yes, Enable the Short I/O Address Decoder.
[Y/N]
Short I/O (VMEbus A16) Control 01 Defines the access characteristics for the
address space defined with the Short I/O
address decoder. Default is $01.

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 ENV - Set Environment

Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default
F-Page (VMEbus A24) Enable Y Yes, Enable the F-Page Address Decoder.
[Y/N] 3
F-Page (VMEbus A24) Control 02 Defines the access characteristics for the
address space defined with the F-Page address
decoder. Default is $02.
ROM Access Time Code 04 Defines the ROM access time. The default is
$04, which sets an access time of five clock
cycles of the local bus.
Flash Access Time Code 03 Defines the Flash access time. The default is
$03, which sets an access time of four clock
cycles of the local bus.
MCC Vector Base 05 Base interrupt vector for the component
VMEC2 Vector Base #1 06 specified. Default: MC2chip = $05, VMEchip2
VMEC2 Vector Base #2 07 Vector 1 = $06, VMEchip2 Vector 2 = $07.
VMEC2 GCSR Group Base D2 Specifies group address ($FFFFXX00) in Short
Address I/O for this board. Default = $D2.
VMEC2 GCSR Board Base 00 Specifies base address ($FFFFD2XX) in Short
Address I/O for this board. Default = $00.
VMEbus Global Time Out Code 01 Controls VMEbus timeout when the
MVME162P2 is system controller. Default $01
= 64 µs.
Local Bus Time Out Code 02 Controls local bus timeout. Default $02 = 256
µs.
VMEbus Access Time Out Code 02 Controls the local-bus-to-VMEbus access
timeout. Default $02 = 32 ms.

Configuring the IndustryPacks

ENV asks the following series of questions to set up IndustryPack modules
(IPs) on MVME162P2s.
The MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide describes the base addresses and the IP register settings. Refer to
that manual for information on setting base addresses and register bits.

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 162Bug Firmware

IP A Base Address = 00000000?

IP B Base Address = 00000000?
IP C Base Address = 00000000?
IP D Base Address = 00000000?
3
Base address for mapping IP modules. Only the upper 16 bits are
significant.
IP D/C/B/A Memory Size = 00000000?

Define the memory size requirements for the IP modules:

Bits IP Register Address

31-24 D FFFBC00F
23-16 C FFFBC00E
15-08 B FFFBC00D
07-00 A FFFBC00C

IP D/C/B/A General Control = 00000000?

Define the general control requirements for the IP modules:

Bits IP Register Address

31-24 D FFFBC01B
23-16 C FFFBC01A
15-08 B FFFBC019
07-00 A FFFBC018

IP D/C/B/A Interrupt 0 Control = 00000000?

Define the interrupt control requirements for the IP modules, channel 0:

Bits IP Register Address

31-24 D FFFBC016
23-16 C FFFBC014
15-08 B FFFBC012
07-00 A FFFBC010

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 ENV - Set Environment

IP D/C/B/A Interrupt 1 Control = 00000000?

Define the interrupt control requirements for the IP modules, channel 1:

Bits IP Register Address 3

31-24 D FFFBC017
23-16 C FFFBC015
15-08 B FFFBC013
07-00 A FFFBC011

If you have specified environmental parameters that will cause an overlap

! condition, a warning message will appear before the environmental
Caution parameters are saved in NVRAM. The important information about each
configurable element in the memory map is displayed, showing where any
overlap conditions exist. This allows you to quickly identify and correct an
undesirable configuration before it is saved.
If an undesirable configuration already exists, you may wish to restore the
factory defaults with env;d <CR>.

ENV warning example:

WARNING: Memory MAP Overlap Condition Exists

S-Address E-Address Enable Overlap M-Type Memory-MAP-Name

$00000000 $FFFFFFFF Yes Yes Master Local Memory (Dynamic RAM)
$FFE00000 $FFE7FFFF Yes Yes Master Static RAM
$01000000 $EFFFFFFF Yes Yes Master VMEbus Master #1
$00000000 $00000000 No No Master VMEbus Master #2
$00000000 $00FFFFFF Yes Yes Master VMEbus Master #3
$00000000 $00000000 No No Master VMEbus Master #4
$F0000000 $FF7FFFFF Yes Yes Master VMEbus F Pages (A24/A32)
$FFFF0000 $FFFFFFFF Yes Yes Master VMEbus Short I/O (A16)
$FF800000 $FFBFFFFF Yes Yes Master Flash/PROM
$FFF00000 $FFFEFFFF Yes Yes Master Local I/O
$00000000 $00000000 No No Master Industry Pack A
$00000000 $00000000 No No Master Industry Pack B
$00000000 $00000000 No No Master Industry Pack C

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 162Bug Firmware

$00000000 $00000000 No No Master Industry Pack D

$00000000 $00000000 No No Slave VMEbus Slave #1
$00000000 $00000000 No No Slave VMEbus Slave #2

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 4Functional Description
4
Introduction
This chapter describes the MVME162P2 VME embedded controller on a
block diagram level. The Summary of Features provides an overview of
the MVME162P2, followed by a detailed description of several blocks of
circuitry. Figure 4-1 shows a block diagram of the overall board
architecture.
Detailed descriptions of other MVME162P2 blocks, including
programmable registers in the ASICs and peripheral chips, can be found in
the MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide (part number VME1X2P2A/PG). Refer to that manual for a
functional description of the MVME162P2 in greater depth.

Summary of Features
The following table summarizes the features of the MVME162P2 VME
embedded controller.
Table 4-1. MVME162P2 Features
Feature Description
Microprocessor MVME162P2: 25MHz MC68040 or MC68LC040 processor
Form factor 6U VMEbus
16/32MB synchronous DRAM (SDRAM), configurable to emulate
1/4/8/16/MB parity-protected DRAM or 4/8/16/32MB ECC-protected
Memory DRAM
512KB SRAM with battery backup
Flash memory MVME162P2: One Intel 28F016SA 1MB or 2MB 8-bit Flash device
EPROM Two 32-pin JEDEC standard PLCC EPROM sockets
8KB NVRAM with RTC, battery backup, and watchdog function (SGS-
Real-time clock
Thomson M48T58)

4-1
 Functional Description

Table 4-1. MVME162P2 Features (Continued)

Feature Description
Switches RESET and ABORT switches on front panel
Four: Board Fail (FAIL), CPU Activity (RUN), System Controller (SCON),
Status LEDs
Fuse Status (FUSES)
4 Four 32-bit tick timers and watchdog timer in Petra ASIC
Timers
Two 32-bit tick timers and watchdog timer in VMEchip2 ASIC
Interrupts Eight software interrupts (on versions with VMEchip2 ASIC)
VME I/O VMEbus P2 connector
Serial I/O Four EIA-232-D serial ports via front panel
Optional Ethernet transceiver interface with DMA via DB15 connector on
Ethernet I/O
front panel
Two IndustryPack interface channels with DMA via 3M connectors behind
IP interface
front panel
SCSI I/O Optional SCSI interface with DMA via front panel
VMEbus system controller functions
VMEbus-to-local-bus interface (A24/A32, D8/D16/D32/block transfer
[D8/D16/D32/D64])
Local-bus-to-VMEbus interface (A16/A24/A32, D8/D16/D32)
VMEbus interface VMEbus interrupter
VMEbus interrupt handler
Global Control/Status Register (GCSR) for interprocessor communications
DMA for fast local memory/VMEbus transfers (A16/A24/A32,
D16/D32/D64)

4-2 Computer Group Literature Center Web Site

 Summary of Features

Processor and Memory

The MVME162P2 is based on the MC68040/MC68LC040
microprocessor. The boards are built with 16MB or 32MB shared DRAM
(SDRAM). Various versions of the MVME162P2 have the SDRAM
configured to model 1MB, 4MB, 8MB, or 16MB of parity-protected
DRAM or 4MB, 8MB, 16MB, or 32MB of ECC-protected DRAM. 4
All boards are available with 512KB of SRAM (with battery backup);
time-of-day clock (with battery backup); an optional Ethernet transceiver
interface; four serial ports with EIA-232-D interface; six tick timers with
watchdog timer(s); two EPROM sockets; 1MB or 2MB Flash memory
(one Flash device); two IndustryPack (IP) interfaces with DMA; optional
SCSI bus interface with DMA; and an optional VMEbus interface (local
bus to VMEbus/VMEbus to local bus, with A16/A24/A32, D8/D16/D32
bus widths and a VMEbus system controller).

I/O Implementation
Peripheral input/output (I/O) signals on the MVME162P2 are routed
through the front panel.
The I/O connections for the four serial ports are implemented with four
RJ45 connectors on the front panel. In addition, the panel has cutouts for
routing of flat cables to the optional IndustryPack modules.
SCSI devices are interfaced via an industry-standard 68-pin panel
connector. The Ethernet interface uses a DB15 connector.

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 Functional Description

ASICs
The following ASICs are used on the MVME162P2:
❏ VMEchip2 ASIC (VMEbus interface). Provides two tick timers, a
watchdog timer, programmable map decoders for the master and
slave interfaces, and a VMEbus-to/from-local-bus DMA controller
4 as well as a VMEbus-to/from-local-bus non-DMA programmed
access interface, a VMEbus interrupter, a VMEbus system
controller, a VMEbus interrupt handler, and a VMEbus requester.
Processor-to-VMEbus transfers are D8, D16, or D32. VMEchip2
DMA transfers to the VMEbus, however, are D16, D32, D16/BLT,
D32/BLT, or D64/MBLT.
❏ Petra ASIC. Combines the functions previously covered by the
MC2 chip, the MCECC chip, and the IP2 chip in a single ASIC.
– MC2 function. Provides a parity DRAM emulation. Also
supplies four tick timers and interfaces to the LAN chip, SCSI
chip, serial port chip, BBRAM, EPROM/Flash, and SRAM.
– MCECC function. Provides an ECC DRAM emulation.
– IP2 function. Provides control and status information for up to
two single-wide or one double-wide IndustryPack module,
which can be plugged into the MVME162P2 main board.

Block Diagram
The block diagram in Figure 4-1 on page 4-5 illustrates the
MVME162P2’s overall architecture.

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 4

4-5
Block Diagram

4 Serial Ports
Optional
RJ45 Front
Panel
Ethernet SCSI
Transceiver Peripherals
VMEbus DB15 Front 68-Pin Front

Figure 4-1. MVME162P2 Block Diagram

A32/24:D64/32/16/08 Panel Panel SCSI
Master/Slave Connector Connector
EIA-232
Transceivers
IndustryPack
I/O 32-Pin
VMEchip2 82596CA 53C710 Dual Z85230
2 Channels JEDEC
VMEbus Ethernet SCSI Serial I/O
EPROM
Interface Controller Coprocessor Controllers
Socket
IP2 MCECC MC2
A32/D32 Flash
Chip Chip Chip
1MB/2MB

http://www.motorola.com/computer/literature
Functions Functions Functions
Petra ASIC
MC68040/MC68LC040 M48T58
16/32MB Battery Backed
or
Synchronous DRAM 8KB RAM/Clock
MC68060/MC68LC060
MPU
4/8/16MB Parity 32MB
DRAM Memory ECC DRAM
Array Memory Array 512KB SRAM
Memory Array
Configuration-Dependent Emulations w/Battery
2498 0003 (2-2)
 Functional Description

Functional Description
This section contains a functional description of the major blocks on the
MVME162P2.

4 Data Bus Structure

The local bus on the MVME162P2 is a 32-bit synchronous bus that is
based on the MC68040 bus, and which supports burst transfers and
snooping. The various local bus master and slave devices use the local bus
to communicate. The local bus is arbitrated by priority type; the priority of
the local bus masters from highest to lowest is: 82596CA LAN, 53C710
SCSI, VMEbus, and MPU. As a general rule, any master can access any
slave; not all combinations pass the common sense test, however. Refer to
the MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide and to the user’s guide for each device to determine its port size, data
bus connection, and any restrictions that apply when accessing the device.

Microprocessor
MVME162P2 models may be ordered with an MC68040 or MC68LC040
microprocessor.
The MC68040 has on-chip instruction and data caches and a floating-point
processor. (A floating-point coprocessor is the major difference between
the MC68040 and MC68LC040.) Refer to the MC68040 user’s manual for
more information.

MC68xx040 Cache
The MVME162P2 local bus masters (VMEchip2, processor, 53C710
SCSI controller, and 82596CA Ethernet controller) have programmable
control of the snoop/caching mode. The IP DMA local bus master’s snoop
control function is governed by the settings of switch S5 segments 1 and 2
(refer to IP DMA Snoop Control (S5 Pins 1/2) on page 1-18). S5
determines the value of the snoop control signal for all IP DMA transfers.
This includes the IP DMA which executes when the DMA control registers
are updated while the IP DMA is operating in command chaining mode.

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 Functional Description

The MVME162P2 local bus slaves that support the snoop/caching mode
are defined in the “Local Bus Memory Map” section of the MVME1X2P2
VME Embedded Controller Programmer’s Reference Guide.

Note As outlined in Table 1-9, the snoop capabilities of the

MC68xx040 processor differ from those of the MC68xx060 used 4
on MVME172P2 series boards. Application software must take
these differences into account.

No-VMEbus-Interface Option
In support of possible future configurations in which the MVME162P2
might be offered as an embedded controller without the VMEbus interface,
certain logic in the VMEchip2 has been duplicated in the Petra chip. (For
the location of the overlapping logic, refer to Chapter 1 in the
MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide.) As long as the VMEchip2 ASIC is present, the redundant logic is
inhibited in the Petra chip. The enabling signals for these functions are
controlled by software and Petra chip hardware initialization.

Memory Options
The following memory options are available on the different versions of
MVME162P2 boards.

DRAM
MVME162P2 boards are built with 16MB or 32MB shared DRAM
(SDRAM). Depending on build options chosen at the time of manufacture,
various versions of the MVME162P2 have the SDRAM configured to
model 1MB, 4MB, 8MB, or 16MB of parity-protected DRAM or 4MB,
8MB, 16MB, or 32MB of ECC-protected DRAM.

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 Functional Description

The SDRAM memory array itself is always a single-bit error correcting

and multi-bit error detection memory, irrespective of which interface
model you use to access the SDRAM. When the MC2 (parity) memory
controller interface is used to access the SDRAM, single-bit errors are
undetectable to users and multi-bit errors are defined to be parity errors.
Firmware will initialize the memory controller to maintain backward
4 compatibility with MVME162LX or -FX products. If the Petra ASIC is
supporting MVME162FX functionality, the parity memory controller
model will be enabled by default. If the Petra ASIC is supporting
MVME162LX functionality, firmware will enable either the parity or the
ECC memory controller model, depending on board configuration. (The
board configuration is a function of switch settings and resistor population
options.)
User code can modify Petra register settings to operate in either mode.
User code can also modify map decoder/switch settings to enable the
maximum amount of memory available. The minimum SDRAM
configuration is 16MB.
For specifics on SDRAM performance and for detailed programming
information, refer to the chapters on MC2 and MCECC memory controller
emulations in the MVME1X2P2 VME Embedded Controller
Programmer’s Reference Guide.

SRAM
The MVME162P2 implementation includes a 512KB SRAM (static
RAM) option. SRAM architecture is single non-interleaved. SRAM
performance is described in the section on the SRAM memory interface in
the chapter on the MC2 memory controller emulation in the MVME1X2P2
VME Embedded Controller Programmer’s Reference Guide. An onboard
battery supplies VCC to the SRAM when main power is removed. The
SRAM arrays are not parity protected.
The battery backup function for the onboard SRAM is provided by a coin-
type Panasonic CR2032 device (or equivalent) that supports primary and
secondary power sources. In the event of a main board power failure, the
CR2032 checks power sources and switches to the source with the higher
voltage.

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 Functional Description

If the voltage of the backup source is lower than two volts, the CR2032
blocks the second memory cycle; this allows software to provide an early
warning to avoid data loss. Because the second access may be blocked
during a power failure, software should do at least two accesses before
relying on the data.
The MVME162P2 provides jumpers (on J14) that allow either power
source of the CR2032 to be connected to the VMEbus +5V STDBY pin or
4
to one cell of the onboard battery. For example, the primary system backup
source may be a battery connected to the VMEbus +5V STDBY pin and
the secondary source may be the onboard battery. If the system source
should fail or the board is removed from the chassis, the onboard battery
takes over.

For proper SRAM operation, some jumper combination must be installed

! on the Backup Power Source Select header (refer to the jumper
Caution information in Chapter 1). If one of the jumpers is set to select the battery,
a battery must be installed on the MVME162P2. The SRAM may
malfunction if inputs to the CR2032 are left unconnected.
The SRAM is controlled by the Petra MC2 sector, and the access time is
programmable. Refer to the description of the Petra MC2 emulation in the
MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide for more detail.

About the Battery

The power source for the onboard SRAM is a coin-type Panasonic
CR2032 device (or equivalent) with two lithium cells. The battery is
socketed for easy removal and replacement. Small capacitors are provided
so that the battery can be quickly replaced without data loss.
The service life of the battery is very dependent on the ambient
temperature of the board and the power-on duty cycle. The lithium battery
supplied on the MVME162P2 should provide at least two years of backup
time with the board powered off and with an ambient temperature of 40°
C. If the power-on duty cycle is 50% (the board is powered on half of the
time), the battery lifetime is four years. At lower ambient temperatures, the
backup time is correspondingly longer.

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 Functional Description

If you intend to place the board in storage, putting the M48T58 in power-
save mode by stopping the oscillator will prolong battery life. This is
especially important at high ambient temperatures. To enter power-saving
mode, execute the 162Bug PS command (refer to Debugger Commands in
Chapter 3) or its equivalent application-specific command. When restoring
the board to service, execute the 162Bug SET command (set
4 mmddyyhhmm) after installation to restart the oscillator and initialize the
clock.
The MVME162P2 is shipped with the battery disconnected (i.e., with
VMEbus +5V standby voltage selected as both primary and secondary
power source). In order to use the battery as a power source, whether
primary or secondary, it is necessary to reconfigure the jumpers on J14
before installing the board. Refer to SRAM Backup Power Source (J14) on
page 1-10 for available jumper configurations.
The power leads from the battery are exposed on the solder side of the
board. The board should not be placed on a conductive surface or stored in
a conductive bag unless the battery is removed.

Lithium batteries incorporate inflammable materials such as lithium and

! organic solvents. If lithium batteries are mistreated or handled incorrectly,
Warning they may burst open and ignite, possibly resulting in injury and/or fire.
When dealing with lithium batteries, carefully follow the precautions listed
below in order to prevent accidents.
❏ Do not short circuit.
❏ Do not disassemble, deform, or apply excessive pressure.
❏ Do not heat or incinerate.
❏ Do not apply solder directly.
❏ Do not use different models, or new and old batteries together.
❏ Do not charge.
❏ Always check proper polarity.

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 Functional Description

To remove the battery from the module, carefully pry the battery from its
socket.
Before installing a new battery, ensure that the battery pins are clean. Note
the battery polarity and press the battery into the socket. When the battery
is in the socket, no soldering is required.

EPROM and Flash Memory

4

The MVME162P2 implementation includes 1MB or 2MB Flash memory.

Flash memory is a single Intel device (28F016SA on the MVME162P2)
organized in a 1MB x 8 or 2Mb x 8 configuration. For information on
programming Flash, refer to the Intel documents listed under
Manufacturer’s Documents in the Related Documentation appendix.
The Flash write enable signal is controlled by:
❏ A bit in the Flash Access Time Control register in the Petra ASIC
❏ A board-level configuration jumper (J16) and configuration switch
(S5, segment 4) which determine the status of Flash write protection
on the board
Refer to the MVME1X2P2 VME Embedded Controller Programmer’s
Reference Guide for specifics.
The EPROM locations are standard JEDEC 32-pin PLCC sockets that
accommodate three jumper-selectable densities (256 Kb x 8; 512 Kb x 8,
the factory default; 1 Mb x 8). The setting of a configuration switch (line
GPI3, segment 5 on S4), allows reset code to be fetched either from Flash
memory (S4 segment 5 set to OFF) or from EPROMs (S4 segment 5 set to
ON).

Note that MVME162P2 models ordered without the VMEbus interface are
shipped with Flash memory blank (the factory uses the VMEbus to
program the Flash memory with debugger code). To use the debugger
firmware, be sure that configuration switch S4 is set for the EPROM
memory map. Refer to chapters 1 and 3 for further details.

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 Functional Description

Battery-Backed-Up RAM and Clock

An M48T58 RAM and clock chip is used on the MVME162P2. This chip
provides a time-of-day clock, oscillator, crystal, power fail detection,
memory write protection, 8KB of RAM, and a battery in one 28-pin
package. The clock provides seconds, minutes, hours, day, date, month,
4 and year in BCD 24-hour format. Corrections for 28-, 29- (leap year), and
30-day months are made automatically. No interrupts are generated by the
clock. Although the M48T58 is an 8-bit device, the interface provided by
the Petra chip supports 8-, 16-, and 32-bit accesses to the M48T58. Refer
to the description of the Petra MC2 function in the MVME1X2P2 VME
Embedded Controller Programmer’s Reference Guide and to the M48T58
data sheet for detailed programming guidance and battery life information.

VMEbus Interface and VMEchip2

The VMEchip2 ASIC provides the local-bus-to-VMEbus interface, the
VMEbus-to-local-bus interface, and the DMA controller functions of the
local VMEbus. The VMEchip2 also provides the VMEbus system
controller functions. Refer to the VMEchip2 description in the
MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide for detailed programming information.
Note that the Abort switch logic in the VMEchip2 is not used. The GPI
inputs to the VMEchip2 which are located at $FFF40088 bits 7-0 are not
used. Instead, the Abort switch interrupt is integrated into the Petra MC2
sector at location $FFF42043. The GPI inputs are integrated into the Petra
MC2 sector at location $FFF4202C, bits 23-16.

I/O Interfaces
The MVME162P2 provides onboard I/O for many system applications.
The I/O functions include serial ports, IndustryPack (IP) interfaces, and
optional interfaces for LAN Ethernet transceivers and SCSI mass storage
devices.

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 Functional Description

Serial Communications Interface

The MVME162P2 uses two Zilog Z85230 serial port controllers to
implement the four serial communications interfaces. Each interface
supports CTS, DCD, RTS, and DTR control signals, as well as the TXD
and RXD transmit/receive data signals.
Because the serial clocks are omitted in the MVME162P2 implementation, 4
serial communications are strictly asynchronous. The MVME162P2
hardware supports serial baud rates of 110b/s to 38.4Kb/s.
The Z85230 supplies an interrupt vector during interrupt acknowledge
cycles. The vector is modified based upon the interrupt source within the
Z85230. Interrupt request levels are programmed via the Petra MC2
function (the MC2 emulation can handle up to four Z85230 chips). Refer
to the Z85230 data sheet listed listed under Manufacturer’s Documents in
the Related Documentation appendix, and to the MC2 programming model
in the MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide, for information.
The Z85230s are interfaced as DTE (data terminal equipment) with EIA-
232-D signal levels. The four serial ports are routed to four RJ45
connectors on the MVME162P2 front panel.

IndustryPack (IP) Interfaces

The IP2 function in the Petra ASIC supports four IndustryPack (IP)
interfaces; the MVME162P2 board itself accommodates up to two IP
modules. The IP modules are accessible from the front panel. The IP2
function as implemented on the MVME162P2 also includes two DMA
channels (one for each IP, or two for a double-wide IP), 32 or 30MHz (32
MHz for MC68LC0x0 or 30 MHz for MC680x0) or 8MHz IndustryPack
clock selection (jumper selectable), and one programmable timebase
strobe which is connected to the two interfaces. Refer to the IP2
Programming Model in the MVME1X2P2 VME Embedded Controller
Programmer's Reference Guide for details of the IP interface. Refer to
Chapter 5, Pin Assignments for the pin assignments of the IP connectors.

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 Functional Description

Notes MVME162P2 boards do not monitor power supply +5 Vdc

power and assert IP reset if the power falls too low. Instead, IP
reset is handled by the ENV command of the 162Bug debugger,
as described in Chapter 3. The IP reset is also driven active by the
power-up reset signal.
Two IP modules plugged into the same MVME162P2 board can
4 not use the Strobe∗ signal unless the jumper is removed from J11.
This will disconnect the Strobe∗ output from the Petra/IP2 ASIC.

Ethernet Interface
The MVME162P2 uses the Intel 82596CA LAN coprocessor to implement
the optional Ethernet transceiver interface. The 82596CA accesses local
RAM using DMA operations to perform its normal functions. Because the
82596CA has small internal buffers and the VMEbus has an undefined
latency period, buffer overrun may occur if the DMA is programmed to
access the VMEbus. Therefore, the 82596CA should not be programmed
to access the VMEbus.
Every MVME162P2 that is built with an Ethernet interface is assigned an
Ethernet Station Address. The address is $0001AF2xxxxx, where xxxxx is
the unique 5-nibble number assigned to the board (i.e., every
MVME162P2 has a different value for xxxxx).
Each board has an Ethernet Station Address displayed on a label attached
to the VMEbus P2 connector. In addition, the six bytes including the
Ethernet address are stored in the BBRAM configuration area. That is,
0001AF2xxxxx is stored in the BBRAM. The upper four bytes (0001AF2x)
are read at $FFFC1F2C; the lower two bytes (xxxx) are read at
$FFFC1F30. The MVME162 debugger has the capability to retrieve or set
the Ethernet address.
If the data in BBRAM is lost, use the number on the label on backplane
connector P2 to restore it.
The Ethernet transceiver interface is located on the MVME162P2 main
board, and the industry-standard DB15 connector is located on its front
panel.

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 Functional Description

Support functions for the 82596CA LAN coprocessor are provided by the
Petra MC2 sector. Refer to the 82596CA user’s guide and to the description
of the MC2 function in the MVME1X2P2 VME Embedded Controller
Programmer’s Reference Guide for detailed programming information.

SCSI Interface
The MVME162P2 may have provision for mass storage subsystems
4
through the industry-standard SCSI bus. These subsystems may include
hard and floppy disk drives, streaming tape drives, and other mass storage
devices. The optional SCSI interface is implemented using the NCR
53C710 SCSI I/O controller.
Support functions for the 53C710 are provided by the Petra MC2 sector.
Refer to the NCR 53C710 user’s guide and to the description of the MC2
function in the MVME1X2P2 VME Embedded Controller Programmer’s
Reference Guide for detailed programming information.

SCSI Termination
It is important that the SCSI bus be properly terminated at both ends.
In the case of the MVME162P2, terminators for the SCSI bus are present
on the main board. The SCSI terminators are enabled or disabled by a
jumper on header J12. If the SCSI bus ends at the MVME162P2, a jumper
must be installed at J12.
The FUSES LED on the MVME162P2 front panel monitors +5V power to
the SCSI bus TERM power line in addition to LAN power and
IndustryPack power; the FUSES LED illuminates when all fuses on the
MVME162P2 are operational. (The fuses are solid-state circuit breakers
that reset when the short which trips them is removed.) Because any device
on the SCSI bus can provide power to the TERM power line, the FUSES
LED does not directly indicate the condition of the fuse.

Local Resources
The MVME162P2 includes many resources for the local processor. These
include tick timers, software-programmable hardware interrupts, a
watchdog timer, and a local bus timeout.

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 Functional Description

Programmable Tick Timers

Six 32-bit programmable tick timers with 1µs resolution are available: two
in the VMEchip2 ASIC and four in the Petra/MC2 chip. The tick timers
may be programmed to generate periodic interrupts to the processor. Refer
to the VMEchip2 and Petra/MC2 descriptions in the MVME1X2P2 VME
Embedded Controller Programmer’s Reference Guide for detailed
4 programming information.

Watchdog Timer
A watchdog timer function is provided in both the Petra/MC2 chip and the
VMEchip2 ASIC. When the watchdog timer is enabled, it must be reset by
software within the programmed interval or it times out. The watchdog
timer can be programmed to generate a SYSRESET signal, a local reset
signal, or a board fail signal if it times out. Refer to the VMEchip2 and
Petra/MC2 descriptions in the MVME1X2P2 VME Embedded Controller
Programmer’s Reference Guide for detailed programming information.
The watchdog timer logic is duplicated in the VMEchip2 and Petra/MC2
ASICs. Because the watchdog timer function in the VMEchip2 is a
superset of that function in the Petra/MC2 chip (system reset function), the
timer in the VMEchip2 is to be used in all cases except for versions of the
MVME162P2 which do not include the VMEbus interface (i.e., boards
ordered with a "No VMEbus Interface" option).

Software-Programmable Hardware Interrupts

The VMEchip2 ASIC supplies eight software-programmable hardware
interrupts. These interrupts allow software to create a hardware interrupt.
Refer to the VMEchip2 description in the MVME1X2P2 VME Embedded
Controller Programmer’s Reference Guide for detailed programming
information.

Local Bus Timeout

The MVME162P2 provides timeout functions in the VMEchip2 ASIC and
the Petra/MC2 chip for the local bus. When the timer is enabled and a local
bus access times out, a Transfer Error Acknowledge (TEA) signal is sent
to the local bus master. The timeout value is selectable by software for 8

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 Functional Description

µsec, 64 µsec, 256 µsec, or infinity. The local bus timer does not operate
during VMEbus bound cycles. VMEbus bound cycles are timed by the
VMEbus access timer and the VMEbus global timer. Refer to the
VMEchip2 and Petra/MC2 descriptions in the MVME1X2P2 VME
Embedded Controller Programmer’s Reference Guide for detailed
programming information.
The access timer logic is duplicated in the VMEchip2 and Petra/MC2
4
ASICs. Because the local bus timer in the VMEchip2 can detect an
offboard access and the Petra/MC2 local bus timer cannot, the timer in the
VMEchip2 ASIC is used in all cases except for versions of the
MVME162P2 which do not include the VMEbus interface (i.e., boards
ordered with a "No VMEbus Interface" option).

Local Bus Arbiter

The local bus arbiter implements a fixed priority (see Table 4-2).
Table 4-2. Local Bus Arbitration Priority
Device Priority Note
LAN 0 Highest
Industry Pack DMA 1
SCSI 2 ...
VMEbus 3 Next Lowest
MC680x0/MC68LC0x0 4 Lowest

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 Functional Description

Connectors
The MVME162P2 has two 96-position DIN connectors: P1 and P2. P1
rows A, B, C, and P2 row B provide the VMEbus interconnection. P2 rows
A and C are not used.
The serial ports on the MVME162P2 are connected to four 8-pin RJ45
4 female connectors ( J17) on the front panel. The two IP modules connect
to the MVME162P2 by two pairs of 50-pin connectors. Two additional 50-
pin connectors behind the front panel are for external connections to IP
signals. The Ethernet LAN connector (J9) is a 15-pin socket connector
mounted on the front panel. The SCSI connector (J23) is a 68-pin socket
connector mounted on the front panel.
Pin assignments for the connectors on the MVME162P2 are listed in
Chapter 5.

Remote Status and Control

The remote reset connector, J2, is a 20-pin connector located behind the
front panel of the MVME162P2. It provides system designers with
flexibility in accessing critical indicator and reset functions. When the
board is enclosed in a chassis and the front panel is not visible, this
connector allows the Reset, Abort, and LED functions to be extended to
the control panel of the system, where they are visible. Alternatively, it
allows a system designer to construct a RESET/ABORT/LED panel that can
be located remotely from the MVME162P2.

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 5Pin Assignments
5
Connector Pin Assignments
This chapter summarizes the pin assignments for the following groups of
interconnect signals on the MVME162P2:

Connector Location Table

Remote Reset connector J2 Table 5-1
IndustryPack A and B connectors J4/5/6, J3/7/8 Table 5-2
Ethernet port, DB15 J9 Table 5-3
Serial ports, RJ45 J17 Table 5-4
SCSI connector J23 Table 5-5
VMEbus connector P1 P1 Table 5-6
VMEbus connector P2 P2 Table 5-7

The tables in this chapter furnish pin assignments only. For detailed
descriptions of the interconnect signals, consult the support information
for the MVME162P2 (available through your Motorola sales office).

5-1
 Pin Assignments

Remote Reset Connector - J2

The MVME162P2 has a 20-pin connector (J2) mounted behind the front
panel. When the MVME162P2 board is enclosed in a chassis and the front
panel is not visible, this connector enables you to extend the reset, abort
and LED functions to the control panel of the system, where they remain
accessible.
Table 5-1. Remote Reset Connector J2 Pin Assignments
5 1 +5V Fused LANLED∗ 2
3 P12VLED∗ SCSILED∗ 4
5 VMELED∗ No connection 6
7 RUNLED∗ STSLED∗ 8
9 FAILSTAT∗ No connection 10
11 SCONLED∗ ABORTSW∗ 12
13 RESETSW∗ GND 14
15 GND GPIO1 16
17 GPIO2 GPIO3 18
19 No connection GND 20

IndustryPack A and B Connectors

Up to two IndustryPack (IP) modules may be installed on the
MVME162P2. For each IP module, there are two 50-pin plug connectors
on the board: module A, J5/6; module B, J7/8. For external cabling to the
IP modules, two 50-pin IDC connectors (module A, J4; module B, J3) are
provided behind the MVME162P2 front panel. The pin assignments are
the same for both types of connector.

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 IndustryPack A and B Connectors

Table 5-2. IndustryPack Interconnect Signals

1 GND CLK 2
3 RESET∗ IPD0 4
5 IPD1 IPD2 6
7 IPD3 IPD4 8
9 IPD5 IPD6 10
11 IPD7 IPD8 12
13 IPD9 IPD10 14
5
15 IPD11 IPD12 16
17 IPD13 IPD14 18
19 IPD15 BS0∗ 20
21 BS1∗ –12V 22
23 +12V +5V 24
25 GND GND 26
27 +5V R/W∗ 28
29 IDSEL∗ DMAREQ0∗ 30
31 MEMSEL∗ DMAREQ1∗ 32
33 INTSEL∗ DMACK∗ 34
35 IOSEL∗ No Connection 36
37 IPA1 DMAEND∗ 38
39 IPA2 ERROR∗ 40
41 IPA3 INT_REQ0∗ 42
43 IPA4 INT_REQ1∗ 44
45 IPA5 STROBE∗ 46
47 IPA6 ACK∗ 48
49 No Connection GND 50

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 Pin Assignments

Ethernet Connector - J9
The MVME162P2’s Ethernet interface is implemented with a DB15
connector located on the front panel of the board. The pin assignments for
this connector are listed in the following table.
Table 5-3. DB15 Ethernet Connector Pin Assignments
1 GND C+ 2
3 T+ GND 4
5
5 R+ GND 6
7 No Connection GND 8
9 C– T– 10
11 GND R– 12
13 +12V GND 14
15 No Connection

Serial Connector - J17

A four-segment RJ45 connector located on the front panel of the
MVME162P2 provides the interface to the four asynchronous serial ports.
The pin assignments for each segment in the connector are as follows.
Table 5-4. Serial Connector Pin Assignments
1 DCDn
2 RTSn
3 Ground
4 TXDn
5 RXDn
6 Ground
7 CTSn
8 DTRn

5-4 Computer Group Literature Center Web Site

 SCSI Connector - J23

SCSI Connector - J23

Connector J23 is a standard 68-pin SCSI connector mounted on the front
panel of the MVME162P2 embedded controller. Table 5-5 lists the pin
assignments for J23.

VMEbus Connectors (P1, P2)

Two three-row 96-pin DIN type connectors, P1 and P2, supply the 5
interface between the base board and the VMEbus. P1 provides power and
VME signals for 24-bit addressing and 16-bit data. Its pin assignments are
set by the IEEE P1014-1987 VMEbus Specification. P2 Row B supplies
the base board with power, with the upper 8 VMEbus address lines, and
with an additional 16 VMEbus data lines. P2 rows A and C are not used in
the MVME162P2 implementation. The pin assignments for P1and P2 are
listed in Table 5-6 and Table 5-7 respectively.

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 Pin Assignments

Table 5-5. SCSI Connector J23 Pin Assignments

1 GND GND 2
3 GND GND 4
5 GND GND 6
7 GND GND 8
9 GND GND 10
11 GND GND 12
5 13 GND GND 14
15 GND GND 16
17 +5.0V TERMPWR +5.0V TERMPWR 18
19 No Connection GND 20
21 GND GND 22
23 GND GND 24
25 GND GND 26
27 GND GND 28
29 GND GND 30
31 GND GND 32
33 GND GND 34
35 DB∗(12) DB∗(13) 36
37 DB∗(14) DB∗(15) 38
39 DPH∗ DB∗(0) 40
41 DB∗(1) DB∗(2) 42
43 DB∗(3) DB∗(4) 44
45 DB∗(5) DB∗(6) 46
47 DB∗(7) DBP∗ 48
49 GND GND 50
51 +5.0V TERMPWR +5.0V TERMPWR 52
53 No Connection GND 54
55 ATN∗ GND 56
57 BSY∗ ACK∗ 58
59 RST∗ MSG∗ 60
61 SEL∗ DC∗ 62
63 REQ∗ IO∗ 64
65 DB∗(8) DB∗(9) 66
67 DB∗(10) DB∗(11) 68

5-6 Computer Group Literature Center Web Site

 VMEbus Connectors (P1, P2)

Table 5-6. VMEbus Connector P1 Pin Assignments

Row A Row B Row C

1 VD0 VBBSY∗ VD8 1

2 VD1 VBCLR∗ VD9 2

3 VD2 VACFAIL∗ VD10 3

4 VD3 VBGIN0∗ VD11 4

5 VD4 VBGOUT0∗ VD12 5

6 VD5 VBGIN1∗ VD13 6

7 VD6 VBGOUT1∗ VD14 7

5
8 VD7 VBGIN2∗ VD15 8

9 GND VBGOUT2∗ GND 9

10 VSYSCLK VBGIN3∗ VSYSFAIL∗ 10

11 GND VBGOUT3∗ VBERR∗ 11

12 VDS1∗ VBR0∗ VSYSRESET∗ 12

13 VDS0∗ VBR1∗ VLWORD∗ 13

14 VWRITE∗ VBR2∗ VAM5 14

15 GND VBR3∗ VA23 15

16 VDTACK∗ VAM0 VA22 16

17 GND VAM1 VA21 17

18 VAS∗ VAM2 VA20 18

19 GND VAM3 VA19 19

20 VIACK∗ GND VA18 20

21 VIACKIN∗ Not Used VA17 21

22 VIACKOUT∗ Not Used VA16 22

23 VAM4 GND VA15 23

24 VA7 VIRQ7∗ VA14 24

25 VA6 VIRQ6∗ VA13 25

26 VA5 VIRQ5∗ VA12 26

27 VA4 VIRQ4∗ VA11 27

28 VA3 VIRQ3∗ VA10 28

29 VA2 VIRQ2∗ VA9 29

30 VA1 VIRQ1∗ VA8 30

31 –12V Not Used +12V 31

32 +5V +5V +5V 32

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 Pin Assignments

Table 5-7. VMEbus Connector P2 Pin Assignment

ROW A ROW B ROW C
1 No Connection +5V No Connection 1

2 No Connection GND No Connection 2

3 No Connection Not Used No Connection 3

4 No Connection VA24 No Connection 4

5 No Connection VA25 No Connection 5

5 6 No Connection VA26 No Connection 6

7 No Connection VA27 No Connection 7

8 No Connection VA28 No Connection 8

9 No Connection VA29 No Connection 9

10 No Connection VA30 No Connection 10

11 No Connection VA31 No Connection 11

12 No Connection GND No Connection 12

13 No Connection +5V No Connection 13

14 No Connection VD16 No Connection 14

15 No Connection VD17 No Connection 15

16 No Connection VD18 No Connection 16

17 No Connection VD19 No Connection 17

18 No Connection VD20 No Connection 18

19 No Connection VD21 No Connection 19

20 No Connection VD22 No Connection 20

21 No Connection VD23 No Connection 21

22 No Connection GND No Connection 22

23 No Connection VD24 No Connection 23

24 No Connection VD25 No Connection 24

25 No Connection VD26 No Connection 25

26 No Connection VD27 No Connection 26

27 No Connection VD28 No Connection 27

28 No Connection VD29 No Connection 28

29 No Connection VD30 No Connection 29

30 No Connection VD31 No Connection 30

31 No Connection GND No Connection 31

32 No Connection +5V No Connection 32

5-8 Computer Group Literature Center Web Site

 ASpecifications
A
Board Specifications
The following table lists the general specifications for the MVME162P2
VME embedded controller. The subsequent sections detail cooling
requirements and EMC regulatory compliance.
A complete functional description of the MVME162P2 boards appears in
Chapter 4. Specifications for the optional IndustryPack modules can be
found in the documentation for those modules.
Table A-1. MVME162P2 Specifications

Characteristics Specifications
Power requirements +5Vdc (±5%), 1.75A typical, 2.25A maximum
(with EPROM; without +12 Vdc (± 5%), 100 mA maximum
IPs) –12 Vdc (± 5%), 100 mA maximum
Operating temperature –5° C to 55° C ( 23° F to 131° F) exit air with forced-air cooling
(refer also to Cooling Requirements and Special Considerations for
Elevated-Temperature Operation)
Storage temperature –40° C to +85° C ( –40° F to 185° F)
Relative humidity 5% to 90% (noncondensing)
Vibration (operating) 2 Gs RMS, 20Hz-2000Hz random
Altitude (operating) 5000 meters (16,405 feet)
Physical dimensions Height Double-high VME board, 9.2 in. (233 mm)
(base board only)
Front panel width 0.8 in. (20 mm)
Front panel height 10.3 in. (262 mm)
Depth 6.3 in. (160 mm)

A-1
 Specifications
A

Cooling Requirements
The Motorola MVME162P2 VME Embedded Controller is specified,
designed, and tested to operate reliably with an incoming air temperature
range of –5° to 55° C (23° to 131° F) with forced air cooling of the entire
assembly (base board and modules) at a velocity typically achievable by
using a 100 CFM axial fan. Temperature qualification is performed in a
standard Motorola VME system chassis. Twenty-five-watt load boards are
inserted in two card slots, one on each side, adjacent to the board under
test, to simulate a high power density system configuration. An assembly
of three axial fans, rated at 100 CFM per fan, is placed directly under the
VME card cage. The incoming air temperature is measured between the
fan assembly and the card cage, where the incoming airstream first
encounters the module under test. Test software is executed as the module
is subjected to ambient temperature variations. Case temperatures of
critical, high power density integrated circuits are monitored to ensure that
component vendors’ specifications are not exceeded.
While the exact amount of airflow required for cooling depends on the
ambient air temperature and the type, number, and location of boards and
other heat sources, adequate cooling can usually be achieved with 10 CFM
and 490 LFM flowing over the module. Less airflow is required to cool the
module in environments having lower maximum ambients. Under more
favorable thermal conditions, it may be possible to operate the module
reliably at higher than 55° C with increased airflow. It is important to note
that there are several factors, in addition to the rated CFM of the air mover,
which determine the actual volume and speed of air flowing over a
module.

A-2 Computer Group Literature Center Web Site

 Cooling Requirements
A

Special Considerations for Elevated-Temperature Operation

The following information is for users whose applications for the
MVME162P2 may subject it to high temperatures.
The MVME162P2 uses commercial-grade devices. Therefore, it can
operate in an environment with ambient air temperatures ranging from 0°
C to 70° C. Several factors influence the ambient temperature seen by
components on the MVME162P2. Among them are inlet air temperature;
air flow characteristics; number, types, and locations of IP modules; power
dissipation of adjacent boards in the system, etc.
A temperature profile of a comparable board (the MVME172LX
embedded controller) was developed in an MVME954A six-slot VME
chassis. Two such boards, each loaded with two GreenSpring
IndustryPack modules, were placed in the chassis with one 36W load
board installed between them. The chassis was placed in a thermal
chamber that maintained an ambient temperature of 55° C. Measurements
showed that the fans in the chassis supplied an airflow of approximately 65
LFM over the MVME172LX boards. Under these conditions, a rise in
temperature of approximately 10° C between the inlet and exit air was
observed. The junction temperatures of selected high-power devices on the
MVME172LXs were calculated (from case temperature measurements)
and were found to be within manufacturers’ specified tolerances.

For elevated-temperature operation, perform similar measurements and

! calculations to determine the actual operating margin for your specific
Caution environment.
To facilitate elevated-temperature operation:
1. Position the MVME162P2 in the chassis to allow for maximum
airflow over the component side of the board.
2. Do not place boards with high power dissipation next to the
MVME162P2.
3. Use low-power IP modules only.

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 Specifications
A

EMC Regulatory Compliance

The MVME162P2 was tested without IndustryPacks in an
EMC-compliant chassis and meets the requirements for Class B
equipment. Compliance was achieved under the following conditions:
❏ Shielded cables on all external I/O ports.
❏ Cable shields connected to chassis ground via metal shell
connectors bonded to a conductive module front panel.
❏ Conductive chassis rails connected to chassis ground. This provides
the path for connecting shields to chassis ground.
❏ Front panel screws properly tightened.
❏ All peripherals EMC-compliant.
For minimum RF emissions, it is essential that the conditions above be
implemented. Failure to do so could compromise the FCC compliance of
the equipment containing the module.
The MVME162P2 is a board-level product and meant to be used in
standard VME applications. As such, it is the responsibility of the OEM to
meet the regulatory guidelines as determined by its application.

A-4 Computer Group Literature Center Web Site

 BTroubleshooting
B
Solving Startup Problems
In the event of difficulty with your MVME162P2 VME embedded
controller, try the simple troubleshooting steps on the following pages
before calling for help or sending the board back for repair. Some of the
procedures will return the board to the factory debugger environment. (The
board was tested under these conditions before it left the factory.) The self-
tests may not run in all user-customized environments.
Table B-1. Troubleshooting MVME162P2 Boards

Condition Possible Problem Try This:

I. Nothing works, no A. If the RUN (or 1. Make sure the system is plugged in.
display on the FUSE) LED is not 2. Check that the board is securely installed in its backplane
terminal. lit, the board may or chassis.
not be getting 3. Check that all necessary cables are connected to the
correct power. board, per this manual.
4. Check for compliance with System Considerations, as
described in this manual.
5. Review the Installation and Startup procedures, as
described in this manual. They include a step-by-step
powerup routine. Try it.
B. If the LEDs are 1. For VMEmodules, the processor module (controller)
lit, the board may should be in the first (leftmost) slot.
be in the wrong 2. Also check that the “system controller” function on the
slot. board is enabled, per this manual.
C. The “system Configure the system console terminal as described in this
console” manual.
terminal may be
configured
incorrectly.

B-1
 Troubleshooting

Table B-1. Troubleshooting MVME162P2 Boards

B
Condition Possible Problem Try This:
II. There is a display A. The keyboard Recheck the keyboard connections and power.
on the terminal, may be connected
but input from the incorrectly.
keyboard has no
B. Board jumpers Check the board jumpers as described in this manual.
effect.
may be
configured
incorrectly.
C. You may have Press the HOLD or PAUSE key again.
invoked flow If this does not free up the keyboard, type in:
control by <CTRL>-Q
pressing a HOLD
or PAUSE key, or
by typing:
<CTRL>-S
III. Debug prompt A. Debugger 1. Disconnect all power from your system.
162-Bug> does EPROM/Flash 2. Check that the proper debugger device is installed.
not appear at may be missing. 3. Remove the jumper from J21, pins 9-10. This enables use
powerup, and the of the EPROM instead of the Flash memory.
B. The board may
board does not
need to be reset. 4. Reconnect power.
autoboot.
5. Restart the system by “double-button reset”: press the
RESET and ABORT switches at the same time; release
RESET first, wait seven seconds, then release ABORT.
6. If the debug prompt appears, go to step IV or step V, as
indicated. If the debug prompt does not appear, go to step
VI.
IV. Debug prompt A. The initial 1. Start the onboard calendar clock and timer. Type:
162-Bug> debugger set mmddyyhhmm <CR>
appears at environment where the characters indicate the month, day, year, hour,
powerup, but the parameters may and minute. The date and time will be displayed.
board does not be set incorrectly.
autoboot.
B. There may be
some fault in the Performing the next step (env;d) will
board hardware. ! change some parameters that may affect
your system’s operation.
Caution
(continues>)

B-2 Computer Group Literature Center Web Site

 Solving Startup Problems

Table B-1. Troubleshooting MVME162P2 Boards

B
Condition Possible Problem Try This:
IV. Continued 2. At the command line prompt, type in:
env;d <CR>
This sets up the default parameters for the debugger
environment.
3. When prompted to Update Non-Volatile RAM, type in:
y <CR>
4. When prompted to Reset Local System, type in:
y <CR>
5. After the clock speed is displayed, immediately (within
five seconds) press the Return key:
<CR>
or
BREAK
to exit to the System Menu. Then enter a 3 for “Go to
System Debugger” and Return:
3 <CR>
Now the prompt should be:
162-Diag>
6. You may need to use the cnfg command (see your board
Debugger Manual) to change clock speed and/or Ethernet
Address, and then later return to:
env <CR>
and step 3.
7. Run the selftests by typing in:
st <CR>
The tests take as long as 10 minutes, depending on RAM
size. They are complete when the prompt returns. (The
onboard self-test is a valuable tool in isolating defects.)
8. The system may indicate that it has passed all the self-
tests. Or, it may indicate a test that failed. If neither
happens, enter:
de <CR>
Any errors should now be displayed. If there are any
errors, go to step VI. If there are no errors, go to step V.
V. The debugger is A. No apparent No further troubleshooting steps are required.
in system mode problems —
and the board troubleshooting is
autoboots, or the done.
board has passed
self-tests.

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 Troubleshooting

Table B-1. Troubleshooting MVME162P2 Boards

B
Condition Possible Problem Try This:
VI. The board has A. There may be 1. Document the problem and return the board for service.
failed one or some fault in the 2. Phone 1-800-222-5640.
more of the tests board hardware or
listed above, and the on-board
cannot be debugging and
corrected using diagnostic
the steps given. firmware.
TROUBLESHOOTING PROCEDURE COMPLETE.

B-4 Computer Group Literature Center Web Site

 CNetwork Controller Data
C
Network Controller Modules Supported
The 162Bug firmware supports the following VMEbus network controller
modules. The default address for each module type and position is shown
to indicate where the controller must reside to be supported by the 162Bug.
The controllers are accessed via the specified CLUN and DLUNs listed
here. The CLUN and DLUNs are used in conjunction with the debugger
commands NBH, NBO, NIOP, NIOC, NIOT, NPING, and NAB; they
are also used with the debugger system calls .NETRD, .NETWR,
.NETFOPN, .NETFRD, .NETCFIG, and .NETCTRL.

Controller CLUN DLUN Address Interface

Type Type
MVME162P2 $00 $00 $FFF46000 Ethernet
MVME376 $02 $00 $FFFF1200 Ethernet
MVME376 $03 $00 $FFFF1400 Ethernet
MVME376 $04 $00 $FFFF1600 Ethernet
MVME376 $05 $00 $FFFF5400 Ethernet
MVME376 $06 $00 $FFFF5600 Ethernet
MVME376 $07 $00 $FFFFA40 Ethernet
0
MVME374 $10 $00 $FF000000 Ethernet
MVME374 $11 $00 $FF100000 Ethernet
MVME374 $12 $00 $FF200000 Ethernet
MVME374 $13 $00 $FF300000 Ethernet
MVME374 $14 $00 $FF400000 Ethernet
MVME374 $15 $00 $FF500000 Ethernet

C-1
 Network Controller Data

C-2 Computer Group Literature Center Web Site

 DDisk/Tape Controller
Data D
Controller Modules Supported
The following VMEbus disk/tape controller modules are supported by the
162Bug. The default address for each controller type is First Address. The
controller can be addressed by First CLUN during execution of the BH,
BO, or IOP commands, or during execution of the .DSKRD or .DSKWR
TRAP #15 calls. Note that if another controller of the same type is used,
the second one must have its address changed by its onboard jumpers
and/or switches, so that it matches Second Address and can be called up by
Second CLUN.

First First Second Second

Controller Type
CLUN Address CLUN Address
CISC Embedded Controller $00 (Note 1) -- -- --
MVME320 - Winchester/Floppy $11 (Note 2) $FFFFB000 $12 (Note 2) $FFFFAC00
Controller
MVME323 - ESDI Winchester $08 $FFFFA000 $09 $FFFFA200
Controller
MVME327A - SCSI Controller $02 $FFFFA600 $03 $FFFFA700
MVME328 - SCSI Controller $06 $FFFF9000 $07 $FFFF9800
MVME328 - SCSI Controller $16 $FFFF4800 $17 $FFFF5800
MVME328 - SCSI Controller $18 $FFFF7000 $19 $FFFF7800
MVME350 - Streaming Tape $04 $FFFF5000 $05 $FFFF5100
Controller
Notes:
1. If an MVME162P2 with an SCSI port is used, the MVME162P2 module has CLUN 0.
2. For MVME162P2s, the first MVME320 has CLUN $11; the second MVME320 has CLUN $12.

D-1
 Disk/Tape Controller Data

Default Configurations

Note SCSI Common Command Set (CCS) devices are the only ones
tested by Motorola Computer Group.

D CISC Embedded Controllers -- 7 Devices

Controller LUN Address Device LUN Device Type

0 $XXXXXXXX 00 SCSI Common Command Set (CCS), which
10 may be any of these:
- Fixed direct access
20
- Removable flexible direct access
30
(TEAC style)
40
- CD-ROM
50
- Sequential access
60

MVME320 -- 4 Devices

Controller LUN Address Device LUN Device Type

11 $FFFFB000 0 Winchester hard drive
1 Winchester hard drive
12 $FFFFAC00 2 5-1/4" DS/DD 96 TPI floppy drive
3 5-1/4" DS/DD 96 TPI floppy drive

D-2 Computer Group Literature Center Web Site

 Default Configurations

MVME323 -- 4 Devices

Controller LUN Address Device LUN Device Type

8 $FFFFA000 0 ESDI Winchester hard drive
1 ESDI Winchester hard drive
9 $FFFFA200 2 ESDI Winchester hard drive
3 ESDI Winchester hard drive D
MVME327A -- 9 Devices

Controller LUN Address Device LUN Device Type

2 $FFFFA600 00 SCSI Common Command Set
10 (CCS), which may be any of these:
$FFFFA700 20 - Fixed direct access
3
30 - Removable flexible direct access
(TEAC style)
40
- CD-ROM
50
- Sequential access
60
80 Local floppy drive
81 Local floppy drive

http://www.motorola.com/computer/literature D-3
 Disk/Tape Controller Data

MVME328 -- 14 Devices

Controller LUN Address Device LUN Device Type

6 $FFFF9000 00 SCSI Common Command Set
08 (CCS), which may be any of these:
10 - Removable flexible direct access
D 7 $FFFF9800 18 (TEAC style)
- CD-ROM
20
- Sequential access
28
16 $FFFF4800
30
40 Same as above, but these will only be
48 available if the daughter card for the second
17 $FFFF5800 SCSI channel is present.
50
58
18 $FFFF7000 60
68
70
19 $FFFF7800

MVME350 -- 1 Device

Controller LUN Address Device LUN Device Type

4 $FFFF5000 0 QIC-02 streaming tape drive
5 $FFFF5100

D-4 Computer Group Literature Center Web Site

 IOT Command Parameters

IOT Command Parameters

The following table lists the proper IOT command parameters for floppies
used with boards such as the MVME328 and MVME162P2.

Floppy Types and Formats

IOT Parameter DSDD5 PCXT8 PCXT9 PCXT9_3 PCAT PS2 SHD D
Sector Size
0- 128 1- 256 2- 512
3-1024 4-2048 5-4096 = 1 2 2 2 2 2 2
Block Size:
0- 128 1- 256 2- 512
3-1024 4-2048 5-4096 = 1 1 1 1 1 1 1
Sectors/Track 10 8 9 9 F 12 24
Number of Heads = 2 2 2 2 2 2 2
Number of Cylinders = 50 28 28 50 50 50 50
Precomp. Cylinder = 50 28 28 50 50 50 50
Reduced Write Current 50 28 28 50 50 50 50
Cylinder =
Step Rate Code = 0 0 0 0 0 0 0
Single/Double DATA D D D D D D D
Density =
Single/Double TRACK D D D D D D D
Density =
Single/Equal_in_all Track S E E E E E E
Zero Density =
Slow/Fast Data Rate = S S S S F F F
Other Characteristics
Number of Physical Sectors 0A00 0280 02D0 05A0 0960 0B40 1680
Number of Logical Blocks 09F8 0500 05A0 0B40 12C0 1680 2D00
(100 in size)
Number of Bytes in Decimal 653312 327680 368460 737280 1228800 1474560 2949120
Media Size/Density 5.25/DD 5.25/DD 5.25/DD 3.5/DD 5.25/HD 3.5/HD 3.5/ED
Notes
1. All numerical parameters are in hexadecimal unless otherwise noted.
2. The DSDD5 type floppy is the default setting for the debugger.

http://www.motorola.com/computer/literature D-5
 Disk/Tape Controller Data

D-6 Computer Group Literature Center Web Site

 ERelated Documentation
E
MCG Documents
The Motorola Computer Group publications listed below are referenced in
this manual. You can obtain paper or electronic copies of MCG
publications by:
❏ Contacting your local Motorola sales office
❏ Visiting MCG’s World Wide Web literature site,
http://www.motorola.com/computer/literature
..

Table E-1. Motorola Computer Group Documents

Motorola
Document Title
Publication Number
MVME1X2P2 VME Embedded Controller Programmer’s V1X2P2A/PG
Reference Guide
MVME162Bug Diagnostics User's Manual V162DIAA/UM
Debugging Package for Motorola 68K CISC CPUs User’s 68KBUG1/D
Manual (Parts 1 and 2) 68KBUG2/D
Single Board Computers SCSI Software User’s Manual SBCSCSI/D

To locate and view the most up-to-date product information in PDF or

HTML format, visit http://www.motorola.com/computer/literature.

E-1
 Related Documentation

Manufacturers’ Documents
For additional information, refer to the following table for manufacturers’
data sheets or user’s manuals. As a further help, sources for the listed
documents are also provided. Please note that in many cases, the
information is preliminary and the revision levels of the documents are
subject to change without notice.
Table E-2. Manufacturers’ Documents
E
Publication
Document Title and Source
Number
M68000 Family Reference Manual M68000FR
MC68040 Microprocessor User’s Manual M68040UM
Literature Distribution Center for Motorola
Telephone: 1-800- 441-2447
FAX: (602) 994-6430 or (303) 675-2150
E-mail: [email protected]
Web: http://www.mot.com/SPS
82596CA Local Area Network Coprocessor Data Sheet 290218
82596CA Local Area Network Coprocessor User’s Manual 296853
28F016SA Flash Memory Data Sheet 209435
Intel Corporation
Web: http://developer.intel.com/design
SYM 53C710 (was NCR 53C710) SCSI I/O Processor Data Manual NCR53C710DM
SYM 53C710 (was NCR 53C710) SCSI I/O Processor Programmer’s Guide NCR53C710PG
Symbios Logic Inc.
1731 Technology Drive, Suite 600
San Jose, CA 95110
NCR Managed Services Center — Telephone: 1-800-262-7782
Web: http://www.lsilogic.com/products/symbios
M48T58(B) TIMEKEEPER™ and 8K x 8 Zeropower™ RAM Data Sheet M48T58
SGS-Thomson Microelectronics Group
Marketing Headquarters (or nearest Sales Office)
1000 East Bell Road
Phoenix, Arizona 85022
Telephone: (602) 867-6100
Web: http://www.st.com/stonline/books

E-2 Computer Group Literature Center Web Site

 Related Specifications

Table E-2. Manufacturers’ Documents (Continued)

Publication
Document Title and Source
Number
Z85230 Serial Communications Controller Product Brief Z85230pb.pdf
Zilog Inc.
210 Hacienda Avenue
Campbell, CA 95008-6609
Web: http://www.zilog.com/products
E

Related Specifications
For additional information, refer to the following table for manufacturers’
data sheets or user’s manuals. As a further help, sources for the listed
documents are also provided. Please note that in many cases, the
information is preliminary and the revision levels of the documents are
subject to change without notice.
Table E-3. Related Specifications

Publication
Document Title and Source
Number
VME64 Specification ANSI/VITA 1-1994
VITA (VMEbus International Trade Association )
7825 E. Gelding Drive, Suite 104
Scottsdale, AZ 85260
Telephone: (602) 951-8866
Web: http://www.vita.com
NOTE: An earlier version of the VME specification is available as:

Versatile Backplane Bus: VMEbus ANSI/IEEE

Institute of Electrical and Electronics Engineers, Inc. Standard 1014-1987
Publication and Sales Department
345 East 47th Street
New York, New York 10017-21633
Telephone: 1-800-678-4333

http://www.motorola.com/computer/literature E-3
 Related Documentation

Table E-3. Related Specifications (Continued)

Publication
Document Title and Source
Number
OR
Microprocessor system bus for 1 to 4 byte data IEC 821 BUS
Bureau Central de la Commission Electrotechnique Internationale
3, rue de Varembé
Geneva, Switzerland
E
ANSI Small Computer System Interface-2 (SCSI-2), Draft Document X3.131- X3.131-198X Rev.
198X, Revision 10c 10c
Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112-5704
IndustryPack Logic Interface Specification, Revision 1.0 ANSI/VITA 4-1995
VITA (VMEbus International Trade Association )
7825 E. Gelding Drive, Suite 104
Scottsdale, AZ 85260
Telephone: (602) 951-8866
Web: http://www.vita.com
Interface Between Data Terminal Equipment and Data Circuit-Terminating ANSI/EIA-232-D
Equipment Employing Serial Binary Data Interchange (EIA-232-D) Standard
Global Engineering Documents
Suite 400
1991 M Street, NW
Washington, DC 20036
Telephone: 1-800-854-7179
Telephone: (303) 397-7956
Web: http://global.ihs.com

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 Index

Numerics BBRAM (battery-backed-up RAM) and

162Bug clock 3-8, 4-12
disk/tape controller data D-1 BG* (bus grant) signal 1-24
firmware 3-8 block diagram 4-4
implementation 3-3 board
network controller data C-1 architecture 4-1
overview 3-1 configuration 1-4
stack space 3-4 connectors 4-18
27C040 EPROM 3-3 dimensions A-1
53C710 SCSI controller 4-15 features 4-1
82596CA LAN coprocessor 4-14 installation 1-23
preparation 1-1
A storage, preparation for 4-10
abort process 2-13 booting the system 2-8, 2-10, 2-11
ABORT switch 4-18 BREAK key 2-13
aborting program execution 2-1 break process 2-13
address ranges, EPROM 1-13 bus grant (BG*) signal 1-24
address/data configurations 1-25
addressing modes 1-25 C
altitude (operating) A-1 cable connections 1-24
ambient air temperature (effect on cooling) cables, I/O ports A-4
A-2 cache memory 4-6
arbitration priority 4-17 chassis grounding A-4
arguments, firmware command 3-5 CISC embedded controller(s) D-1
autoboot process 2-8 CLUN (controller LUN) C-1, D-1
autojumpering (VME backplane) 1-24 command identifier, firmware 3-5
command line input 3-5
B commands, firmware
backplane jumpers 1-24 CNFG (Configure Board Information
backward compatibility 3-9 Block) 3-9
batteries 4-9 ENV (Set Bug/Operating System
baud rate, default 2-7 Environment) 3-11
compatibility, backward 3-9

IN-1
 Index

conductive chassis rails (EMC compliance) debugger

A-4 commands 3-6
configurable items, MVME162P2 board 1-5 firmware (162Bug) 3-8
configuration switches prompt 3-5
S3 (MC2 DRAM size) 2-7 default baud rate 2-7
S4 (as software-readable switch) 2-5 device LUN (DLUN) C-1, D-2
S4 (EPROM/Flash selection) 1-13, 2-8 diagnostic facilities 2-14
S5 (Flash Write Enable mode) 1-20, 2-7, dimensions, base board A-1
4-11 direct access devices D-4
S5 (IP DMA snoop control) 1-18, 2-7 direct memory access (DMA) 4-13
S5 (IP reset mode) 1-19, 2-7 directories, switching 2-14
S6 (MCECC DRAM size) 1-21, 2-7 disk/tape controller modules supported D-1
configuration switches, location of 1-5 DLUN (device LUN) C-1, D-2
Configure Board Information Block (CNFG) DMA (direct memory access) 4-13
firmware command 3-9 DRAM (dynamic RAM)
configuring base address 1-25
162Bug parameters 3-11 options 4-7
hardware 2-5
IndustryPack modules 3-19 E
IP base addresses 3-19 EIA-232-D ports 2-7
VMEbus interface 3-16 EMC regulatory compliance A-4
connector pin assignments 5-1 ENV command parameters 3-11
connectors 4-18 environmental parameters 3-9
IndustryPack (IP) 1-23 EPROM 3-3
console port 2-7 address ranges 1-13
control/status registers 1-26 and Flash memory 4-11
controller LUN (CLUN) C-1, D-1 sockets 1-11, 2-10, 3-3, 4-11
controller modules (disk/tape) D-1 EPROM/Flash mapping 1-14
controller modules (network) C-1 EPROM/Flash selection 1-17
cooling requirements A-2 ESD (electrostatic discharge), precautions
CSR bit IP32 (IP bus clock) 1-9 against 1-3
ESDI Winchester hard drive D-3
D Ethernet
data bus structure, MVME162P2 4-6 controller modules supported C-1
data circuit-terminating equipment (DCE) interface 4-14
I 4-13 signals 5-4
N data sheets E-2 station address 4-14
D date and time, setting 2-8, B-2 extended addressing 1-25
DCE (data circuit-terminating equipment)
E 4-13
X

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F IndustryPack (IP)
features, hardware 4-1 bus clock header (J13) 1-9
firmware 2-2 bus strobe select header (J11) 1-7, 2-5
directories 3-5 interface functions 4-13
documentation E-1 IP1/IP2 reset mode 1-19
Flash modules, installation 1-23
memory 1-11, 3-3, 4-11 signals 5-2
write-protect header (J16) 1-11, 4-11 IndustryPack modules
flexible diskettes (controller data) D-2 base addresses of 3-19
floppy diskettes D-4 configuration 3-20
floppy drives (disk/tape controller) D-2, D-3 configuring 3-19
forced air cooling A-2 general control register 3-20
front panel switches and indicators 2-1 memory size 3-20
functional description 4-1 initial conditions 2-4
fuses, solid-state 1-26 installation
considerations 1-26
G interconnect signals 5-1
GCSR (global control/status registers) 1-26 interrupt acknowledge signal (IACK*) 1-24
general-purpose readable switch (S4) 1-16 interrupt control registers 3-20
global bus timeout 1-26 interrupt functions 4-13
global control/status registers (GCSR) 1-26 Interrupt Stack Pointer (ISP) 3-4
grounding A-4 interrupts, hardware 4-16
grounding strap, use of 1-3 IOT command parameters D-5
IP (IndustryPack)
H reset signal 4-14
handshaking, hardware 2-7 IP2 interface function 4-13
hard disk drive D-3 IP32 CSR bit (IP bus clock) 1-9
hardware ISP (Interrupt Stack Pointer) 3-4
features 4-1
initialization 2-3 J
interrupts 4-16 J17 serial connector 4-18
preparation 1-1 J2 connector 4-18
high-temperature operation A-3 jumper headers
humidity, relative A-1 J1 (system controller selection) 1-7, 2-5
J11 (IP bus strobe) 1-7, 2-5
I J12 (SCSI termination) 1-8, 2-6, 4-15 I
I/O interfaces 4-12 J13 (IP bus clock) 1-9, 2-6 N
IACK* (interrupt acknowledge) signal 1-24 J14 (SRAM backup power) 1-10, 2-6
indicators, front panel 2-1
D
J16 (Flash memory write protection)
1-11, 2-7, 2-8, 4-11
E
J20 (EPROM/Flash configuration) 1-11, X
2-7

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 Index

jumper headers, location of 1-5 I/O interfaces 4-12

jumpers, backplane 1-24 installation 1-23
programming information E-1
L regulatory compliance A-4
LAN MVME320 disk/tape controllers D-2
controller modules supported C-1 MVME323 disk/tape controller D-3
interface 4-14 MVME327A disk/tape controller D-3
LEDs (light-emitting diodes) 2-1, 4-18 MVME328 disk/tape controller D-4
local MVME350 controller D-4
bus 4-16 MVME374 network controller C-1
bus arbiter 4-17 MVME376 network controller C-1
bus timeout 4-16
resources for the processor 4-15 N
Local Area Network (LAN) interface 4-14 network boot process 2-11
location monitors, processor 1-26 network controller modules C-1
logical unit number (LUN) (see CLUN or non-volatile RAM (NVRAM) 3-8, 3-11
DLUN) no-VMEbus-interface option 4-7, 4-11, 4-16
LUN (logical unit number) (see CLUN or
DLUN) O
operating parameters 3-9
M operating temperature A-1
mapping, EPROM/Flash 1-14 option fields, in firmware command 3-6
MC2 DRAM size 1-15
MC2 sector registers 1-13, 1-16 P
MC68040 or MC68LC040 P1 and P2 connectors 4-18, 5-5
cache memory 4-6 parameters, ENV command 3-11
MPU 4-6 Petra ASIC
MCECC memory model 1-22 control of Flash access time 4-11
memory controller emulations (MC1/MC2) IP bus Strobe* signal 2-5
1-20, 1-21 MC2 function 1-13, 2-5
memory options 4-7 MCECC function 1-21
memory requirements 3-3, 3-11 SCSI controller support 4-15
microprocessor options 4-6 pin assignments, connector 5-1
modifying switch settings 1-16, 1-22 port number(s) 3-5
MPU options 4-6 power requirements A-1
I MVME162Bug documentation E-1 powering up the board 2-1
MVME162P2 power-save mode 4-10
N preparing the board 1-1
as network controller C-1
D board specifications A-1 processor
E cooling requirements A-2 bus structure 4-6
X EMC regulatory compliance A-4 cache memory 4-6
features 4-1 location monitors 1-26

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programmable tick timers 4-16 Set Bug/Operating System Environment
(ENV) firmware command 3-11
Q setting date and time 2-8, B-2
QIC-02 streaming tape drive D-4 shielded cables A-4
size of base board A-1
R slave address decoders, VMEbus 3-16
regulatory compliance A-4 snoop control 1-18
related specifications E-3 software-programmable hardware interrupts
relative humidity A-1 4-16
remote control/status connector (J2) 4-18, software-readable switch (S4) 1-16
5-2 specifications
RESET switch 4-18 MVME162P2 A-1
resetting the system 2-1, 2-12 related E-3
RF emissions 1-24 SRAM (static RAM)
minimizing A-4 backup power source selection (J14)
ROMboot process 2-10 1-10
battery options 4-9
S
options 4-8
safety procedures 1-4
startup overview 1-1
SCC (serial communications controller) 2-8
startup problems, solving B-1
SCSI
static variable space (firmware) 3-4
common command set (CCS) devices
storage temperature A-1
D-2, D-4
streaming tape drive D-4
controller (53C710) 4-15
switch settings, modifying 1-16, 1-22
direct access devices D-2
switches, configuration
interface 4-15
S3 (MC2 DRAM size) 1-15
sequential access devices D-2
S4 (EPROM/Flash selection) 1-17
signals 5-5
S5 (Flash Write Enable mode) 1-20
termination 4-15
S5 (IP DMA snoop control) 1-18
termination header (J12) 1-8
S5 (IP reset mode) 1-19
terminator configuration 4-15
S6 (MCECC DRAM size) 1-21
SD command 2-14
switches, front panel 2-1
SDRAM (shared DRAM)
switching directories 2-14
options 4-7
system
sequential access devices D-4
considerations 1-25
serial I
console setup 2-7
communication parameters 2-4
communications controller (SCC) 2-8
controller function 2-5 N
communications interface 1-27, 4-13,
controller jumper (J1) 1-7 D
reset 2-12 E
5-4
startup 2-3
connectors 4-18
System Fail (SYSFAIL*) signal 2-10
X
ports 2-7

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 Index

T
temperature
operating A-1
storage A-1
terminal
configuration 2-4
input/output control 3-5
tick timers 4-15
timeout
global bus 1-26
local bus 4-16
troubleshooting procedures B-1
types of reset 2-12

U
user-configurable switches 1-15, 1-17, 1-19

V
vibration tolerance (operating) A-1
VMEbus
connectors 4-18
interface 4-12
signals 5-5
VMEchip2 ASIC 4-12

W
watchdog timers 4-16
Winchester hard drive D-3

X
XON/XOFF handshaking 2-7

Z
Z85230 serial communications controller
(SCC) 2-8
I
N
D
E
X

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