sensors

Article
A 1.15 µW 200 kS/s 10-b Monotonic SAR ADC Using
Dual On-Chip Calibrations and Accuracy
Enhancement Techniques
Jae-Hun Lee, Dasom Park, Woojin Cho, Huu Nhan Phan, Cong Luong Nguyen
and Jong-Wook Lee *
School of Electronics and Information, Information and Communication System-on-Chip (SoC) Research Center,
Kyung Hee University, Yongin 17104, Korea; [email protected] (J.-H.L.); [email protected] (D.P.);
[email protected] (W.C.); [email protected] (H.N.P.) [email protected] (C.L.N.)
* Correspondence: [email protected]; Tel.: +82-31-201-3730




Received: 30 August 2018; Accepted: 13 October 2018; Published: 16 October 2018


Abstract: Herein, we present an energy efficient successive-approximation-register (SAR)

analog-to-digital converter (ADC) featuring on-chip dual calibration and various
accuracy-enhancement techniques. The dual calibration technique is realized in an energy
and area-efficient manner for comparator offset calibration (COC) and digital-to-analog converter
(DAC) capacitor mismatch calibration. The calibration of common-mode (CM) dependent
comparator offset is performed without using separate circuit blocks by reusing the DAC for
generating calibration signals. The calibration of the DAC mismatch is efficiently performed by
reusing the comparator for delay-based mismatch detection. For accuracy enhancement, we propose
new circuit techniques for a comparator, a sampling switch, and a DAC capacitor. An improved
dynamic latched comparator is proposed with kick-back suppression and CM dependent offset
calibration. An accuracy-enhanced bootstrap sampling switch suppresses the leakage-induced
error <180 µV and the sampling error <150 µV. The energy-efficient monotonic switching technique
is effectively combined with thermometer coding, which reduces the settling error in the DAC.
The ADC is realized using a 0.18 µm complementary metal–oxide–semiconductor (CMOS) process in
an area of 0.28 mm2 . At the sampling rate f S = 9 kS/s, the proposed ADC achieves a signal-to-noise
and distortion ratio (SNDR) of 55.5 dB and a spurious-free dynamic range (SFDR) of 70.6 dB.
The proposed dual calibration technique improves the SFDR by 12.7 dB. Consuming 1.15 µW at
f S = 200 kS/s, the ADC achieves an SNDR of 55.9 dB and an SFDR of 60.3 dB with a figure-of-merit
of 11.4 fJ/conversion-step.

Keywords: analog-to-digital converter; successive approximation register; comparator offset;

capacitor mismatch calibration

1. Introduction
Demand is increasing for various battery-operated sensing systems, for example, the Internet of
Things (IoT), which is deployed in various objects for biomedical, home, industrial, and environmental
monitoring [1]. For the sensor interface in these applications, very low power consumption is required
to provide a long battery lifetime.
To meet the demand, the successive approximation register (SAR) analog-to-digital converter
(ADC) has drawn much interest, due to its medium conversion rate and low-power consumption.
Various approaches have been proposed to further reduce power consumption. Compared with
the conventional structure, the average energy can be reduced by 37.5% using a capacitor splitting

Sensors 2018, 18, 3486; doi:10.3390/s18103486 www.mdpi.com/journal/sensors

Sensors 2018, 18, 3486 2 of 21

technique [2]. When monotonic capacitor switching is used, it saves up to 81.2% [3]. The energy
saving is further improved to 87.5% and 96.9% when merged capacitor switching (MCS) and tri-level
switching is used, respectively [4,5]. However, the MCS technique demands additional reference
voltage with increased circuit complexity. The tri-level switching has a similar drawback, and high
energy efficiency is achieved with complex SAR logic.
Monotonic switching uses energy-efficient down switching only. The switching is efficiently
realized using a reduced number of switches and capacitors, which simplifies the design of SAR
logic [3]. With down switching, the common-mode (CM) voltage at the digital-to-analog converter
(DAC) decreases. Therefore, CM-dependent offset calibration is desirable. In a previous work [6],
an auto-zeroed comparator is proposed for offset calibration. In reference [7], the offset calibration
is performed by using a body terminal that is controlled by a resistive DAC. These works assume a
constant CM voltage; therefore, they are not directly applicable to a monotonic SAR ADC.
Mismatch in the capacitive DAC, which occurs due to process variations and routing parasitics,
limits the linearity of the ADC. Several techniques have been reported to calibrate the mismatch [7–9].
In reference [7], both the comparator offset and mismatch calibrations are applied for a 10-bit
split-capacitor ADC; a separate calibrating DAC is used to measure the capacitor mismatch,
which consumes additional power and chip area.
Taking advantage of scaled-down complementary metal–oxide–semiconductor (CMOS) process,
various digital calibration techniques have been reported [10–13]. In reference [11], a low-power
calibration technique is presented where circuit blocks, except for the DAC and comparator,
are implemented in a field programmable gate array (FPGA). Because the capacitive DAC operates as
a single-ended circuit for error evaluation, this approach is rather sensitive to the CM noise. Moreover,
the digital calibration usually requires computationally intensive post-processing, and thus, is not
suitable for battery-operated low-power sensing applications.
In this paper, we present a low-power SAR ADC realized in an energy and area-efficient manner
for a sensor interface. The proposed ADC features (1) fully-integrated on-chip dual calibration and
(2) various accuracy-enhancement techniques.

(1) Dual calibration: The proposed calibration techniques, CM-dependent comparator offset
calibration (COC) and DAC capacitor mismatch calibration, are realized in an energy and
area-efficient manner. By reusing the DAC for generating calibration signals, the CM-dependent
comparator offset is calibrated without using separate circuit blocks for calibration. After COC,
DAC capacitor calibration is efficiently performed by reusing the comparator for delay-based
mismatch detection.
(2) Accuracy-enhancement techniques: To support the calibration operation, we propose new
accuracy-enhancement techniques for a comparator, a sampling switch, and a DAC capacitor.
We present a dynamic latched comparator, which is robust to kick-back noise. An improved
bootstrap sampling switch is proposed, which suppresses a leakage-induced error within 180 µV
and a sampling error less than 150 µV. The monotonic switching technique is effectively combined
with thermometer coding to reduce the settling error in the DAC.

The measured data indicate the successful operation of the ADC and performance improvement
by the proposed dual calibration technique. At a sampling rate of 200 kS/s, the ADC achieves a
signal-to-noise and distortion ratio (SNDR) of 55.9 dB and a spurious-free dynamic range (SFDR) of
60.3 dB with a figure-of-merit (FoM) of 11.4 fJ/conversion-step.

2. Design
Figure 1a shows a block diagram of the proposed ADC. Top-plate sampling is performed using a
bootstrap sampling switch. Monotonic switching is chosen for simple implementation. Thermometer
coding is used for the upper 3-bits and binary coding for the remaining 7-bits; the DAC consists of
thermometer-coded capacitors CT [i] and binary-weighted capacitors CB [i] (i = 0 to 6). Thermometer
requiring a high conversion rate. The drawback, is that the design of the asynchronous or variable
delay logic is rather complicated; for each transition, this approach needs to test a specific condition
(DAC voltage settling) to make sure that the previous step is finished before going to the next step.
Our work is targeted to sensor applications where a high conversion rate is not needed, but the
energy and area efficiencies are important. Although more cycles are needed, the segmented DAC
Sensors 2018, 18, 3486 3 of 21
(thermometer + binary coding) reduces differential non-linearity (DNL) errors [15]. In addition, the
monotonic switching is efficiently combined with thermometer coding; because monotonic
coding reduces
switching the size
performs of down
only the most significant
switching, thebit (MSB) capacitor
realization from 256 to 64coding
of the thermometer unit capacitors. Thus,
is achieved by
the settling error in the DAC can be reduced.
simply adding shifter registers and switches.

(a)

(b)
Figure 1. (a)
(a) Block
Block diagram
diagram of
of the
the proposed
proposed analog-to-digital
analog-to-digital converter
converter (ADC)
(ADC) with
with dual
dual calibration.
calibration.
(b) Timing sequence of the ADC.

A straightforward
The proposed ADC waysupports
to reduce athedual settling error is reserving
calibration technique different
for COC delayand
times
DACfor each DAC
capacitor
capacitor [14].
mismatch This approach
calibration. Duringreduces
the overall
COC, conversion
we note that time the
suitable for applications
capacitive DAC isrequiring
not used a high
for
conversion rate. The drawback, is that the design of the asynchronous or variable
analog-to-digital (A/D) conversion. To realize the calibration without using separate circuit blocks, delay logic is rather
complicated;
the for each
DAC is reused fortransition,
implementing this approach needs to testvoltage
the common-mode a specific condition(CMVG).
generators (DAC voltage
During settling)
COC,
ato multiplexer
make sure that the previous
(MUX) step isinputs
array selects finished before
from thegoing
CMVG to the
fornext
the step.
DAC. Our work is
During targeted
normal A/Dto
sensor applications where a high conversion rate is not needed, but the
conversion, the inputs from SAR logic are selected. The linearity of SAR ADC is affected by theenergy and area efficiencies
are important.
mismatch in theAlthough
capacitivemore
DAC.cycles are needed,
Because the segmented
high mismatch errorsDAC
occur(thermometer
for the large+ capacitors,
binary coding)the
reduces
DAC differential
mismatch non-linearity
calibration (DNL)toerrors
is applied upper[15]. In arrays.
CT[i] addition, Tothe monotonic
realize switchinginis an
the calibration efficiently
energy
combined
and with thermometer
area-efficient manner, the coding;
lowerbecause monotonic
CB[i] are switchingthey
not calibrated; performs
requireonly down switching,
sufficient intrinsic
the realization
linearity. of the thermometer
Otherwise, they set the upper coding is achieved
limit by simply adding shifter registers and switches.
on performance.
The proposed
Figure 1b showsADCthe supports
timinga sequence
dual calibration
for thetechnique
proposed fordual
COCcalibration.
and DAC capacitor
Withoutmismatch
using a
calibration.
separate Duringthe
circuit, thecomparator
COC, we note is that the capacitive
reused to detect DAC is not used
the DAC for analog-to-digital
mismatch. Therefore, COC (A/D)is
conversion.first
performed To realize
and then theDAC
calibration
mismatch without using separate
calibration follows. circuit
The COC blocks, the DAC
includes four issteps:
reused for
reset,
implementing the common-mode voltage generators (CMVG). During COC, a multiplexer (MUX)
array selects inputs from the CMVG for the DAC. During normal A/D conversion, the inputs from
SAR logic are selected. The linearity of SAR ADC is affected by the mismatch in the capacitive DAC.
Because high mismatch errors occur for the large capacitors, the DAC mismatch calibration is applied
to upper CT [i] arrays. To realize the calibration in an energy and area-efficient manner, the lower
CB [i] are not calibrated; they require sufficient intrinsic linearity. Otherwise, they set the upper limit
on performance.
Sensors 2018, 18, 3486 4 of 21

Figure 1b shows the timing sequence for the proposed dual calibration. Without using a separate
circuit, the comparator is reused to detect the DAC mismatch. Therefore, COC is performed first and
Sensors 2018, 18, x FOR PEER REVIEW 4 of 20
then DAC mismatch calibration follows. The COC includes four steps: reset, offset measurement,
writing the calibration data, and applying the calibration during A/D conversion. Similar steps are
offset measurement, writing the calibration data, and applying the calibration during A/D
used for DAC mismatch calibration: reset, mismatch measurement, and applying the calibration data.
conversion. Similar steps are used for DAC mismatch calibration: reset, mismatch measurement,
The data for the DAC mismatch calibration is static and they are applied before A/D conversion.
and applying the calibration data. The data for the DAC mismatch calibration is static and they are
The data for COC are dynamic in nature and they are applied during A/D conversion. During the
applied before A/D conversion. The data for COC are dynamic in nature and they are applied
calibration period, the SAR logic is turned off for power saving.
during A/D conversion. During the calibration period, the SAR logic is turned off for power saving.
2.1. Dynamic Latched Comparator
2.1. Dynamic Latched Comparator
The dynamic latched comparator is widely used to reduce power consumption [16]. We consider
threeThe issues dynamic
for the designlatchedof comparator is widely
the comparator: used tooperation
(1) the clocked reduce power consumption
of the comparator [16]. We
disturbs the
consider three issues for the design of the comparator: (1) the clocked operation
top plate of DAC by kick-back; (2) systematic and random device mismatch creates an offset voltage of the comparator
Vdisturbs the top plate of DAC by kick-back; (2) systematic and random device mismatch creates an
offset ; (3) during monotonic switching, V offset depends on the CM voltage V CM .
offsetFigure
voltage 2aVshows
offset; (3) during monotonic switching, Voffset depends on the CM voltage VCM.
the waveforms of the DAC voltage V DACP,N which are disturbed by the clock
Figure 2a shows
transition. In the dynamic the waveforms of the DAC
latched comparator, voltage
the input VDACP,N which
difference are disturbed
is resolved when theby thesignal
clock clock
transition.
CLK In thefrom
is switched dynamic
low to latched
high. Bycomparator, the input
the CLK transition, differencenoise
the kick-back is resolved whenat the
is generated clock
the input
signal CLK is switched from low to high. By the CLK transition, the kick-back
of the comparator by clock feed-through [17]. Then, there is a recovery period when V DACP,N settles to noise is generated at
the input of the comparator by clock feed-through [17]. Then, there is a
a stable voltage. Because this is the time when the comparator starts resolving the input difference, recovery period when
aVDACP,N settles to a stable
small asymmetry in thisvoltage.
recoveryBecause this cause
period can is theatime whenerror.
decision the comparator starts resolving the
input difference, a small asymmetry in this recovery period can cause a decision error.

(a)

(b)

Figure 2.
Figure 2. (a)
(a)Waveform
Waveformshowing
showingthethegeneration
generationofof
thethe
kick-back noise
kick-back by by
noise thethe
clocked operation.
clocked (b)
operation.
Schematic of the comparator using cascode to reduce the kick-back.
(b) Schematic of the comparator using cascode to reduce the kick-back.

Figure 2b
Figure 2bshows
showsa aschematic
schematic of of
thethe comparator.
comparator. By use
By the the of
use of auxiliary
auxiliary transistors
transistors (MRMR
(MR1 and 1 and
2 ),
MR2), hysteresis
hysteresis can existcan
in exist in the comparator
the comparator by the mismatch
by the mismatch introducedintroduced
through the through
processthe process
variations.
variations. we
Therefore, Therefore,
use the we use the common-centroid
common-centroid layouttocarefully
layout carefully suppresstothe
suppress the hysteresis.
hysteresis. In addition,In
addition,
the the comparator
comparator is carefullyisdesigned
carefullyfor
designed forsuppression
kick-back kick-back suppression and CM-dependent
and CM-dependent offset
offset calibration.
calibration. To reduce the kick-back, the input transistor pair M1,2 is shielded using three cascode
transistors MC1–3. To increase the output resistance of the MC1–3, we choose a small aspect ratio of
(W/L) = 1 μm/5 μm so that they operate in the saturation region. By the increased output resistance,
the large voltage step created by CLK transition is attenuated as it goes through the MC1–3 [18]. The
size and bias voltages for the cascode are chosen by circuit simulations. By adjusting the bias
Sensors 2018, 18, 3486 5 of 21
Sensors 2018, 18, x FOR PEER REVIEW 5 of 20

To reduceVthe
voltage kick-back, the input transistor pair M1,2 is shielded
B2, we are able to control the current through
using three
MC2,3. When VB2 iscascode
decreased transistors
from 1.2MC 0.7.
to1–3
To increase the output resistance
V with VB1 = 1 V, it effectively reduces the of the MC , we choose a small aspect ratio of
1–3peak current through MC2,3 from 7 to 1 μA during the (W/L) = 1 µm/5 µm
so that they operate in the saturation
CLK transition. In addition, we perform sizing region. By the increased output
optimization of M1,2resistance,
from W/Lthe = large
8 μm/0.5 voltage
μmstep
to 4
created by CLK transition is attenuated as it
μm/0.3 μm. By the use of cascode and the size optimization, the goes through the MC [18]. The size and bias
1–3peak value of kick-back is reduced voltages for
the cascode are chosen by circuit simulations. By
from 4 to 1 mV. Although the small-size input pair and the cascode reduceadjusting the bias voltage V , we are able to
B2 the comparator speed, control
the current through MC . When V is decreased
the proposed ADC is targeted for low-speed sensing applications. Therefore,
2,3 B2 from 1.2 to 0.7 V with V B1the= 1tradeoff
V, it effectively
does not
reduces the peak current through
greatly affect the overall performance of MC from
2,3the ADC. 7 to 1 µA during the CLK transition. In addition,
we perform
To handle sizing optimization
Voffset , the comparator of M1,2 from W/Lusing
is calibrated = 8 µm/0.5 µm to 4 µm/0.3
a binary-weighted By theBecause
µm. array.
capacitor use of
cascode and the size optimization, the peak value of kick-back is
analog offset calibration requires additional DAC [7], we choose a simple digital approach. Usingreduced from 4 to 1 mV. Although thea
small-size input pair and the cascode reduce the comparator speed,
register array to store the offset calibration data, CM-dependent offset calibration is performed (See the proposed ADC is targeted for
low-speed
Section B for sensing applications.detail.)
implementation Therefore, the tradeoff does not greatly affect the overall performance
of theThe
ADC. Voffset of the comparator consists of static (the first term) and dynamic (the second term)
To which
offsets, handlecan V offset , the comparator
be written as is calibrated using a binary-weighted capacitor array.
Because analog offset calibration requires additional DAC [7], we choose a simple digital approach.
Using a register array to store the offset calibration VSG − VTH1,2data,CM-dependent
Δ(W/ L)1,2 ΔRoffset  calibration is performed
Voffset = ΔVTH1,2 +  + load  (1)
(See Section B for implementation detail.) 2  (W/ L)1,2 Rload 
The V offset of the comparator consists of static (the first term) and dynamic (the second term)
where which
offsets, ΔVTH1,2can is the threshold
be written as mismatch, VTH1,2 is the threshold voltage, Δ(W/L)1,2 is the physical
dimension mismatch between M1 and M2, and ΔRload is the load resistance ! mismatch [3]. The
dynamic offset is attributed to charge injection, V SG − | thus
V |
TH1,2 voltage ∆ ( W/L )
dependent.
1,2 ∆Rload
Voffset = ∆VTH1,2 + + (1)
Figure 3a compares error probabilities obtained 2 by(static
W/L)and 1,2 Rload offset calibrations. The
dynamic
result is obtained using Spectre transient noise simulation with the difference Vdiff = 1 mV applied to
where ∆V TH1,2
the input of theis comparator.
the thresholdThe mismatch,
sampling V TH1,2
rate isis fsthe= 4threshold
kS/s andvoltage,
the supply ∆(W/L) 1,2 isisthe
voltage VDDphysical
= 1.8 V.
dimension
The error mismatch
probability between
is obtained , and ∆Rload
M1 andbyM2counting the iscasethe load
when resistance mismatchmakes
the comparator [3]. Thethe dynamic
wrong
offset is attributed to charge injection, thus voltage dependent.
decision out of 1000 simulations. The wrong decision is caused by the noise and the Voffset of the
Figure 3a
comparator. compares
Because error approach
the static probabilities obtained
performs the COC by static and at
one time dynamic
VCM = 0.9 offset
V, itcalibrations.
reduces the
The
static offset only. The dynamic approach performs the COC at each VCM from 0.9 to 0 V with= a1112.5
result is obtained using Spectre transient noise simulation with the difference V diff mV
applied to the input of the comparator. The sampling rate is f
mV step. And this approach reduces both the static and dynamic offsets. The result shows that thes = 4 kS/s and the supply voltage is
Vtwo = 1.8 V. The error probability is obtained by counting the case
DD approaches achieve a similar error probability at VCM = 0.9 V. In the low VCM range, however, when the comparator makes the
wrong decision
the error out ofCOC
of dynamic 1000 is simulations.
significantly The wrong
lower than decision is caused
that of static COC. by the noise and the V offset of
the comparator.
In addition, we evaluate the error probabilities as a function of Vdiff. at
Because the static approach performs the COC one time V CM 3b
Figure = 0.9
showsV, it the
reduces
error
the static offset
probability of only.
threeThe dynamic approach
comparators. The result performs the COCby
is obtained at each V CM from
performing 0.9 to
1000 0 V with
Monte Carlo a
112.5 mV step. And this approach reduces both the static and dynamic
simulations that consider both local and global process variation under a TTT corner. The result offsets. The result shows that
the two approaches
confirms that the errorachieve a similar error
is significantly probability
reduced whenatboth V CM cascode
= 0.9 V. In and low V
theCOC are range,Inhowever,
CMused. the next
the error of dynamic COC is significantly lower than
section, we describe the implementation details for realizing dynamic COC. that of static COC.

50 60
Error probability (%)

Error probability (%)

40 50

40
30
30
20
20
10 Dynamic COC w/o cascode, w/o COC
10 with cascode, w/o COC
Static COC with cascode, with COC
0 0
0.0 0.2 0.4 0.6 0.8 -2 -1 0 1 2
VCM (V) Vdiff (mV)
(a) (b)

Figure 3. Comparison
Figure of error
Comparison probability
of error as a function
probability of (a) common-mode
as a function voltage, (b)
of (a) common-mode input
voltage,
difference.
(b) input difference.
array elements. The manufacturer’s process specification provides statistical data for the mismatch
of the threshold voltage, drain current, and the transconductance as a function of device size ratio
(W/L)0.5. By using the mismatch data corresponding to the size of the input pair M1,2 into (1), we
determine a typical Voffset = 25 mV for the comparator. The proposed offset calibration method
allows an offset
Sensors 2018, correction up to ±24 least significant bits (LSB) in the 0.7 LSB step under TTT corner.
18, 3486 6 of 21
Although the process corner changes the calibration range up to 20%, the 5-bit calibration scheme
still covers the Voffset range. In addition, the delay of the comparator does not vary significantly with
In addition, we evaluate the error probabilities as a function of V . Figure 3b shows the error
the calibration code. When the mismatch in the DAC capacitor is notdiff considered, it varies from 9
probability of three comparators. The result is obtained by performing 1000 Monte Carlo simulations
(FFF corner) to 13 ns (SSS corner) with Vdiff = 0.
that consider both local and global process variation under a TTT corner. The result confirms that the
With the same VCM applied to the inputs of the comparator, the state of the capacitor is
error is significantly reduced when both cascode and COC are used. In the next section, we describe
determined in order of weight by VOUTP,N. In the case of VOUTP = 1 (VOUTN = 1), it increases the
the implementation details for realizing dynamic COC.
capacitance at V+ (V−) node. This process is repeated five times. For each VCM step, this timing
control is performed
2.2. Comparator by the shift register, which is controlled by CAL_WR. The rising edge of
Offset Calibration
CAL_WR clears the D F/F, which holds the previous data for the capacitor array. When the state of
5-bitsFigure 4a showsfor
is determined a block diagram
a given to implement
VCM, MEM_EN the dynamic
is generated fromCOC. A reset
the last stagesignal
of theRST
shiftinitializes
register,
the digital
which writeslogic
theand registers.
calibration A MUX
data to the controlled
register viabyMEM_IN[4:0].
CMP_CAL_EN Thisselects the input
operation to the
repeats DAC.
until all
When COC is enabled by CMP_CAL_EN = 1, the output from the CMVG is
nine VCM steps are processed. During normal A/D conversion, the stored data in the register are supplied to the DAC.
For normal A/D
sequentially read conversion, the output from
using MEM_OUT[4:0], whichthe SAR
sets thelogic
stateisofinput to the DAC.
the capacitor array.

(a)

(b)

Figure
Figure 4.
4. (a)(a)Block
Blockdiagram
diagramfor
for comparator
comparator offset
offset calibration,
calibration, (b)
(b) Control
Control block
block for
for the
the
binary-weighted
binary-weighted capacitors.
capacitors.

Figure 4b shows the control block for the binary-weighted capacitor array. The residual offset is
in theory reduced by half when increasing the number of calibration bits by one [19]. We determine
the number of array elements using circuit simulations. The error probability is reduced by 18.5%
and 39.5% when the number of elements is increased to two and five, respectively. Considering
the tradeoff between the complexity and the error, we choose 5-bit for the capacitor array elements.
The manufacturer’s process specification provides statistical data for the mismatch of the threshold
voltage, drain current, and the transconductance as a function of device size ratio (W/L)0.5 . By using
the mismatch data corresponding to the size of the input pair M1,2 into (1), we determine a typical
V offset = 25 mV for the comparator. The proposed offset calibration method allows an offset correction
up to ±24 least significant bits (LSB) in the 0.7 LSB step under TTT corner. Although the process
corner changes the calibration range up to 20%, the 5-bit calibration scheme still covers the V offset
range. In addition, the delay of the comparator does not vary significantly with the calibration code.
When the mismatch in the DAC capacitor is not considered, it varies from 9 (FFF corner) to 13 ns
(SSS corner) with V diff = 0.
Sensors 2018, 18, 3486 7 of 21

With the same V CM applied to the inputs of the comparator, the state of the capacitor is determined
in order of weight by V OUTP,N . In the case of V OUTP = 1 (V OUTN = 1), it increases the capacitance
at V+ (V−) node. This process is repeated five times. For each V CM step, this timing control is
performed by the shift register, which is controlled by CAL_WR. The rising edge of CAL_WR clears
the D F/F, which holds the previous data for the capacitor array. When the state of 5-bits is determined
for a given V CM , MEM_EN is generated from the last stage of the shift register, which writes the
calibration data to the register via MEM_IN[4:0]. This operation repeats until all nine V CM steps are
processed. During normal A/D conversion, the stored data in the register are sequentially read using
Sensors 2018, 18, x FOR PEER REVIEW 7 of 20
MEM_OUT[4:0], which sets the state of the capacitor array.
Figure 5 shows the schematic of the CMVG. The CMVG is implemented without using separate
Figure 5 shows the schematic of the CMVG. The CMVG is implemented without using
circuit blocks by reusing the DAC. To be compatible with monotonic switching where V CM is gradually
separate circuit blocks by reusing the DAC. To be compatible with monotonic switching where VCM
reduced, the CMVG generates nine V CM steps of each 112.5 mV in the range from 0.9 to 0 V. Each V CM is
is gradually reduced, the CMVG generates nine VCM steps of each 112.5 mV in the range from 0.9 to
generated by controlling the bottom plate of the capacitor arrays CT [6:0] and CB [6:0]. With a reference
0 V. Each VCM is generated by controlling the bottom plate of the capacitor arrays CT[6:0] and CB[6:0].
voltage of 1.8 V, a V CM step of 112.5 mV corresponds to 32 CU (CU = 31.7 fF is a unit capacitor).
With a reference voltage of 1.8 V, a VCM step of 112.5 mV corresponds to 32 CU (CU = 31.7 fF is a unit
To complete one cycle of COC, eight clocks are needed; one clock for reset, five clocks for determining
capacitor). To complete one cycle of COC, eight clocks are needed; one clock for reset, five clocks for
the state of the capacitor array, and two clocks for the data store. Therefore, we use a CLK/8 divider
determining the state of the capacitor array, and two clocks for the data store. Therefore, we use a
for the CMVG. The V changes its value at every rising edge of CLK/8.
CLK/8 divider for the DACP,N
CMVG. The VDACP,N changes its value at every rising edge of CLK/8.

Figure
Figure5.5.Block
Blockdiagram
diagramof
ofthe
thecommon-mode
common-modevoltage
voltagegenerator.
generator.

Figure showsthe
Figure 6a shows theblock
block diagram
diagram of register
of the the register
controlcontrol for writing
for writing the calibration
the calibration data
data Cal_j[4:0]
Cal_j[4:0] (j =When
(j = 1 to 9). 1 to 9). When CMP_CAL_EN
CMP_CAL_EN = 1 and MEM_EN
= 1 and MEM_EN = 1, theofoutput
= 1, the output of the
the shifter shifterprovides
register register
provides
the clock the
for clock
D F/F.for D F/F.
Then, Then, MEM_IN[4:0]
MEM_IN[4:0] are written aretowritten to thewith
the register register with the
the rising edgerising edge of
of MEM_EN.
MEM_EN.
During normal During
A/Dnormal
conversion,A/Dthe conversion,
calibration thedatacalibration
stored in the data stored
register in the register
are sequentially read are
out
sequentially
using a 9 to 1read
MUXout andusing a 9counter
a 4-bit to 1 MUX and a in
as shown 4-bit counter
Figure as shown
6b. The in Figure
calibration 6b. The
data read calibration
signal CAL_RD
data
resetsread signal
a 4-bit CAL_RD
counter andresets
starts areading
4-bit counter and with
Cal_j[4:0] startsevery
reading Cal_j[4:0]
falling edge ofwith
CLK. every falling
Figure edge
7 shows
of
theCLK. Figure
timing 7 shows
waveform forthe
thetiming waveform
comparator offsetfor the comparator
measurement, whichoffset measurement,
starts with CMP_CAL_EN which starts= 1.
with CMP_CAL_EN
For each V CM step, the = 1. For each
rising edge VofCM step, theisrising
CAL_WR used edge of CAL_WR
for reset. During the is period
used forwhenreset. During the
CAL_WR = 1,
period
the CMVGwhengenerates
CAL_WRa =V1, CMthe
to CMVG
determinegenerates
the statea Vof to determine
CMthe the state
capacitor array. of the
Then, the capacitor
calibration array.
data
Then, the calibration
MEM_IN[4:0] are storeddata
with MEM_IN[4:0]
the MEM_EN signal.are stored
When with
offset the MEM_ENforsignal.
measurement nine V CM When offset
is finished,
measurement
CMP_CAL_EN forsignal
nine V CM is finished,
becomes CMP_CAL_EN
low, which indicates thesignal
end ofbecomes low, offset
comparator whichmeasurement.
indicates the end
of comparator offset measurement.

(a) (b)

Figure 6. Block diagram of the register control for the (a) data write and (b) data read operations.

2.2. Digital-to-Analo Converter Capacitor Mismatch Calibration

of CLK. Figure 7 shows the timing waveform for the comparator offset measurement, which starts
with CMP_CAL_EN = 1. For each VCM step, the rising edge of CAL_WR is used for reset. During the
period when CAL_WR = 1, the CMVG generates a VCM to determine the state of the capacitor array.
Then, the calibration data MEM_IN[4:0] are stored with the MEM_EN signal. When offset
measurement
Sensors for nine VCM is finished, CMP_CAL_EN signal becomes low, which indicates the8 of
2018, 18, 3486 end21
of comparator offset measurement.

Sensors 2018, 18, x FOR PEER REVIEW 8 of 20

(a) (b)
already close to the ground and does not change significantly. Therefore, Cal_1[4:0] is used during
FigureWith
this period. 6. Block
the diagram of the register
end-of-conversion (EOC),
controlthe
forADC
the (a)generates and (b)
(b) data
data writeoutputs.
and data read
read operations.
operations.

2.2. Digital-to-Analo Converter Capacitor Mismatch Calibration

Figure 8 shows the timing waveform during the normal A/D conversion when the COC is
applied. Before the comparator makes a decision, the calibration data MEM_OUT [4:0] are applied
to the comparator. When CLK_RD becomes high, MEM_OUT [4:0] are read, which sets the state of
the capacitor array in the comparator. When the comparator makes a decision, thermometer-coded
Sensors 2018, 18, x FOR PEER REVIEW 8 of 20
bits T[6:0] and binary-coded bits B[6:0] are sequentially generated. When the B[6:0] switches, VCM is
already close to the ground and does not change significantly. Therefore, Cal_1[4:0] is used during
this period. With the end-of-conversion (EOC), the ADC generates outputs.

Figure
Figure 7.
7. Timing
Timing waveform
waveform for
for comparator
comparator offset
offset measurement.
measurement.

2.3. Digital-to-Analo Converter Capacitor Mismatch Calibration

Figure 8 shows the timing waveform during the normal A/D conversion when the COC is
applied. Before the comparator makes a decision, the calibration data MEM_OUT [4:0] are applied
to the comparator. When CLK_RD becomes high, MEM_OUT [4:0] are read, which sets the state of
the capacitor array in the comparator. When the comparator makes a decision, thermometer-coded
bits T[6:0] and binary-coded bits B[6:0] are sequentially generated. When the B[6:0] switches, V CM is
already close to the ground and does not change significantly. Therefore, Cal_1[4:0] is used during this
period. With the end-of-conversion (EOC), the ADC generates outputs.
Figure 7. Timing waveform for comparator offset measurement.

Figure 8. Timing waveform during normal A/D conversion when the offset calibration data are
applied.

Figure 9 shows the sequence of the calibration for detecting the DAC capacitor mismatch. The
DAC array consists of CT[i] and CB[i]. We note that the one-bit of CT[i] has a weight of 64CU. Under
the ideal matching condition, the sum of binary capacitors from CB[6] to CB[0] has the same weight,
64CU. For the DAC capacitor mismatch calibration, we detect the difference between VDACP and
VDACN, which can be used to evaluate the mismatch between the upper and lower DAC. The
proposed approach is different from the previous works [7,8,11], which evaluate the mismatch
using the DAC in the same branch. Although the previous approach can potentially achieve a better
Figure 8.
calibration
Figure 8.Timing
Timing
result, waveform
it waveform
requires during
aduring
rather normal
A/DA/D
complicated
normal conversion
whenwhen
calibration
conversion logic thewell
as
the offset offset
ascalibration
data are data
additional
calibration are
calibration
applied.
applied.
DAC. By reusing the offset-calibrated comparator, our approach evaluates the mismatch in the
DACFigure
capacitor9 shows
without thea sequence of theblock.
separate circuit calibration
A small formismatch
detectinginthe theDACDACcapacitor
capacitor mismatch.
leads to a
The Figure
DAC 9
arrayshows the
consists sequence
of C T [i] of
andthe C calibration
B [i]. We for
note detecting
that the the DAC
one-bit
slight difference between VDACP and VDACN, which leads to a large comparator delay for generating ofcapacitor
C T [i] hasmismatch.
a weight The
of
DAC
64C U
output.. array
Under consists
the of
ideal C [i] and
matching
T C [i]. We
condition,
B notethethat
sumtheofone-bit
binary of C [i]
capacitors
In the case of a large mismatch, the comparator generates output with aB relatively T has a weight
from C of
[6] 64C
to C U . Under
[0]
B shorthas
the
the ideal
same matching
weight, 64C condition,
U . For the the
DAC sum of binary
capacitor capacitors
mismatch from
calibration,C
delay. The delay is encoded using two-bit data for each CT[i]. Due to circuit complexity, CB[i]weight,
B[6]
we to C B[0]
detect has
the the same
difference between
is not
64CU. For the DAC capacitor mismatch calibration, we detect the difference between VDACP and
calibrated.
VDACN , which
Using the can be usedproperties
symmetric to evaluate of thethedifferential
mismatch structure,
between the the upper
proposed andcalibration
lower DAC. methodThe
proposed the
measures approach
mismatch is different
between from the previous
the upper and lower works
DAC.[7,8,11], which evaluate
The mismatch the mismatch
in the one-bit CT[i] is
using the DAC in the same branch. Although the previous approach
sequentially detected by using the sum of CB[i] in the other branch. The positive DAC branch can potentially achieve a better
is
calibrationfirst
evaluated result,
and itthe
requires
negative a rather
DAC branch complicated calibration
is calibrated next. logic as well ascan
The procedure additional calibration
be summarized as
Sensors 2018, 18, x FOR PEER REVIEW 9 of 20

(1) Before
Sensors starting
2018, 18, 3486 mismatch calibration, the bottom nodes of all capacitors in the DAC are reset by21
9 of
connecting them to the ground.
(2) To evaluate the mismatch error of CT[0], connect the bottom plate of CT[0] in the positive
V DACP and V
branch toDACN , which can
the reference be used
voltage VREFto and
evaluate the mismatch
generate between
VDACP. Then, connect thethe
upper and plate
bottom lowerofDAC.all
The Cproposed approach is different from the previous works [7,8,11], which evaluate
B[6:0] in the negative branch to VREF and generate VDACN. If there is a mismatch, the difference
the mismatch
using the DAC
between in the
VDACP andsame
VDACNbranch. Although
is reflected as thethe previous
output delayapproach can potentially achieve a better
in the comparator.
calibration result, it requires a rather complicated calibration
(3) The delay in the comparator is encoded using two-bit data LSB_P[1:0], logic as well as additional calibration
which represents
DAC. By reusing the offset-calibrated comparator,
mismatch information for CT[0] in the positive branch. our approach evaluates the mismatch in the DAC
capacitor
(4) withoutevaluate
Sequentially a separatethecircuit block.ofAthe
mismatch small mismatch
remaining in the DAC capacitor
thermometer-coded leads to(CaTslight
capacitors [1] −
difference between V
CT[6]) in the positive and V
DACPDAC branch.
DACN , which leads to a large comparator delay for generating output.
In the
(5) Incase
the of
samea large mismatch,
manner, the comparator
evaluate the mismatch generates output
of seven CT[i]with a relatively
in the negative short
DAC delay. The delay
branch. This
is encoded using two-bit data for each C [i]. Due to
mismatch information is encoded using two-bit data LSB_N[1:0].
T circuit complexity, C B [i] is not calibrated.

Sequenceofofthe
Figure9.9.Sequence
Figure theproposed
proposeddigital-to-analog
digital-to-analogconverter
converter(DAC)
(DAC)mismatch
mismatchcalibration.
calibration.

Using 10
Figure theshows
symmetric properties
the block diagramof the
for differential
realizing the structure,
proposedtheDAC
proposed calibration
mismatch method
calibration. It
measures the mismatch between the upper and lower DAC. The mismatch in the one-bit
consists of a DAC calibration logic, a delay detector, registers, and compensation capacitors. During CT [i] is
sequentially
mismatch detected CAL_END
calibration, by using the sum of
selects theCMUX
B [i] into
the other the
receive branch.
inputThe
frompositive
the DACDAC branch is
calibration
evaluated
logic. first and the
The calibration negative
logic DAC branch
sequentially controls is calibrated
the bottomnext.
plateThe procedure in
of capacitors canthe
bepositive
summarized
and
as follows:
negative DACs. Then, the delay detector generates LSB_P[1:0], which indicates the mismatch data
of
(1)theBefore
positive DACmismatch
starting (LSB_N[1:0] for the negative
calibration, branch).
the bottom The
nodes of all two-bit outputs
capacitors in the are
DACsequentially
are reset by
written seven times into the register.
connecting them to the ground. When the mismatch evaluation is finished for C T[0:6], the

mismatch data are retrieved from the register. There are seven register outputs for positive
(2) To evaluate the mismatch error of CT [0], connect the bottom plate of CT [0] in the positive branch
(Cal_P0[1:0]-Cal_P6[1:0]) and negative (Cal_N0[1:0]-Cal_N6[1:0]) branches. These outputs are used
to the reference voltage V REF and generate V DACP . Then, connect the bottom plate of all CB [6:0] in
to set the compensation capacitors attached to each CT[0:6] .
the negative branch to V REF and generate V DACN . If there is a mismatch, the difference between
V DACP and V DACN is reflected as the output delay in the comparator.
(3) The delay in the comparator is encoded using two-bit data LSB_P[1:0], which represents mismatch
information for CT [0] in the positive branch.
(4) Sequentially evaluate the mismatch of the remaining thermometer-coded capacitors
(CT [1] − CT [6]) in the positive DAC branch.
(5) In the same manner, evaluate the mismatch of seven CT [i] in the negative DAC branch.
This mismatch information is encoded using two-bit data LSB_N[1:0].

Figure 10 shows the block diagram for realizing the proposed DAC mismatch calibration.
It consists of a DAC calibration logic, a delay detector, registers, and compensation capacitors.
During mismatch calibration, CAL_END selects the MUX to receive the input from the DAC calibration
logic. The calibration logic sequentially controls the bottom plate of capacitors in the positive and
negative DACs.Figure
Then,10.
theBlock
delay detector
diagram forgenerates LSB_P[1:0],
realizing DAC capacitorwhich indicates
mismatch the mismatch data of
calibration.
the positive DAC (LSB_N[1:0] for the negative branch). The two-bit outputs are sequentially written
 Figure 10 shows the block diagram for realizing the proposed DAC mismatch calibration. It
consists of a DAC calibration logic, a delay detector, registers, and compensation capacitors. During
mismatch calibration, CAL_END selects the MUX to receive the input from the DAC calibration
logic. The calibration logic sequentially controls the bottom plate of capacitors in the positive and
Sensors 2018, 18, 3486
negative DACs. Then, the delay detector generates LSB_P[1:0], which indicates the mismatch10data of 21

of the positive DAC (LSB_N[1:0] for the negative branch). The two-bit outputs are sequentially
written seven
seven times intotimes into theWhen
the register. register. When theevaluation
the mismatch mismatchisevaluation
finished forisCfinished for CT[0:6], the
T [0:6], the mismatch data
mismatch
are retrieved datafromaretheretrieved from are
register. There the seven
register. There
register are seven
outputs register
for positive outputs for positive
(Cal_P0[1:0]-Cal_P6[1:0])
(Cal_P0[1:0]-Cal_P6[1:0]) and negative (Cal_N0[1:0]-Cal_N6[1:0]) branches.
and negative (Cal_N0[1:0]-Cal_N6[1:0]) branches. These outputs are used to set the These outputs are used
compensation
to set the compensation capacitors
capacitors attached to each C [0:6]. attached to each C T[0:6] .
T

Sensors 2018, 18, x FOR PEER REVIEW 10 of 20

Figure10.
Figure Blockdiagram
10.Block diagramfor
forrealizing
realizing DAC
DAC capacitor
capacitor mismatch
mismatch calibration.
calibration.
Figure 11 shows the schematic of DAC calibration logic. It consists of positive/negative branch
Figure logic,
calibration 11 shows the schematic
a clock divider, ofand
DAC a calibration
logic gate.logic. It consistsoffset
Comparator of positive/negative
and DAC mismatch branch
calibration logic, a clock divider, and a logic gate. Comparator offset and DAC
calibrations are enabled by signals CMP_CAL_EN and DAC_CAL_EN, respectively. The two mismatch calibrations
are enabledlogics
calibration by signals CMP_CAL_EN
sequentially generateand the DAC_CAL_EN,
signals to controlrespectively.
the bottom Theplatetwo
of calibration logics
the capacitors in
sequentially generate the signals to control the bottom plate of the capacitors in the
the DAC. To control the other side of the DAC, the period of positive (negative) DAC calibration isDAC. To control
the other
set by theside of the DAC, the
LSB_N_CNTL period of positive
(LSB_P_CNTL) (negative)
signal. DAC calibration
Two clock cycles are isused
set byfortheevaluating
LSB_N_CNTL the
(LSB_P_CNTL) signal. Two clock cycles are used for evaluating the comparator delay
comparator delay and writing the mismatch data to the register, which is generated by the clock and writing the
mismatch data to the register, which is generated by the clock divider. From the
divider. From the last stage of D F/F, CAL_END is generated, which indicates the end of the last stage of D F/F,
CAL_END phase.
calibration is generated, which indicates the end of the calibration phase.

Figure
Figure 11.
11. Schematic
Schematic of
of the
the DAC
DAC calibration
calibration logic.
logic.

Figure 12 shows
Figure shows thethetiming
timingwaveform
waveformofofthe theDAC
DAC calibration logic.
calibration logic.The
Thelow-level
low-leveltransition
transitionof the
of
CMP_CAL_EN signal indicates the end of COC. Then, the DAC_CAL_EN
the CMP_CAL_EN signal indicates the end of COC. Then, the DAC_CAL_EN signal is enabled tosignal is enabled to perform
the DAC the
perform capacitor
DAC mismatch
capacitor calibration
mismatch and the shiftand
calibration registers in theregisters
the shift positive inbranch calibration
the positive logic
branch
start operation.
calibration logicFirst,
start T_P0 becomes
operation. active
First, to becomes
T_P0 switch theactive
bottomto plate
switch of the
capacitor
bottom CTplate
[0] inofthecapacitor
positive
branch. During this time, LSB_N_CNTL controls the bottom plate
CT[0] in the positive branch. During this time, LSB_N_CNTL controls the bottomof capacitors C [6:0] in the negative
B plate of capacitors
branch.
C The
B[6:0] in theLSB_N_CNTL
negative branch. is enabled until mismatchisevaluations
The LSB_N_CNTL enabled untilare performed
mismatch for all CT [0:6]are
evaluations in
the positivefor
performed DAC
all Cbranch.
T[0:6] inThe
the negative branch
positive DAC calibration
branch. logic operates
The negative branchin a similar logic
calibration manner using
operates
LSB_P_CNTL.
in When the
a similar manner DACLSB_P_CNTL.
using mismatch calibration
When isthefinished,
DAC CAL_END
mismatch becomes low.is finished,
calibration
CAL_END becomes low.
Figure 13a shows the schematic of the delay detector. The detector consists of two delay
generators and D F/Fs. The outputs PSET_D1,D2 of the delay generator are used for the reference
for detecting the mismatch. They are applied to the input terminal of D F/F. Then, the sampling
operation of PSET_D1,D2 is performed by the comparator output CMP_OUT . The sampling
evaluates the amount of mismatch existing in the positive (negative) DAC branch using two-bit
data LSB_P[1:0] (LSB_N[1:0]).
 CAL_END becomes low.
Figure 13a shows the schematic of the delay detector. The detector consists of two delay
generators and D F/Fs. The outputs PSET_D1,D2 of the delay generator are used for the reference
for detecting the mismatch. They are applied to the input terminal of D F/F. Then, the sampling
operation of PSET_D1,D2 is performed by the comparator output CMP_OUT . The sampling
Sensors 2018, 18, 3486
evaluates the amount of mismatch existing in the positive (negative) DAC branch using two-bit11 of 21
data LSB_P[1:0] (LSB_N[1:0]).

Figure 12. Timing waveform for DAC capacitor mismatch calibration.

Figure 12. Timing waveform for DAC capacitor mismatch calibration.

Figure 13a shows the schematic of the delay detector. The detector consists of two delay generators
and D F/Fs. The outputs PSET_D1,D2 of the delay generator are used for the reference for detecting
the mismatch. They are applied to the input terminal of D F/F. Then, the sampling operation of
PSET_D1,D2 is performed by the comparator output CMP_OUT. The sampling evaluates the amount
of mismatch existing in the positive (negative) DAC branch using two-bit data LSB_P[1:0] (LSB_N[1:0]).
Sensors 2018, 18, x FOR PEER REVIEW 11 of 20

(a)

(b)

(c)

Figure
Figure 13.Schematic
13. (a) (a) Schematic of delay
of the the delay detector.
detector. (b) Timing
(b) Timing waveform
waveform of delay
of the the delay detector.
detector. (c)
(c) Modified
Modified latch control to avoid meta-stability.
latch control to avoid meta-stability.
The comparator delay depends on the DAC capacitor mismatch. When the mismatch error of
CT[0] in the positive branch is evaluated (See Figure 9), for example, the capacitors in the negative
branch is assumed to have sufficient intrinsic linearity; we assume the total sum of these capacitors
to be 64CU even in the case when the individual capacitor CB[i] experiences the worst-case mismatch
deviation of 1% from the ideal binary ratio. To meet the requirement, we carefully lay out the
routing paths and iteratively trim the size of each capacitor with the aid of a CAD tool. Instead of
Sensors 2018, 18, 3486 12 of 21

The comparator delay depends on the DAC capacitor mismatch. When the mismatch error of
CT [0] in the positive branch is evaluated (See Figure 9), for example, the capacitors in the negative
branch is assumed to have sufficient intrinsic linearity; we assume the total sum of these capacitors to
be 64CU even in the case when the individual capacitor CB [i] experiences the worst-case mismatch
deviation of 1% from the ideal binary ratio. To meet the requirement, we carefully lay out the routing
paths and iteratively trim the size of each capacitor with the aid of a CAD tool. Instead of SAR logic,
the DAC calibration logic controls the bottom nodes of capacitors. Then, the difference ∆V in between
V DACP and V DACN is obtained [2] using:

6
∑ CB [i ]
CT [0] + ∆CT [0] i =0
VDACP = VCM + VREF , VDACN = VCM + VREF (2)
6 6
∑ (CT [i ] + CB [i ]) + ∆CT [0] ∑ (CT [i ] + CB [i ])
i =0 i =0

where ∆CT [0] is the deviation from the ideal 64CU . Similar expressions can be written for CT [i].
The delay time tD of the comparator can be written as the sum of two terms, the load capacitor
discharge time tcharge and the latch delay time tlatch [20] as:
!
2
VDD IBIAS2
V C CL,V+
tD = tcharge + tlatch = 2CL,out TH7,8 + L,out ln (3)
IBIAS2 gm,eff 2
CL,out 8VTH7,8 gmR1,2 gm1,2 ∆Vin

where V TH7,8 is the threshold voltage of the transistor M7,8 (See Figure 2b), IBIAS2 is the bias current
of the second stage, CL,out is the output load capacitance, CL,V+ is the capacitance at the output
of the first stage, gm,eff is the effective transconductance of the back-to-back inverter, gmR1,2 is the
transconductance of the intermediate stage transistors MR1,2 , and gm1,2 is the transconductance of the
input pair. The first term of (3) is independent of ∆V in but affected by the process corner. The second
term is inversely proportional to ∆V in .
Using (2), we obtain ∆V in of 0.6 and 0.9 LSB for 1.0% and 1.5% capacitor mismatch. Considering
some margin for the mismatch, the delay generator is sized to produce proper delay so that mismatch
error from 0.5 to 1.5 LSB is detected. To prevent malfunction, we determine the proper delay in the
comparator and the delay generator by performing extensive Monte-Carlo simulations. Because the
delay in these circuits shares a global process corner, we are able to mitigate the mismatch between
delay detectors by using careful layout.
Table 1 shows the delay depending on process corners. The result shows that the comparator
delay is reduced when the process corner is changed from SSS to FFF corner as expected. Using the
difference between the total delay and the delay without mismatch, we are able to extract the delay
depending on the mismatch. Circuit simulations show that the delay has an approximate inverse
linear relationship with the error ∆V in . Therefore, the delay threshold for PSET_D1,D2 is chosen by
using three equal delay regions. To deal with the process variation, the delay is further tuned using
V TUNE1,2 in the delay generator.
Figure 13b shows the timing waveform where the mismatch is evaluated in the positive DAC
branch. When the mismatch is small, the difference between V DACP and V DACN is also small,
resulting in a relatively long delay in the comparator [21]. For example, consider the case when
the mismatch is more than 0.5 LSB but less than 1.0 LSB. In the evaluation phase, CMP_OUT rises
after PSET_D1 which sets LSB_P[0] to high and LSB_P[1] to low. The LSB_P[0:1] is subsequently
written to the register. When the delay detector samples the output of the comparator using D F/F,
meta-stability can occur. To remove this, we insert a logic gate to generate an Enable signal as shown
in Figure 13c. In this way, the Enable signal provides the clocks for D F/F in a well-defined sequence
and removes meta-stability.
 Sensors 2018, 18, 3486 13 of 21

Table 1. Delays depending on process corner and tuning voltages.

Process Corner SSS TTT FFF

Total delay * 21 17 13
CMP_OUT (ns)
Delay w/o mismatch ** 13 11 9
Delay by the mismatch 8 6 4
PSET_D1 (ns) 2.7 2 1.3
PSET_D2 (ns) 5.4 4 2.6
V TUNE1 , V TUNE2 (mV) 543, 539 496, 492 420, 414
* The delay range is obtained for the capacitor mismatch corresponding to the ∆V in from 0.5 to 1.5 LSB.
** This delay range is mainly from capacitor discharge time with ∆V in = 0. SSS (slow NMOS, slow PMOS,
slow Poly), TTT (typical NMOS, typical PMOS, typical Poly), FFF (fast NMOS, fast PMOS, fast Poly)

By the delay detector, two-bit data (LSB_P[1:0] and LSB_N[1:0]) for each CT [0:6] in the two
branches are generated. By the calibration logic, the data are sequentially written in the register
(Figure 14). The data are used to control the switch for the compensation capacitors attached to each
CT [0:6], as shown in Figure 15. Each compensation capacitor consists of 0.5CU and 1.0CU . The value
of the capacitors is chosen considering a worst-case mismatch (2%) of 64CU . The effect of calibration
can be enhanced by using both add and subtract operations. The subtract operation is implemented
by taking advantage of the differential structure [22]. To simplify the logic for the subtract operation
and consider the layout parasitic, the size of the original DAC capacitors is reduced by 0.5CU . Then,
the error compensating range is from −0.5 to +1 LSB in the 0.5 LSB step.
Sensors
Sensors2018,
2018,18,
18,x xFOR
FORPEER
PEERREVIEW
REVIEW 1313ofof2020

Figure
Figure14.
Figure 14.Schematic
14. Schematicofof
Schematic ofthe
theregister
the registerfor
register forstoring
for storingthe
storing thecalibration
the calibrationdata.
calibration data.
data.

Figure
Figure15.
15.Schematic
Schematicofofcompensation
compensationcapacitors
capacitorsininthe
thepositive
positiveDAC
DACbranch.
branch.

In order
InIn order toto
order assess
to assess the
assess the performance
the performance improvementby
performance improvement
improvement by the
by the proposed
the proposed calibration
proposed calibrationtechnique,
calibration technique,
technique,
behavioral
behavioral simulations
behavioralsimulations
simulationsare are performed
areperformed using
performedusing Matlab.
usingMatlab. By
Matlab.By including
Byincluding random
includingrandom
randomDACDAC capacitor
DACcapacitor mismatch
capacitormismatch
mismatch
inthe
inin the behavioral
thebehavioral model
modelofof
behavioralmodel the
ofthe ADC,
theADC,
ADC,we we perform
weperform 1000
perform1000 Monte-Carlo
1000Monte-Carlo simulations.
Monte-Carlosimulations. Comparator
simulations.Comparator
Comparatorand and
and
kT/C
kT/C noises
kT/Cnoises
noisesareare
arenot not included.
notincluded.
included.The The foundry
Thefoundry datasheet
foundrydatasheet shows
datasheetshows
shows1% 1% capacitor
1%capacitor mismatch
capacitormismatch whichisisais
mismatchwhich which a
a conservative
conservative estimate.
conservative estimate. Because
estimate. Because there
Because there is additional
there isis additional mismatch
additional mismatch caused
mismatch caused
caused byby routing
by routing and
routing and fringing
and fringing
fringing
components,we
components,
components, weconsider
we consider the
considerthe random
therandom mismatch
randommismatch
mismatchfrom from 1.0%
from1.0%
1.0%toto 2.5%.
to2.5%.
2.5%.
Figure
Figure1616shows
showsthetheprobability
probabilitydistribution
distributionofofan
aneffective
effectivenumber
numberofofbits
bits(ENOB)
(ENOB)before
beforeand
and
after
afterthe
themismatch
mismatchcalibration.
calibration.InInthethecase
caseofof1%
1%mismatch,
mismatch,thetheaverage
averageENOB
ENOBbefore
beforeand
andafter
after
calibration
calibrationisis8.61
8.61and
and8.87
8.87bits,
bits,respectively.
respectively.TheThestandard
standarddeviation
deviationisisreduced
reducedfrom
from0.24
0.24toto0.12
0.12
bits
bitsby
bythe
thecalibration.
calibration.InInthe
thecase
caseofof1.5%
1.5%mismatch,
mismatch,thetheaverage
averageENOB
ENOBimproves
improvesfromfrom8.29
8.29toto8.65
8.65
bits.
bits. The
The standard
standard deviation
deviation isis reduced
reduced from
from 0.33
0.33 and
and 0.25
0.25 bits
bits after
after calibration.
calibration. The
The
in the behavioral model of the ADC, we perform 1000 Monte-Carlo simulations. Comparator and
kT/C noises are not included. The foundry datasheet shows 1% capacitor mismatch which is a
conservative estimate. Because there is additional mismatch caused by routing and fringing
components, we consider the random mismatch from 1.0% to 2.5%.
Sensors 2018, 18, 3486 14 of 21
Figure 16 shows the probability distribution of an effective number of bits (ENOB) before and
after the mismatch calibration. In the case of 1% mismatch, the average ENOB before and after
calibration isFigure
8.61 16 andshows
8.87thebits,
probability distribution
respectively. Theofstandard
an effectivedeviation
number of is bitsreduced
(ENOB) before
from and 0.24 to 0.12
after the mismatch calibration. In the case of 1% mismatch, the average ENOB before and after
bits by the calibration. In the case of 1.5% mismatch, the average ENOB improves from 8.29 to 8.65
calibration is 8.61 and 8.87 bits, respectively. The standard deviation is reduced from 0.24 to 0.12 bits
bits. The standard
by the calibration.deviation
In the case of is1.5%
reduced
mismatch,from 0.33 ENOB
the average and improves
0.25 bitsfrom after
8.29 tocalibration.
8.65 bits. The
binary-weighted
The standard capacitors
deviationare not calibrated.
is reduced from 0.33 With
and 0.25thebits
quantization noise
after calibration. The and the discrete value of
binary-weighted
capacitors
compensation are not calibrated.
capacitors, these set With theupper
the quantization
limit noise and the discreteafter
on performance valuecalibration.
of compensation In the case
capacitors, these set the upper limit on performance after calibration.
when the binary capacitors are calibrated, the ENOB improves by 0.3–0.4 bits depending on the In the case when the binary
capacitors are calibrated, the ENOB improves by 0.3–0.4 bits depending on the mismatch. In addition,
mismatch. In addition, we perform simulations for static nonlinearity. For 2% mismatch, the peak
we perform simulations for static nonlinearity. For 2% mismatch, the peak DNL is +0.09/−0.63 LSB
DNL is +0.09/−0.63
before calibration LSBandbefore calibration
it is reduced to +0.08/and it LSB
−0.32 is reduced to +0.08/−0.32
after calibration. LSB after
The peak integral calibration. The
non-linearity
peak integral non-linearity
(INL) is +1.71/ −1.72 LSB (INL) is +1.71/−1.72
before calibration and it isLSB before
improved calibration
to +0.74/ −0.75 LSB and
afteritcalibration.
is improved to
The result shows that the proposed DAC mismatch calibration
+0.74/−0.75 LSB after calibration. The result shows that the proposed DAC mismatch is effective at improving both dynamic
calibration is
and static performances of the ADC.
effective at improving both dynamic and static performances of the ADC.

400 400
Before cal. Before cal.
After cal. After cal.
# of occassion
# of occassion

300 300

200 200

100 100

0 0
5 6 7 8 9 10 5 6 7 8 9 10
ENOB (bit) ENOB (bit)
Sensors 2018, 18, x FOR PEER REVIEW (a) (b) 14 of 20

400 400
Before cal. Before cal.
After cal. After cal.
# of occassion
# of occassion

300 300

200 200

100 100

0 0
5 6 7 8 9 10 5 6 7 8 9 10
ENOB (bit) ENOB (bit)
(c) (d)
Figure
Figure 16. 16. Probability
Probability distributions
distributions of of
ananeffective
effective number
numberof ofbitsbits
(ENOB)
(ENOB)beforebefore
and after
andDAC
after DAC
capacitor mismatch calibration. Capacitor mismatches are (a) 1.0%, (b) 1.5%, (c) 2.0%, (d) 2.5%.
capacitor mismatch calibration. Capacitor mismatches are (a) 1.0%, (b) 1.5%, (c) 2.0%, (d) 2.5%.
2.4. Bootstrap Sampling Switch
2.3. BootstrapFigure
Sampling Switch
17 shows the proposed bootstrap sampling switch. Based on the previous work [23], it is
modified to reduce leakage-induced error (off-state) and sampling error (on-state). It consists of a
Figure 17 shows the proposed bootstrap sampling switch. Based on the previous work [23], it
booster, a sampling switch, and a clamping circuit.
is modified to reduce leakage-induced error (off-state) and sampling error (on-state). It consists of a
booster, a sampling switch, and a clamping circuit.
2.3. Bootstrap Sampling Switch
Figure 17 shows the proposed bootstrap sampling switch. Based on the previous work [23], it
is modified to reduce leakage-induced error (off-state) and sampling error (on-state). It 15
Sensors 2018, 18, 3486
consists
of 21
of a
booster, a sampling switch, and a clamping circuit.

FigureFigure
17. Schematic of the
17. Schematic proposed
of the proposed bootstrap sampling
bootstrap sampling switch.
switch.

The sampling error defined by the difference between V and V occurs due to the
The sampling error defined by the difference between DACP VDACP andINPVINP occurs due to the
on-resistance of the switch. To reduce the resistance, a boosted voltage of about 2V DD is applied
on-resistance
to theofgate
theofswitch.
N1 and To reduce the
N2 through thecapacitor
resistance, CC2 .a In
boosted
addition, voltage of about
P1 in parallel with2VNDD is applied to
1 forms a
the gate transmission-gate
of N1 and N2 which through thereduces
further capacitor CC2. In addition,
the on-resistance. To reduce P1 thein leakage-induced
parallel with N 1 forms a
error,
transmission-gate which further 1reduces
the threshold voltages of N and N 2 the on-resistance. To reduce the leakage-induced error, the
(both are inside deep n-well) are increased by controlling the
body terminal. When the sampling
threshold voltages of N1 and N2 (both are inside clock CLKS is high,n-well)
deep the bodyare voltage V b1,2 is by
increased set to the threshold
controlling the body
voltage of P2 by the clamping circuit. When CLKS goes low, V b1,2 is reduced by V DD through the
terminal. When the sampling clock CLKS is high, the body voltage Vb1,2 is set to the threshold
capacitor CC1 , which is about −1.3 V. The size of these transistors is optimized by considering the
P2 bybetween
voltage oftradeoff the clamping circuit.and
the on-resistance When CLKS goes
leakage-induced low, Vb1,2 is reduced by VDD through the
error.
capacitor CC1,Figurewhich 18aiscompares
about −1.3 V. The size of
the leakage-induced errorthese transistors
as a function is . optimized
of V INP by considering
The result is obtained from the
tradeoff between
post-layout the on-resistance
simulations and leakage-induced
with a sampling rate of 3 kS/s. The error.
V DACP is measured at 1 ms after the input
V
FigureINP18a compares the leakage-induced error as a shown;
is sampled. Three cases of the bootstrap switch (BS) are function(1) BS-1
of V having transmission-gate
INP. The result is obtained
without a clamping circuit; (2) BS-2 having a clamping circuit and the series switch (N1 and N2 )
from post-layout simulations with a sampling rate of 3 kS/s. The VDACP is measured at 1 ms after the
only [23]; (3) BS-3 having a clamping circuit and the transmission-gate (Figure 17). In the case of BS-1,
input VINP theis sampled. Three
leakage-induced cases of
error increases with the
V INPbootstrap
reaching 800 switch
µV at V(BS) are shown; (1) BS-1 having
INP = 1.8 V. The result shows that
transmission-gate without
BS-3 has a smaller errora than
clamping circuit;
that of BS-2 except(2) BS-2
at V having a clamping circuit and the series
INP = 1.8 V; BS-3 shows a leakage-induced error
switch (Nless
1 and
thanN 502)µV
only [23];
up to V INP(3) BS-3
= 1.7 having
V. The a clamping
worst-case error is 180circuit and18bthe
µV. Figure transmission-gate
shows the sampling error (Figure
as a function
17). In the case of BS-1, theof V . The turn-on voltage of the sampling
INP leakage-induced error increases with VINP switch is 2V . The gate-to-source
DDreaching 800 μV at voltage
VINP = 1.8 V.
V gs of the switch, thus, the turn-on resistance depends on V INP . This causes the sampling error to
The result shows that BS-3 has a smaller error than that of BS-2 except at VINP = 1.8 V; BS-3 shows a
vary with the input. A constant V gs bootstrapping technique is reported [24]; it can be challenging
leakage-induced error less than 50 μV up to VINP = 1.7 V. The worst-case error is 180 μV. Figure 18b
to implement this technique under different process corners. Another work focuses on reducing
shows thethesampling error asonly
turn-on resistance a function
[25]; this of VINP. The
approach turn-on
can suffer fromvoltage of the
the leakage sampling
error switchatis 2VDD.
when operated
The gate-to-source
a low sampling voltage
rate. TheVgs result
of the showsswitch,
that thethus,
BS-3theshowsturn-on
overall resistance
smaller errordepends
than that ofonBS-2;
VINP. This
causes thethesampling
sampling errorerroristo reduced
vary withby using
theainput.
transmission-gate.
A constantBS-3 Vgs shows a worst-case
bootstrapping sampling error
technique is reported
of 150 µV, which is higher than that of BS-1. However, the high leakage-induced error of BS-1 is not
[24]; it can be challenging to implement this technique under different process corners. Another
suitable for our application.
work focuses on reducing the turn-on resistance only [25]; this approach can suffer from the leakage
error when operated at a low sampling rate. The result shows that the BS-3 shows overall smaller
 Sensors 2018, 18, x FOR PEER REVIEW 15 of 20
error than that of BS-2; the sampling error is reduced by using a transmission-gate. BS-3 shows a
worst-case
error than sampling error
that of BS-2; the of 150 μV,
sampling which
error is higher
is reduced than athat
by using of BS-1. However,
transmission-gate. the high
BS-3 shows a
leakage-induced error of BS-1 is not suitable for our application.
worst-case sampling error of 150 μV, which is higher than that of BS-1. However, the high
Sensors 2018, 18, 3486 16 of 21
leakage-induced error of BS-1 is not suitable for our application.
800 300
BS-1: w/o clamp and T-gate
800 300
Leakage error (μV)
BS-2: with clamp and series switch

(μV)(μV)
BS-1:with
w/oclamp,
clamp and T-gate 200
600 BS-3: series, T-gate
Leakage error (μV)

BS-2: with clamp and series switch

200

error
600 BS-3: with clamp, series, T-gate
100

error
400 100

Sampling
400 0

Sampling
0
200
-100 BS-1: w/o clamp and T-gate
200 BS-2:w/o
with clamp and series switch
-100 BS-1: clamp and T-gate
BS-3:with
BS-2: withclamp
clamp, series,
and seriesT-gate
switch
0 -200
0.0 0.3 0.6 0.9 1.2 1.5 1.8 BS-3:
0.3 with
0.6clamp,0.9
series,1.2
T-gate 1.5
0 -200 0.0 1.8
0.0 0.3 0.6
Input0.9
(V) 1.2 1.5 1.8 0.0 0.3 0.6 Input
0.9 (V)1.2 1.5 1.8
Input (V) Input (V)
(a) (b)
(a) (b)
Figure 18. Comparison of three bootstrap sampling switches for (a) leakage-induced error and (b)
Figure 18.
Figure
sampling Comparison
18.
errorComparison
as a function ofofthree
thebootstrap
three
of input. sampling
bootstrap switches for
sampling switches for(a)
(a)leakage-induced
leakage-induced error
error and
and (b)(b)
sampling
sampling error
error asasa afunction
functionof ofthe
theinput.
input.

3. Measured
3. MeasuredResults
Results
3. Measured Results
Figure 19 shows
Figure 19 shows thethemicrophotograph
microphotograph of
of the ADC
ADC fabricated
fabricatedwith
with a 0.18
a 0.18 µmμm CMOS
CMOS process.
process.
Figure 19 shows the microphotograph of the ADC fabricated with a 0.18 μm CMOS process.
2. 2 .
The The
corecore
areaarea is 0.28
is 0.28 mm mm
The core area is 0.28 mm2.

Figure19.
Figure
Figure 19. Microphotograph of
19.Microphotograph
Microphotograph offabricated
of fabricated
fabricatedADC.
ADC.
ADC.

Figure
Figure 20 comparesDNL/INL
DNL/INLofofthe theADC
ADC before and after COC and DAC capacitor mismatch
Figure 2020compares
compares DNL/INL of the ADC before and
and after
afterCOC
COCand andDAC
DACcapacitor
capacitormismatch
mismatch
calibration. A total of 51,200 codes are collected to build a histogram. The peak DNL is +1.79/−1.0 LSB
calibration.AAtotal
calibration. totalofof51,200
51,200 codes
codes are
are collected
collected to build
build aa histogram.
histogram.The Thepeak
peakDNLDNLisis+1.79/−1.0
+1.79/−1.0
before calibration and it is +0.94/−0.98 LSB after calibration. We note that there is no missing code after
LSB before
LSB calibration. calibration
before calibration and it is +0.94/−0.98 LSB after calibration. We note that there is nonomissing
The peak and it +3.06/
INL is is +0.94/−0.98
−3.17 LSBLSB after
before calibration.
calibration and itWe note that
is reduced there −is1.61
to +1.32/ missing
LSB
code
codeafter after
after calibration. The peak INL is +3.06/−3.17 LSB before calibration and it is reducedtoto
calibration. The peak INL is +3.06/−3.17 LSB before calibration and it is reduced
calibration.
+1.32/−1.61
+1.32/−1.61 LSBafter
LSB aftercalibration.
calibration.
Figure 21 compares the measured output spectra of the ADC before and after calibration. The data
Figure2121from
isFigure
obtained compares
compares the
the FFTthe measured
measured
spectrum output
withoutput spectra
spectra
9000 points. of the
the ADC
ADCbefore
ofperforming
After before and
COC, theand after calibration.
afterand
SNDR SFDR areThe
calibration. The
data is
dataimproved obtained
is obtained from
from
by 3.3 the
andthe FFT spectrum
FFTrespectively.
9.7 dB, spectrum with with 9000
When9000 points.
points.
the DAC After performing
After calibration
mismatch performing COC, the
COC, the
is applied, SNDR
the SNDR and
SNDR and
SFDR
SFDR and are
are improved
SFDR
improved by3.3
are improved
by 3.3and
and
by 2.89.7
9.7 dB,3respectively.
and
dB, respectively. When
dB, respectively.
WhenWhenthe DAC
theboth
DACCOCmismatch
and DAC
mismatch calibration isisapplied,
calibrations
calibration are
applied,
the SNDR and SFDR are improved by 2.8 and 3 dB, respectively. When both COC andDAC
theperformed,
SNDR and the SFDR
SNDR are
and improved
SFDR are by 2.8 and
improved to 3 and
55.5 dB, 70.6
respectively.
dB, Whenresulting
respectively, both COC in anand
ENOB DAC
calibrations
of 8.9 bits. are performed, the SNDR and SFDR are improved to 55.5 and 70.6 dB, respectively,
calibrations are performed, the SNDR and SFDR are improved to 55.5 and 70.6 dB, respectively,
resulting in an ENOB of 8.9 bits.
resulting in an ENOB of 8.9 bits.
Sensors 2018, 18, 3486 17 of 21
Sensors 2018, 18, x FOR PEER REVIEW 16 of 20
Sensors 2018, 18, x FOR PEER REVIEW 16 of 20

2
2

1
1

(LSB)
DNL(LSB)
0
0

DNL
-1
-1

-2
-2 0 200 400 600 800 1000
0 200 400 600 800 1000
(a)
(a)
3
3
2
2
1
(LSB)

1
INL(LSB)

0
0
-1
INL

-1
-2
-2
-3
-3 0 200 400 600 800 1000
0 200 400Digital code
600 800 1000
Digital code
(b)
(b)
Figure 20. Measured static nonlinearity of ADC. (a) differential non-linearity (DNL), (b) integral
Figure Measured
20. 20.
Figure Measured static
staticnonlinearity
nonlinearity of
of ADC.
ADC. (a)
(a) differential non-linearity(DNL),
differential non-linearity (DNL),
(b)(b) integral
integral
non-linearity (INL).
non-linearity
non-linearity (INL).
(INL).
0
0 SNDR = 49.4 dB
-20 SNDR
SFDR == 57.9
49.4 dB
dB
(dB)

-20 SFDR
ENOB == 57.9
7.91 dB
Amplitude(dB)

bit
-40 ENOB = 7.91 bit
-40
Amplitude

-60
-60
-80
-80
-100
-100
-120
-120 0 1 2 3 4
0 1 2
Frequency (kHz) 3 4
Frequency (kHz)
(a)
(a)
0
0 SNDR = 52.7 dB
-20 SNDR
SFDR == 67.6
52.7 dB
dB
(dB)

-20 SFDR
ENOB == 67.6
8.46 dB
Amplitude(dB)

bit
-40 ENOB = 8.46 bit
-40
Amplitude

-60
-60
-80
-80
-100
-100
-120
-120 0 1 2 3 4
0 1 2
Frequency (kHz) 3 4
Frequency (kHz)
(b)
(b)
0
0 SNDR = 55.5 dB
-20 SNDR
SFDR == 70.6
55.5 dB
dB
(dB)

-20 SFDR
ENOB == 70.6
8.92 dB
Amplitude(dB)

bit
-40 ENOB = 8.92 bit
-40
Amplitude

-60
-60
-80
-80
-100
-100
-120
-120 0 1 2 3 4
0 1 2
Frequency (kHz) 3 4
Frequency (kHz)
(c)
(c)

Figure 21. Measured output spectra of the ADC. (a) Before calibration, (b) after comparator offset
calibration, and (c) after both comparator offset and DAC capacitor mismatch calibrations. f S = 9 kS/s,
f IN = 1.32 kHz.
 Sensors 2018, 18, x FOR PEER REVIEW 17 of 20
Figure 22a shows the measured SNDR and SFDR before and after calibrations as a function of
input frequency fIN. Figure 22b shows the measured SNDR and SFDR before and after calibrations
Figure 21. Measured output spectra of the ADC. (a) Before calibration, (b) after comparator offset
for sampling rate fS up to 100 kS/s. We characterize the ADC using a high fIN.
calibration, and (c) after both comparator offset and DAC capacitor mismatch calibrations. fS = 9 kS/s,
Figure 23 shows measured spectra of the ADC for fIN = 20.35 kHz. When both COC and DAC
fIN = 1.32 kHz.
calibration
Sensors 2018, are performed, the measured SNDR and SFDR are 56.2 and 70.3 dB, respectively,
18, 3486 18 of 21
resulting in an ENOB of 9.0 bits. At the Nyquist frequency, the measured
Figure 22a shows the measured SNDR and SFDR before and after calibrations as a functionSNDR and SFDR are 55.9of
and 60.3 dB, respectively.
input frequency fIN. Figure 22b shows the measured SNDR and SFDR before and after calibrations
Figure24a
Figure 22ashows
shows the measured SNDR and SFDR before andof faafter calibrations as a function
with fINof
for sampling rate fS upmeasured
to 100 kS/s.SNDR and SFDR
We characterize as a ADC
the function
using IN. The
high fINSFDR
. decreases
input
and the frequency
SNDR f . Figure 22b shows the measured SNDR and SFDR before and after calibrations for
Figure 23 remains
IN
shows relativelyspectra
measured constant ofup
thetoADC
100 for
kHz.fINFigure
= 20.3524bkHz.shows
When measured
both COC SNDR and
and DAC
sampling
SFDR rate f S up
as a function oftofS.100
BothkS/s.
SNDR Weand
characterize
SFDR the ADC
remain a high f IN
usingconstant
relatively . to fS = 200 kS/s.
up
calibration are performed, the measured SNDR and SFDR are 56.2 and 70.3 dB, respectively,
resulting in an ENOB of 9.0 bits. At the Nyquist frequency, the measured SNDR and SFDR are 55.9
80 80
and 60.3 dB, respectively.
Figure
70 24a shows measured SNDR and SFDR as a function
70 of fIN. The SFDR decreases with fIN
SNDR, SFDR (dB)

SNDR, SFDR (dB)

and the SNDR remains relatively constant up to 100 kHz. Figure 24b shows measured SNDR and
60 60
SFDR as a function of fS. Both SNDR and SFDR remain relatively constant up to fS = 200 kS/s.
50 50
80 SNDR w/o offset cal. 80 SNDR w/o cal.
40 SNDR with offset cal. 40 SNDR with offset cal.
SNDR with offset & mismatch cal. SNDR with offset & mismatch cal.
70 70
SFDR w/o offset cal. SFDR w/o cal.
30
SNDR, SFDR (dB)

30 SFDR with offset cal.

SNDR, SFDR (dB)

SFDR with offset cal.
60 SFDR with offset & mismatch cal. 60 SFDR with offset & mismatch cal.
20 20
1 2 3 4 5 0 20 40 60 80 100
50 50
Input frequency (kHz) Sampling rate (kS/s)
SNDR w/o offset cal. SNDR w/o cal.
SNDR with(a) 40
offset cal. 40 SNDR with offset cal.
(b)
SNDR with offset & mismatch cal.
SNDR with offset & mismatch cal.
SFDR w/o offset cal. SFDR w/o cal.
30 22. 30
Figure
Figure 22.Measured
Measured signal-to-noise
signal-to-noise
SFDR with offset cal.
and anddistortion
distortionratioratio(SNDR)
(SNDR)and spurious-free
SFDR
and with offset cal. dynamic
spurious-free dynamicrange
range
SFDR with offset & mismatch cal. SFDR with offset & mismatch cal.
(SFDR)
(SFDR)asasa function
a function of (a)
of (a)input
input frequencies
frequencies with
withf Sf =
S
9
= kS/s,
9 (b)
kS/s,20 sampling
(b) rates
sampling with
rates withf IN =IN1.35
f = kHz.kHz.
1.35
20
1 2 3 4 5 0 20 40 60 80 100

Figure 23 shows 0
Inputmeasured
frequency spectra of the ADC for f IN = 20.35Sampling
(kHz) kHz. Whenrate (kS/s)
both COC and
After calibration
DAC calibration are performed,
(a)
-20 the measured SNDR and SFDR
SNDR = 56.2 dB are 56.2 and
(b) 70.3 dB, respectively,
Amplitude (dB)

resulting in an ENOB of -40 SFDR = 70.3 dB

9.0 bits. At the Nyquist frequency, the measured SNDR and SFDR are 55.9
Figure 22. Measured signal-to-noise and distortion ratio= 9.03
ENOB (SNDR)
bit and spurious-free dynamic range
and 60.3 dB, respectively.-60
(SFDR) as a function of (a) input frequencies with fS = 9 kS/s, (b) sampling rates with fIN = 1.35 kHz.
-80

-100 0
After calibration
-20
-120 SNDR = 56.2 dB
Amplitude (dB)

0 10 20 30 40 50
SFDR60 = 70.370
dB 80 90 100
-40
ENOB
Frequency = 9.03 bit
(kHz)
-60
(a)
-80
0
-100 After calibration
-20 SNDR = 55.9 dB
Amplitude (dB)

-120 SFDR = 60.3 dB

-40 0 10 20 30 40 50 60
ENOB = 8.98 bit70 80 90 100
-60 Frequency (kHz)
-80 (a)
-100 0
After calibration
-20
-120 SNDR = 55.9 dB
Amplitude (dB)

0 10 20 30 40 50
SFDR60 = 60.370
dB 80 90 100
-40
ENOB
Frequency = 8.98 bit
(kHz)
-60
(b)
-80
Figure 23. Measured output
-100 spectra of the ADC at (a) fIN = 20.35 kHz, (b) fIN = 99.35 kHz. fS = 200 kS/s.

-120
0 10 20 30 40 50 60 70 80 90 100
Frequency (kHz)
(b)

Figure 23. Measured

Figure Measuredoutput spectra
output of the
spectra of ADC at (a) fat
the ADC IN =(a)
20.35
f INkHz, (b) fINkHz,
= 20.35 = 99.35
(b)kHz.
f IN f=S =99.35
200 kS/s.
kHz.
f S = 200 kS/s.

Figure 24a shows measured SNDR and SFDR as a function of f IN . The SFDR decreases with f IN
and the SNDR remains relatively constant up to 100 kHz. Figure 24b shows measured SNDR and
SFDR as a function of f S . Both SNDR and SFDR remain relatively constant up to f S = 200 kS/s.
Sensors 2018, 18, 3486 19 of 21
Sensors 2018, 18, x FOR PEER REVIEW 18 of 20

75
70

SNDR, SFDR (dB)

65
60
55
SNDR
50 SFDR
45
10 20 30 40 50 60 70 80 90 100
Input frequency (kHz)
(a)
75
SNDR, SFDR (dB)

70
65
60
55
50
SNDR
SFDR
45
0 50 100 150 200 250 300
Sampling rate (kS/s)
(b)
Figure 24.
24. (a)
(a) Measured
Measured SNDR
SNDRandandSFDR
SFDRatatdifferent
differentinput
inputfrequencies.
frequencies.f SfS== 200
200kS/s,
kS/s, (b) Measured
and SFDR
SNDR and SFDR at
at different
different sampling
sampling rates.
rates. ffIN
IN ==4.35
4.35kHz.
kHz.

The overall power consumption of the ADC is 1.15 µW. μW. The
The power
power breakdown
breakdown shows
shows that the
DAC, the comparator,
comparator, SAR
SAR logic,
logic, and
and calibration
calibration blocks
blocks consume
consume 101
101 (8.8%),
(8.8%), 516
516 (44.9%),
(44.9%), 280
280 (24.3%),
(24.3%),
and 253 nW
nW (22%),
(22%), respectively.
respectively. Comparison
Comparison withwiththe
theother
otherworks
worksisisshown
shownin inTable
Table2.2.

Table 2. Comparison
Table 2. Comparison with
with other
other works.
works.

[11] [11] [26][26]

[28]
[28] [29] [27]
[29] This
[27]Work
This Work
Technology
Technology (nm)(nm) 130 130 180180 130
130 65
65 130130 180180
Supply voltage
Supply (V) (V) 0.5 0.5
voltage 0.6 0.6 0.5
0.5 0.55 1.0/0.4
0.55 1.0/0.4 1.8/1.0
1.8/1.0
Resolution (bit) (bit)
Resolution 11 11 10 10 1313 10
10 10 10 10 10
Sampling rate (kS/s) 10 200 40 20 1 200
Sampling rate (kS/s) 10 200 40 20 1 200
SNDR (dB) 61.8 57.5 66.3 55.0 56.7 55.9
SNDR
SFDR (dB) (dB) 77.5 61.8 66.757.5 66.3
71.0 55.0
68.8 56.767.6 55.9
60.3
SFDR
ENOB * (bit) (dB) 77.5 66.7
† 71.0 68.8 67.6 60.3
9.93 9.26 10.7 8.84 9.1 8.98
ENOB @Nyquist
* (bit) @Nyquist 9.93 9.26 † 10.7 8.84 9.1 8.98
Calibration Off-chip
Calibration Off-chip - - On-chip
On-chip -- - - On-chip
On-chip
Core area (mm2 ) 0.58 0.08 0.90 0.21 0.19 0.28
Power (µW) (mm ) 0.73 †† 0.58 1.040.08
Core area 2 0.90
1.47 0.21
0.21 0.190.05 0.28
1.15
Power (μW)
FoM (fJ/conv-step) 74.8 0.73 †† 8.01.04 1.47
17.9 0.21
22.4 0.0594.5 1.15
11.4
FoM (fJ/conv-step)
† Input frequency †† 74.8 8.0 17.9 22.4 94.5 11.4
of 20 kHz. Not including the power consumption of FPGA. * ENOB = (SNDR − 1.76)/6.02.
† Input frequency of 20 kHz. †† Not including the power consumption of FPGA. * ENOB = (SNDR −
The work in reference [11] presents a low-power (~0.7 µW) SAR ADC for which calibration is
1.76)/6.02.
performed off-chip. The work in [27] presents a 13-bit SAR ADC with on-chip calibration in a relatively
largeThe
areawork
of 0.9inmm 2 using 0.13 µm CMOS. Our work is realized using 0.18 µm CMOS in a compact
reference [11] presents a low-power (~0.7 μW) SAR ADC for which calibration is
chip area of off-chip. 2
0.28 mm The. Both the works
performed work in [27][28,29]
presentsshow a relatively
13-bit SAR low-power
ADC with consumption, however, in
on-chip calibration it isa
achieved
relativelywith
largerelatively low
area of 0.9 mm f S 2=using
20 and
0.131 kS/s,
μm CMOS.respectively. To capture
Our work all these
is realized usingtradeoffs,
0.18 μm we can in
CMOS usea
the figure-of-merit (FoM), which is defined as:
compact chip area of 0.28 mm . Both the works [28,29] show relatively low-power consumption,
2

however, it is achieved with relatively low fS = 20 and 1 kS/s, respectively. To capture all these
Power Power
tradeoffs, we can use the figure-of-merit
FoM = (FoM), which
= is defined as: (4)
f S × 2ENOB 2 × ERBW × 2ENOB
Pow er Pow er
FoM = = (4)
f S × 2 EN O B 2 × ER BW × 2 EN O B
Sensors 2018, 18, 3486 20 of 21

where effective resolution bandwidth (ERBW) is approximately equal to half of the sampling frequency.
The work in [26] shows a good FoM of 8.0 fJ/conv-step using a bypass window, however, it requires a
fine-tuned reference voltage to accurately set the bypass window. Consuming 1.15 µW at f S = 200 kS/s,
the ADC in this work achieves a good FoM of 11.4 fJ/conv-step.

4. Conclusions
We present a low-power SAR ADC with dual on-chip calibration technique applied for
COC and DAC capacitor mismatch correction. The proposed calibration technique is realized
in an energy and area-efficient method that does not use separate circuit blocks. In addition,
various accuracy-enhancement techniques further improve the performance of the ADC. A monotonic
switching technique is efficiently combined with thermometer coding to reduce the error caused
by incomplete settling. The CM-dependent comparator offset is dynamically calibrated by reusing
the differential DAC. In addition, the dynamic latched comparator is carefully designed to remove
decision errors due to kick-back noise. The evaluation of the DAC capacitor mismatch is performed
by reusing the comparator for delay measurement. The calibration of the DAC mismatch in the
thermometer-coded seven MSB bits is efficiently performed by using the symmetry property of the
differential structure. Measured data show the successful operation of the proposed dual calibration
technique. At f S = 9 kS/s, the proposed ADC achieves the measured SNDR of 55.5 dB and the SFDR of
70.6 dB. At an increased f S = 200 kS/s, the ADC achieves an SNDR of 55.9 dB and an SFDR of 60.3 dB
with a FoM of 11.4 fJ/conversion-step. The results indicate the potential of our work for low-power
sensing applications.

Author Contributions: J.-H.L. designed the ADC and setup, performed the experimental work, and wrote the
manuscript. D.P. provided the idea of comparator offset calibration and wrote the manuscript. W.C. performed
debugging of the ADC. H.N.P. performed Monte-Carlo simulations. C.L.N. performed analysis on the comparator
offset calibration. J.-W.L. conceived the project, organized the paper content, and edited the manuscript.
Funding: This research was supported by the Basic Science Research Program through the National Research
Foundation of Korea (NRF-2018R1A2A2A05018621).
Acknowledgments: The chip fabrication and CAD tools were made available through the IDEC (IC Design
Education Center).
Conflicts of Interest: The authors declare no conflict of interest.

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