AFE79XX JESD APP NOTE

REV 0.9 05/02/2020

AFE79xx: JESD App Note

Fs is the DC PLL frequency.
RX is Receiver chain.
TX is Transmitter chain.
FB is Feedback chain.

This document deals with basics of JESD and debug hooks for JESD link. It doesn’t deal with programming and assumes the programming
is correctly done, as generated by the Latte tool.

1. JESD Blocks overview:

Refer to the Configuration App Note.

2. Accessing JESD registers:

For accessing JESD registers, first the appropriate page should be selected.

Select Channel Page select Write

Address Data
JESD TX 0 0x0016 0x01
JESD TX 1 0x0016 0x02
JESD TX 0 &1 0x0016 0x03
JESD RX 0 0x0016 0x04
JESD RX 1 0x0016 0x08
JESD RX 0 & 1 0x0016 0x0C
SERDES 0 0x0016 0x20
SERDES 1 0x0016 0x40
SERDES 0 &1 0x0016 0x60
SUBCHIP 0x0016 0x10

There are two types of SERDES registers. Some registers are common to the 4 lanes, and there are lane specific registers.
Accessing the SERDES registers is not direct as they are 16-bit wide and SPI is 8-bit. For writing to register address, A, first write the
MSB 8-bits of the data to address 2*((A+0x2000)[13:0])+1 and then the LSB 8-bits to 2*((A+0x2000)[ [13:0]). Accessing only 8-bits
is not possible. The complete 16-bits should be accessed in the same sequence.
For example to write 0x1234 to register 0x8413,
Step 1: Data to write is 0x12. Address to write 0x413*2+1=0x827.
0x4827 0x12
Step 2: Data to write is 0x34. Address to write 0x413*2=0x826.
0x4826 0x34

Read is also similar, however, each read should happen twice and only the second read is valid. To read register, 0x8413,
Step1: Read 0x4827 discard the read.
Step2: Read 0x4827 the read back value is the MSB.
Step3: Read 0x4826 discard the read.
Step4: Read 0x4826 the read back value is the LSB.

Note: In register map, the MSB and LSB addresses are directly given. While accessing, you need to access both together. Not doing so
will result in invalid access to SerDes resulting in bad state of SerDes which can be recovered from only on reset.
Lane Page Select Serdes Lane Prefix (16-bit Serdes Lane Prefix (8-Bit
Format) Format)
1 0x0016 0x20 0x81xx 0x42xx, 0x43xx
2 0x0016 0x20 0x80xx 0x40xx, 0x41xx
3 0x0016 0x20 0x82xx 0x44xx, 0x45xx
4 0x0016 0x20 0x83xx 0x46xx, 0x47xx
5 0x0016 0x40 0x83xx 0x46xx, 0x47xx
6 0x0016 0x40 0x82xx 0x44xx, 0x45xx
7 0x0016 0x40 0x80xx 0x40xx, 0x41xx
8 0x0016 0x40 0x81xx 0x42xx, 0x43xx

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3. SERDES PLL:
There is one PLL each for SERDES TX and SERDES RX of top 4 lanes and another set of PLLs for bottom 4 lanes.
When SERDES firmware is loaded, bit 7 of 0x160 register of the JESD RX page, gives the status of the SERDES PLL lock. If this bit
is 1, PLL didn’t lock and if it is 0, PLL locked. Note that the alarm has to be cleared before reading.

4. SERDES Lane Polarity:

If the polarity of the lanes are reversed, in JESD 204B the lane will link with K characters but will fail to link with data. In JESD 204C
protocol, it will never link. In this case, try inverting the corresponding lanes.

Address
Register Property Name (choose the right MSB LSB
lane)
RX_PRBS_CONFIGURAT RX_POLARITY_FLIP 0x8042 0 0
ION
NRZ_TX_TEST_PATTER TX_POLARITY_FLIP 0x80a0 0 0
N_CONFIGURATION

5. Debug Hooks for ADC JESD TX Bring Up:

a. Check the configuration on both sides.
b. In case the Receiver is seeing an
c. Check if the sync_sel is proper in JESD SUBCHIP page is programmed properly. In case of LVDS Sync, check if the syncin
polarity is also okay.

Address
Register Property Name (choose the right MSB LSB
lane)
Register 54h adc_jesd_sync_n0 0x54 2 0
Register 54h adc_jesd_sync_n1 0x54 6 4
Register 55h adc_jesd_sync_n2 0x55 2 0
Register 55h adc_jesd_sync_n3 0x55 6 4
Register 56h adc_jesd_sync_n4 0x56 2 0
Register 56h adc_jesd_sync_n5 0x56 6 4

d. Try overriding the Sync signal and see if the response is as expected. Each of these below map to 6 sync signals.
The ‘_ovr’ will override the pin value with the corresponding value of ‘_val’. Writing 0s into ‘_val’ will send K characters and
writing 1 will send K characters. To let the sync signal determine what is being sent, write 0 to ‘_ovr’.

Address
Register Property Name (choose the right MSB LSB
lane)
Register 58h adc_jesd_sync_n_sel0_spi_ovr 0x58 0 0
Register 58h adc_jesd_sync_n_sel1_spi_ovr 0x58 1 1
Register 58h adc_jesd_sync_n_sel2_spi_ovr 0x58 2 2
Register 58h adc_jesd_sync_n_sel3_spi_ovr 0x58 3 3
Register 58h adc_jesd_sync_n_sel4_spi_ovr 0x58 4 4
Register 58h adc_jesd_sync_n_sel5_spi_ovr 0x58 5 5

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Register 59h adc_jesd_sync_n_sel0_spi_val 0x59 0 0

Register 59h adc_jesd_sync_n_sel1_spi_val 0x59 1 1
Register 59h adc_jesd_sync_n_sel2_spi_val 0x59 2 2
Register 59h adc_jesd_sync_n_sel3_spi_val 0x59 3 3
Register 59h adc_jesd_sync_n_sel4_spi_val 0x59 4 4
Register 59h adc_jesd_sync_n_sel5_spi_val 0x59 5 5

6. Debug Hooks for DAC JESD RX Bring Up:

Key Registers:

Property Name Address MSB LSB Description

This is sticky bit-wise status which gets set on alignment of
COMMA_ALIGN_LOCK_FLAG 0xE8 3 0 K characters (in JESD204B) and on alignment of header bits
(in 204C).
CLEAR_COMMA_ALIGN_LOCK
0xE8 3 0 Clears the COMMA_ALIGN_LOCK_FLAG when set to 1.
_FLAG
This is sticky bit-wise status which gets set on alignment of
EMB_ALIGN_LOCK_FLAG 0xE8 7 4 Extended Multi Block(in 204C). This is invalid in 204B.
CLEAR_EMB_ALIGN_LOCK_FL
0xE8 7 4 Clears the EMB_ALIGN_LOCK_FLAG when set to 1.
AG
This is sticky bit-wise status which gets set when the JESD
VALID_DATA_OUT_FLAG 0xEF 3 0 state machine goes to Data Phase.
CLEAR_VALID_DATA_OUT_FL Clears the CLEAR_VALID_DATA_OUT_FLAG when set
0xE9 3 0 to 1.
AG
Code Group Synchronization current state (non-sticky). It is
2 bits per lane and value of 0 means state machine is waiting
JESD_CS_STATE 0xA2 7 0 for K characters and Value of 2 means it received K
characters.
Frame Alignment Synchronization current state (non-
sticky). This denotes if the 1C character sent during the K
JESD_FS_STATE 0xA4 7 0 characters to data transition (as per protocol) is received. It
is 2 bits per lane and value of 0 means 1C is not received
and 1 means, it is received.
Elastic Buffer current state (non-sticky). This denotes if the
elastic buffer is released and the state machine moved into
JESD_BUF_STATE 0xA6 7 0 data state. It is 2 bits per lane.
0-Waiting for the state machine to move into data state.
3-State Machine in data state
0x118-
ALARMS 7 0 Alarms Registers (sticky).
0x11F
0x100-
ALARMS_CLEAR 7 0 Clear for alarm registers.
0x107
To reset the top 2 lanes of DAC_JESD_AB or
LINK0_COMMA_ALIGN_RESET 0x40 0 0 DAC_JESD_CD.
To reset the bottom 2 lanes of DAC_JESD_AB or
LINK1_COMMA_ALIGN_RESET 0x40 1 1 DAC_JESD_CD.
These bits select which errors cause a sync request for lanes
[0:1]. Sync requests take priority over the error notification;
so, if sync request isn't desired; set these bits to '0'.

LINK0_SYNC_REQUEST_ENA 0x78 7 0 Each of the bits for the above-mentioned lane errors are
mapped to:
bit7 = JESDB: multiframe alignment error
bit6 = JESDB: frame alignment error

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bit5 = JESDB: link configuration error

bit4 = JESDB: elastic buffer overflow (bad RBD value)
bit3 = JESDB: elastic buffer match error. The first non-/K/
doesn’t match 0x1C.
bit2 = JESDB: code synchronization error
bit1 = JESDB: 8b/10b not-in-table code error
Bit0 = JESDB: 8b/10b disparity error

bit7 = JESDC: EoEMB alignment error

bit6 = JESDC: EoMB alignment error
bit5 = JESDC: cmd-data in crc mode not matching with spi
register bits
bit4 = JESDC: elastic buffer overflow (bad RBD value)
bit3 = JESDC: TIED to 0.
bit2 = JESDC: extended multiblock alignment error
bit1 = JESDC: sync-header invalid error ('11' or '00'
received
in expected sync header location)
Bit0 = JESDC: sync-header CRC error
These bits select which errors cause a sync request for lanes
LINK1_SYNC_REQUEST_ENA 0x79 7 0 [2:3].
-do-

Lanes and corresponding registers: Note that the lane numbers are post lane mux (towards the protocol layer).

Function Lane 0 Lane 1 Lane 2 Lane 3

Comma Align lock COMMA_ALIGN_LOCK_ COMMA_ALIGN_LOCK_ COMMA_ALIGN_LOCK_ COMMA_ALIGN_LOCK_
FLAG FLAG FLAG FLAG
0xE8[0] 0xE8[1] 0xE8[2] 0xE8[3]
Comma Align Reset LINK0_COMMA_ALIGN_ LINK0_COMMA_ALIGN LINK1_COMMA_ALIGN LINK1_COMMA_ALIGN
RESET _RESET _RESET _RESET
0x40[0] 0x40[0] 0x40[1] 0x40[1]
CS State JESD_CS_STATE JESD_CS_STATE JESD_CS_STATE JESD_CS_STATE
0xA2 [1:0] 0xA2 [3:2] 0xA2 [5:4] 0xA2 [7:6]
FS State JESD_FS_STATE JESD_FS_STATE JESD_FS_STATE JESD_FS_STATE
0xA4 [1:0] 0xA4 [3:2] 0xA4 [5:4] 0xA4 [7:6]
SerDes LOS Errors ALARMS ALARMS ALARMS ALARMS
0x119[0] 0x119[1] 0x119[2] 0x119[3]
SerDes FIFO Errors ALARMS ALARMS ALARMS ALARMS
0x119[4] 0x119[5] 0x119[6] 0x119[7]
Link Errors ALARMS ALARMS ALARMS ALARMS
0x11C[7:0] 0x11D [7:0] 0x11E [7:0] 0x11F [7:0]

Meaning of Lane Errors (204B):

As a common possibility for any of the following errors, ensure that the Eye is in good, polarities are as expected, and the lane rates of AFE
and the ASIC/FPGA are same.

Bit Meaning Issue Resolution

Number
0 8b/10b disparity error Disparity Error. Balancing the 1s- Ensure SerDes eye is good, and polarity
0s is not done. and rates of transmitter and receiver are
as expected. There is an option to change
the SerDes receiver polarity using the
register bit RX_POLARITY.
1 8b/10b not-in-table code error Received 10b character is not in -do-
the 8b/10b table.
2 code synchronization error Indicates Code Group -do-
initialization state machine Reset
caused by at least 4 invalid data

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received.
3 elastic buffer match error Didn’t receive 1C as first non-K -do-
character.
4 elastic buffer overflow Elastic buffer has overflown. Change RBD Value.
5 link configuration error ILA parameters are not matching. Ensure that all ILA parameters are as
expected and lane IDs are same for
transmitter and receiver. This is important
to check this when lane mux is employed.
6 frame alignment error Frame Alignment failed. Ensure that F is same for transmitter and
receiver.
7 multiframe alignment error Multi-Frame Alignment failed. Ensure that K is same for transmitter and
receiver.

Meaning of Lane Errors (204C):

As a common possibility for any of the following errors, ensure that the Eye is in good, polarities are as expected, and the lane rates of AFE
and the ASIC/FPGA are same.

Bit Number Meaning Issue Resolution

0 sync-header CRC error Header CRC error failed. Ensure SerDes eye is good, and polarity
and rates of transmitter and receiver are as
expected. There is an option to change the
SerDes receiver polarity using the register
bit RX_POLARITY.
1 sync-header invalid error '11' or '00' received -do-
in expected sync header
location.
2 extended multiblock alignment Failed to align to Extended Ensure that the E programmed on both the
error Multi Block Alignment. sides is same.
3 TIED to 0.
4 elastic buffer overflow (bad Elastic buffer has overflown. Change RBD Value.
RBD value)
5 cmd-data in crc mode not cmd-data in crc mode not Either mask this error or match this
matching with spi matching with spi register value to what is being transmitted.
register bits register bits (register
JESDC_CMD_DATA)
6 EoMB alignment error Multi-Block Alignment failed. Ensure that Eye is good.
7 EoEMB alignment error Extended Multi-Block Ensure that E is same for transmitter and
Alignment failed. receiver.

Debug Process for DAC JESD RX link:

a. First ensure that the SERDES eye value is good.
b. Check for the Comma Align Lock. The value of this should be True. This being true means, K28.5 characters are recognized and
consecutive comma_align_valid_thresh_tx0/1 number of K28.5 characters are recognized. If comma align lock didn’t come,
ensure that K28.5 characters are being sent, lane rate is same and the SERDES RX PLL locked (See section 2). If you want to
reinitialize the comma align logic after the change, make comma_align_reset_tx0 1 and back to 0. Note that this will come up
only for the enabled lanes (value of lane_ena).
c. Check for CS State. The CS state should be 0b10 (2 in decimal) for the enabled lanes. If the Comma Align is detected, this will
come to 2. Otherwise, it will be 0.
d. If there is CS and comma align states are not correct and there are no alarms, there are no JESD alarms, it means K character is
not yet received. Check Eye, Sync Mux and what the ASIC/FPGA is sending.
e. Check for FS State. The CS state should be 0b01 (1 in decimal) for the enabled lanes. This state machine is after the comma
align and CS state. Conditions for FS State coming up:
a. There are some errors. Check the Alarms for any errors. In that case, please clear them.
b. Sysref didn’t reach after clearing the init states. Read back the TX_DAC_SYSREF_FLAG (0xF0[4:7] value should
be 0xf) to check if the Sysref reached. Since this is sticky, ensure to clear this flag before resetting and giving the
sysref (by making CLEAR_TX_DAC_SYSREF_FLAG as 0xf and back to 0x0).
c. It is receiving K characters. FS State will move only when it receives data.
d. RX Buffer Delay (RBD) value is not enough. Change it’s value and check if it works. It should be somewhere
between 0 to K-1.

7. RBD Setting:

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8. SERDES Debug:

a. Read out the Eye Margin for each lane (post equalization) using the below C function and ensure that it is more than 800. The
read value *0.5 is the approximate serdes eye height in peak. If the SERDES Eye is poor, continue debugging as below.
getSerdesRxLaneEyeMarginValue function can be used.
b. Ensure that before the AFE is initialized, the ASIC serdes TX is configured and sending a random pattern on the lanes.
c. The STX cursor can be set using SetSerdesTxCursor function.
d. There are PRBS 9, 15, 23 and 31 available both on SERDES TX and RX.
C Functions below can be used to check do the PRBS test.
1. enableSerdesRxPrbsCheck: Enable and setting the PRBS Mode for SERDES RX.
2. getSerdesRxPrbsError: Count the number of PRBS errors.
3. sendSerdesTxPrbs: Enable and setting the PRBS Mode for SERDES TX.

Receiver test can be done by setting same pattern in ASIC/FPGA TX and then reading the receiver errors using:
getSerdesRxPrbsError function. If this value is changing, that means there are errors.

e. Complete eye diagram of the SerDes can be read using the C function getSerdesEye.

The cursors of a 3-tap FFE can be adjusted for SerDes TX pre-emphasis. The settings are the
values to be programmed to the SerDes register/C function. Higher is the main cursor value, the
larger is the swing. The pre-cursor and post-cursor equalizations are to be looked at in relative
sense. Those may not be absolute equalization provided.

Pre-Cursor Main Cursor Post-Cursor Pre- Main Post-

equalization Value equalization Cursor Setting Cursor
(dB in (dB in Setting setting
relative to relative to
post cursor) pre cursor)
0 25 0 0 0 0
0 23 0 0 1 0
0 21 0 0 2 0

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0 19 0 0 3 0
0 17 0 0 4 0
0 15 0 0 5 0
0 13 0 0 6 0
0 11 0 0 7 0
0 24 0.72 0 0 1
0 20 0.87 0 2 1
0 16 1.09 0 4 1
0 12 1.45 0 6 1
0 23 1.51 0 0 2
0 21 1.66 0 1 2
0 15 2.33 0 4 2
0 22 2.38 0 0 3
0 13 2.69 0 5 2
0 21 3.35 0 0 4
0 19 3.71 0 1 4
0 14 3.78 0 4 3
0 17 4.17 0 2 2
0 20 4.44 0 0 5
0 15 4.75 0 3 2
0 16 5.62 0 2 5
0 19 5.68 0 0 6
0 17 6.41 0 1 6
0 18 7.13 0 0 7
0.72 24 0 1 0 0
0.87 20 0 1 2 0
0.87 22 1.66 1 0 2
1.09 16 0 1 4 0
1.09 20 3.71 1 0 4
1.45 12 0 1 2 0
1.45 14 2.69 1 4 2
1.45 16 4.75 1 2 4
1.45 18 6.41 1 0 6
1.51 23 0 2 0 0
1.66 21 0 2 1 0
1.66 22 0.87 2 0 1
2.33 15 0 2 4 0

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2.33 19 4.17 2 0 4
2.38 22 0 3 0 0
2.69 18 5.62 2 0 5
2.69 13 0 2 5 0
2.69 14 1.45 2 4 1
2.69 17 4.75 2 1 4
3.35 21 0 4 0 0
3.71 19 0 4 1 0
3.71 20 1.09 4 0 1
3.78 18 4.75 3 0 4
3.78 14 0 3 4 0
4.17 17 0 4 2 0
4.17 19 2.33 4 0 2
4.44 20 0 5 0 0
4.75 15 0 4 3 0
4.75 16 1.45 4 2 1
4.75 18 3.78 4 0 3
4.75 17 2.69 4 1 2
5.62 16 0 5 2 0
5.62 18 2.69 5 0 2
5.68 19 0 6 0 0
6.41 18 1.45 6 0 1
6.41 17 0 6 1 0
7.13 18 0 7 0 0

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