IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO.

1, MARCH 2005 5

Review on High-k Dielectrics Reliability Issues

G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo

Invited Paper

Abstract—High- gate dielectrics, particularly Hf-based mate- bias temperature instability (BTI). Section IV will deal with the
rials, are likely to be implemented in CMOS advanced technolo- breakdown or characteristics of the dielectrics.
gies. One of the important challenges in integrating these materials
is to achieve lifetimes equal or better than their SiO2 counterparts.
In this paper we review the status of reliability studies of high- II. HYSTERESIS PHENOMENA
gate dielectrics and try to illustrate it with experimental results. One of the challenges for the high- integration is the
High- materials show novel reliability phenomena related to the
asymmetric gate band structure and the presence of fast and re-
threshold voltage stability during operation. In literature, the
versible charge. Reliability of high- structures is influenced both hysteresis which is a shift in is attributed to a trapping of
by the interfacial layer as well as the high- layer. One of the main charges in the pre-existing traps without creation of additional
issues is to understand these new mechanisms in order to asses the traps. We present in this section several measurement tech-
lifetime accurately and reduce them. niques which allow a better assessment of the instability.
Index Terms—Breakdown, BTI, high- dielectrics, hysteresis. The hysteresis dependences are discussed allowing argument
on trapping and detrapping mechanisms. Finally, some process
solutions are presented in order to improve the electrical sta-
I. INTRODUCTION
bility of Hf-based dielectrics.

T HE PHYSICAL limitations of the conventional silicon

dioxide as gate dielectric has reached the point where
films thickness are only a few atomic layers thick [1]. Below the
A. Methodology of Characterization
1) DC Characterization: Charge trapping has been charac-
physical thickness of 15 Å, the gate leakage current exceeds the terized until recently by quasi-static or dc measurement tech-
specifications (1 A cm ). To get around this critical problem, niques on MOS devices. Two types of measure are possible: the
high- dielectrics have been introduced as hafnium-based [2], first is a sweep of gate voltage and the drain current is sensed; the
zirconium, aluminum oxides. In fact, while keeping the EOT second is also a sweep of , but this time, it is the capacitance
constant high- dielectrics allow us to increase the physical which is measured. In both cases, a shift of characteristics (hys-
thickness of the gate stack. Hence, the gate leakage is found teresis) is observed and is related to a build-up or loss of charge
to be reduced by 2 to 3 orders of magnitude. Although a in the high- stack. Fig. 1 (a) and (b) obviously shows the ef-
large amount of effort has been invested toward high- gate fect of charge trapping on the MOSFET characteristics. Further-
dielectrics, many critical problems still remain. These problems more, the amount of hysteresis can be calculated by comparing
include defects in the material which can lead to undesired the shift between up and down traces at fixed drain current
transport through the dielectrics and trapping-induced instabil- or gate capacitance.
ities. Furthermore, the asymmetric gate band structure induces Finally, this technique has the advantage to screen quickly the
polarity effects on the leakage and reliability. All of these charge trapping effects on the characteristics of MOS device.
stack properties lead to anomalous behavior with respect to the However, given the weak ramp rate (10 V/s maximum), this
conventional SiO . static measurement technique is not adapted to characterize fast
In this paper, we will discuss the main differences in terms of transient trapping which is responsible for the hysteresis effect.
reliability between high- dielectrics and the better known sil- A time-resolved measurement technique down to microsecond
icon dioxide. We will begin by discussing the high- bulk prop- time range is necessary so as to capture the fast transient com-
erties and the defect leading to a fast reversible charge trapping ponent of the charge trapping observed in the HfO stack.
never observed until now on silicon dioxide. A second section 2) Dynamic Characterization: To qualitatively assess the
concerns a problem already met on silicon dioxide and called threshold voltage shift, alternative fast measurement techniques
are set up. Two methods have been reported in the recent
Manuscript received September 30, 2004; revised November 16, 2004. This literature: single-pulsed [3] or multiple-pulsed [4] techniques.
work was supported in part by the STmicroelectronics, LETI, IMEP. Both methods allow a better evaluation of the fast charging and
G. Ribes, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, and E.
Vincent are with STmicroelectronics, F-38926, Crolles France (e-mail:guil- discharging effects in SiO /HfO gate stacks and deal with the
[email protected]; [email protected]). impact of instability on the device performance.
J. Mitard is with CEA-LETI/D2NT-I7, 28054 Grenoble, France (e-mail: mi- a) Single-Pulsed Technique: This technique, developed
[email protected]).
G. Ghibaudo is with IMEP, Grenoble, France. for the first time by Kerber et al. [3], minimizes the effect
Digital Object Identifier 10.1109/TDMR.2005.845236 of charge trapping and detrapping on the characteristics of
1530-4388/$20.00 © 2005 IEEE
6 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 1, MARCH 2005

Fig. 2. Single-pulsed experimental setup to monitor the transient effects in

(a) high-k MOS structure.

Fig. 3. Drawing of setup used for multiple-pulsed technique.

acterize a 10 10 m device, the minimum rise and fall time

which can be used is about 2 s; we use 50 s).
b) Multiple-Pulsed Technique: This technique, proposed
(b)
by Leroux et al. [4], characterizes the trapping and detrapping
Fig. 1. (a) I –V characteristic of 1 nm SiO –4.5 nm HfO NFET. (b) C –V transients and thereby the stability of the MOS transistor by
characteristic of 1 nm SiO –4.5 nm HfO NFET.
monitoring the drain current evolution.
As shown in Fig. 3, a low noise and wide bandpass con-
nMOS device. Fig. 2 illustrates the schematic measurement verter is used to extract the and a static bias generator is
setup where the device under test is used in an inverter circuit. directly connected to the drain of the MOSFET. The advantages
During measurement, a small static bias and a trapezoidal of this system as compared to the standard one [3] are threefold,
pulse is applied to the resistor and the gate, respectively. A namely: 1) a significant reduction of the noise level; 2) use of
digital oscilloscope is used to record simultaneously the drain a constant drain voltage avoiding any drain current normaliza-
and the gate voltage and is extracted using the following tion as well as the charging current through the parasitic capac-
relationship: itances; and 3) accurate drain current transients.
Another originality of this fast measurement technique is
where (1) the multiple acquisitions. Indeed, typical transients
from microseconds up to seconds are represented in Fig. 4 using
Thus, from the gate leading edge, the up-trace of the – char- several gate voltage pulses with 2-ns leading edge. As a result,
acteristic can be rapidly constructed. As for the down trace, it is this complete set of transients in a large time-range enables
determined by the down ramp of the sweep. an accurate evaluation of the trapping kinetics. In the same
However, with this pulsed technique, we are obliged to use way, the detrapping kinetics of the fast traps can be deduced
a normalization factor since the drain voltage changes during when the gate voltage goes from high to a lower level (for
measurement. This effect is due to the resistive load which forms example: stress at 2 V and drop to 1.5 V for an NFET). Thus,
a voltage divider with the channel of MOS transistor. This nor- by sampling these and curves at specific times, an
malization to a constant is justified only when the device parametric plot can be reconstructed. As illustrated in
under test operates in its linear regime, which is not always Fig. 5, very short times for the characteristics trace can
the case during the pulse. Moreover, when the pulse’s rise or be achieved (a few microseconds and only limited by the
fall time becomes shorter, the charging current of parasitic ca- converter speed).
pacitances such as , , or is more and more pre- Further, to convert the drain current transient into a threshold
dominant and limits the speed of the measurement. Thus, it voltage shift, a reference characteristic is chosen. So, knowing
is more difficult to extract charge trapping characteristics for the parametric plot acquired at the shortest time (here
ultra-short time with this single technique (the resolution de- 5 s) and assumed without trapping, we can extract the shift
pends on the size of the tested device—for example, to char- versus time for each drain current transient. Indeed, for a given
RIBES et al.: REVIEW ON HIGH- DIELECTRICS RELIABILITY ISSUES 7

Fig. 4. Drain current degradation versus time and gate bias. Increasing drain Fig. 6. Schematic diagram of the setup for charge pumping measurement.
current decay is measured with increasing gate bias.

At the beginning, charge pumping technique has been set

up to study the interface properties between the substrate and
gate dielectric (Si-SiO ). Using this conventional technique, it
has been possible to assess the interface states density ( ) of
MOSFETs only measuring the substrate current (elements of the
theory are given in [8]). However, with the emergence of alter-
native gate dielectrics and the existence of “new” traps within
SiO /high- structure, a complementary method has been car-
ried out.
As shown in Fig. 6, two types of signals can be applied on the
gate in order to study different traps. The first, corresponding to
the classical charge pumping (CP) method, has the amplitude
of the pulse fixed while the base level is varied between two
regimes, for instance from accumulation to inversion. With this
conventional CP measurement, it has been demonstrated that it
could be possible to isolate interface state densities from bulk
traps. The second charge pumping procedure is quite different
Fig. 5. Up and down I V trace at different times compared to static curves because the base level is fixed and a variable amplitude signal
and classical dynamic measurement [1].
is applied on the gate. As mentioned for previous techniques,
this method allows, once again, to underline the contribution of
pulse, is obtained from the difference between applied gate fast traps in the instability phenomena and can help us to
voltage and corresponding gate bias taken at constant drain cur- sense the defects in the high- bulk. However, the originality
rent on the reference curve (horizontal arrow in Fig. 5). of this last experiment lies in fast measurements which can be
Finally, it is noted that all the results coming from this ex- performed at different frequencies. So, the frequency response
periment are based on two assumptions. The first concerns the of traps can be obtained and information concerning their po-
dielectric material polarization effects which, in the literature, sitions both in space and energy within the dual gate structure
were proposed as the cause for threshold voltage instability [5], can be collected. Nevertheless, much care must be taken about
[6]. However, a recent study [7] has shown that the origin of the geometric effects if a correct assessment of the defect density is
dielectric relaxation current was the electron trapping and de- desired [9].
trapping in the high- dielectric stacks. Thus, it is supposed, in
this experiment, the observed drain current variation is only due B. Parameters Influencing the Hysteresis
to a charge trapping effect. The second hypothesis is related to
the carrier’s mobility in the channel. In this section, the mobility In the previous section, fast measurement techniques al-
alteration due to a scattering of trapped charge is considered as lowing a correct assessment of the stability of high- MOS
a second-order factor which does not affect the drain current devices have been outlined. These techniques are used to
degradation much. characterize charge trapping in SiO /HfO dual stacks (details
c) Charge Pumping Technique: This technique, inten- concerning the device fabrication are in [10]) and the depen-
sively investigated throughout the past decades, has been dence of charge trapping characteristics of these films with
recently modified to characterize the charge trapping in bias, time, stack thickness, and temperature are investigated in
Hf-based stacks, in particular HfO [3]. this section.
8 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 1, MARCH 2005

1) Polarity Dependence: Through the conventional mea-

surement, – or – characteristics can be quickly measured
and are useful monitors for charge trapping. Typical results
obtained from multiple – and – traces are shown,
respectively, in Fig. 1(a) and (b).
The first important point is that the superposition of all up
traces contrary to the down traces which are increasingly shifted
(inset of Fig. 1(a)). So, this fact suggests the charge trapping is
a reversible phenomenon and a full recovery is possible.
However, it is noted that, if a starting voltage of 0 V rather than
V is used, a partial recovery of threshold voltage is obtained
[Fig. 1(b)]. Thus, applying a sufficiently negative bias, a com-
plete discharge of traps is assured. The second point is the raise
of shift when the maximum gate bias increasing. This shift
of characteristics is consistent with a build-up of negative charge
within the dual layer structure.
Fig. 7. Dynamic V shift for four samples with different gate architecture.
2) Time Dependence: Previously, the time dependence of
hysteresis phenomena has been clearly evidenced from the short
time measurement techniques (Figs. 4 and 5). Other research agreement with measurements when is about 0.32. Thus, this
groups [13], [19] have also observed that the shift due to result clearly shows the existence of a large time dependence of
the trapped charge follows logarithmic time dependence over trapping phenomena.
several decades. The authors justified it in considering that the 3) Stack Thickness Dependence: Based on the results of
time constant is a function of the distance from the dielec- previous experiments, the threshold voltage instability
tric/substrate interface. Indeed, the authors report that the trap- in SiO /HfO dual layer gate is due to the charging and dis-
ping time constant increases from the interface charging of pre-existing defects. To mention the impact of the
due to a decrease in the transport probability of carriers from gate stacks architecture on the hysteresis phenomena, results
the substrate to the location of trap. Hence, the usual kinetics of concerning four samples with different stacks are shown in
charge trapping process can be written as Fig. 7. In this case, it is noted that the magnitude of shift
mainly depends on the HfO thickness [11] whereas its bias
(2) dependence is mostly related to the interfacial oxide thickness.
Hence, these results are consistent with the fact that reducing
where is the density of trapped carrier, is the trap density, the thickness of the high- material, the number of bulk defects
and is the time constant of the trap. available to be charged by electrons diminishes. Concerning
The time constant is a function of the capture cross section the interfacial SiO layer, it has been demonstrated in other
and the gate current density . Since the transport prob- studies [4], [12] that the thickness of this layer influences the
ability of carriers changes exponentially with distance, the time mechanisms of charging and discharging of the HfO defects.
constant can be written as where In all cases, at operational conditions for future transistors
is the transport probability of carrier to reach the trap ( V), the shift remains weak ( mV) on three
of the four tested splits.
(3) 4) Temperature Dependence: To study the influence of tem-
perature on the shift, single pulsed technique has been em-
Considering a uniform distribution of traps, the can be de- ployed and the difference between the - curves generated
rived as by the up and the down swings of has been measured. As
illustrated in Fig. 8, a lowering of hysteresis is noticed when
(4) temperature increased. Up to now, this has been attributed to a
temperature-enhanced detrapping [12], [14].
Zafar et al. [13] have proposed a deferent shift versus time
C. Mechanisms and Modeling
dependence. The authors have used a model which assumes that
the traps have a continuous distribution in capture cross section As shown previously, hysteresis phenomena are influenced by
instead of single valued numerous parameters, namely, bias, time, architecture, and tem-
perature. To understand these dependences, models have been
put forward in the literature. In this section, a review of different
(5) models is proposed as well as possible mechanisms related to
charge trapping and detrapping.
This assumption about allows the introduction of a con- 1) Charge Trapping: The magnitude of instability in
stant which is a measure of the distribution width. In other SiO /HfO dual layer gate dielectrics is shown to depend
words, if , it implies that has discrete values with no dis- strongly on experimental conditions as well. To take into
tribution. However, for all curves, it has only found a good account this polarity and time dependence, a team [16] has
RIBES et al.: REVIEW ON HIGH- DIELECTRICS RELIABILITY ISSUES 9

Fig. 10. I (t) during gate pulse displays a charge trapping during pulse width
at V = 2 V and charge recovery at V = 1 V.

Fig. 8. Temperature dependence on hysteresis phenomena.

Fig. 11. Two mechanisms which may take part in the detrapping at positive
bias: back tunnelling and Poole–Frenkel.
(a) (b)
Fig. 9. Two types of model: defects are located (a) at the SiO /HfO interface filling by electron tunnelling appears to contribute to the hys-
or (b) in the bulk of high-k film.
teresis phenomena. Recently, a study [4] has demonstrated that
the trapping kinetic ( shift versus trapping time) can be mod-
initially proposed a simple model with a defect band in HfO eled using a Shockley–Read–Hall statistic.
layer located in energy between the silicon and hafnia conduc- 2) Charge Detrapping: It is commonly reported in the liter-
tion band [Fig. 9(a)]. This model has some attractive features, ature that applying a sufficient negative gate bias, a full recovery
since it explains qualitatively, for negative and positive gate of trapped charge [3] is obtained. Nevertheless, even at positive
bias, the charging and discharging of defects by tunnelling bias, it has been observed that a partial recovery of charge can
through the interfacial SiO layer. At the same time, studying take place (Fig. 10). This partial recovery can originate from two
the mobility degradation in high- MOS devices, Morioka et possible detrapping mechanisms. The first may be due to a back
al. [15] proposed to locate hysteresis traps at the HfSiO/SiO tunnelling of electron from traps to substrate and the second,
interface as shown in Fig. 9(b). Thus, two types of models are resulting from a Poole–Frenkel-like electrons conduction from
encountered in the literature. To address the critical issue of traps to traps toward the gate electrode (Fig. 11).
the location of the trapped charge (bulk of the high- film or Indeed, for the back tunnelling mechanism, a recent study
the interface high- /interface layer), Young et al. [11] have [4] has shown that the detrapping kinetic can be modeled by
characterized the hysteresis phenomena on samples with dif- a trap-like approach similar to a Shockley–Read–Hall model.
ferent HfO thicknesses. Their results suggest the trapping Based on self-consistent solving of continuity potential relation
occurs mostly in the bulk of high- material rather than only and of the time evolution trap filling probability (6), simulations
at the interface. This finding is consistent with data presented of threshold voltage shift with time account reasonably well for
in Section II-C since less trapping in physically thinner high- the obtained experimental results.
gate stacks is observed.
Considering the model with HfO bulk traps, trapping mech- (6)
anisms are finally investigated. In the previous section, we have
observed the strong transient charging effects in particular with where is capture, is emission, is electrons, and is holes.
a thin SiO bottom oxide. These transient effects are reason- Concerning the Poole–Frenkel mechanism, an experimental
ably attributed to a tunnelling of carriers through the interfacial analysis [14] of recovery gate bias dependence of the detrapping
oxide. Depending on this interface, two mechanisms for elec- characteristic time activation energy shows a field enhanced
tron trap filling can be mentioned: a filling by channel-to-defect kinetics (activation energy decreases with recovery gate bias)
tunnelling or by the capture of HfO conduction band electrons. (Fig. 12). This last result seems to be in agreement with a re-
According to Pantisano et al. [12], for a bottom oxide interme- covery assisted by Poole–Frenkel conduction. The temperature
diate thickness ( nm), trap filling is likely due to the second and gate bias dependence of detrapping characteristic time was
mechanism while for thin interfacial oxide (1 nm), a direct trap also demonstrated to follow the Poole–Frenkel theory. In this
10 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 1, MARCH 2005

A possible explanation of this result is the thermal stability

of HfSiON films (it remains amorphous even after a high tem-
perature annealing, contrary to an HfO layer). Indeed, crystal-
lization is, generally, an undesirable feature since it introduces
grains into the gate stack. Thus, this nonuniformity of high-
stack can result in additional structural defects, contributing to
the instability.
2) Metal Gate Integration: In a previous study [19], it was
also noted that a smaller hysteresis is observed on NFET using
HfO with TiN as metal gate rather than poly-Si gated HfO .
This observation, confirmed by [20], indicates the gate process
is also a contributor to the charge trapping. The reasons why the
Fig. 12. Detrapping characteristic time t shows decreasing activation energy high- dielectric is more stable with metal gate are still vague.
with respect to recovery gate voltage (1 V, 1.2 V, 1.4 V). Nevertheless, it is possible the top surface nitridation, a process
essential to a compatibility of HfO with polysilicon, leads to a
study [14], a good agreement is exhibited with experimental degradation of high- gate dielectric.
data and an extraction of the trap energy level distribution is 3) Annealing: Another way to effectively improve the
given ( eV ). hysteresis phenomena is the incorporation of deuterium during
Thus, the detrapping kinetics seem to be dominated by a com- the ALD process. In fact, the device shows smaller charge
petition between two mechanisms. A detailed study of stack de- trapping and thus a weaker shift (about by a factor of 2)
position processes (ALCVD, MOCVD, etc.) and stack archi- than ALD HfO device [21]. It is likely this treatment pas-
tecture (chemical interfacial oxide, metal gate, or poly-Si gate) sivates some dangling bonds responsible for the observed in-
could distinguish the different mechanisms. stability. As a result, the heavy water ( ) introduction into
3) Origins of Defects: The physical and chemical nature of a conventional CMOS process allows appreciably reducing the
the electron traps in the HfO /SiO structure remains unclear number of traps within the high- gate dielectric.
because the performance of high- gate dielectrics is likely to
be affected by various lattice defects. Among these defects, in- E. Conclusion on Hysteresis Phenomena
terstitial oxygen atoms and positively charged oxygen vacancies
In this section, a presentation of hysteresis phenomena as well
are suspected of playing a significant role in the observed
as the techniques to correctly quantify this effect has been made.
instability since they can trap electrons from the bottom of the
Independent of the used high- material, a few general remarks
hafnia conduction band and from silicon (results of ab initio
can be made.
calculations [22]). This result is consistent with investigations
To assess the severity of the charge trapping high- gate di-
using electron spin resonance (ESR) measurements which have
electric, special fast measurement techniques are required. Fur-
shown that species, clearly a negatively charged defect, was
thermore, electron trapping in the high- layer is the dominant
the result of electron trapping in HfO dielectric [23]. Addition-
charging mechanism at positive bias. Based on a model with
ally, chlorine impurities or water-related defects, such as OH
bulk traps and depending on the interfacial layer thickness, two
(OH-) groups, are also possible contributors to the hysteresis
types of trapping mechanism are considered: a capture of HfO
phenomena.
conduction band electrons or an electron direct tunnelling from
D. Toward Minimizing Hysteresis substrate to defect.
Concerning detrapping, it occurs when the positive bias ap-
Hysteresis in scaled high- dielectrics has been studied plied to the gate is reduced. However, a total recovery of
using both static and short time measurement techniques. The shift can be obtained with a sufficient negative gate voltage. Two
data shown previously indicates a significant amount of charge detrapping mechanisms seem to compete: a back tunnelling to
trapped especially for thick HfO stacks. Although the exact the substrate and a Poole–Frenkel mechanism.
origin of these traps still remains speculative, effective ways to Finally, the instability can be lowered by different ways.
improve the threshold voltage stability of alternative dielectrics Indeed, the scaling of high- material strongly reduces the
are explored in this section. number of defect sites to be charged. Also, the process im-
1) Hafnium Silicate Integration: Among the candidates to provements such as the use and the integration of new
replace SiO -based dielectrics, it is reported that nitrided sili- materials allow a significant reduction of charging effects. With
cate hafnium is also a promising material [18]. A publication these improvements, the problem of threshold stability during
has recently reported on the comparison of the electrical sta- device operation can be prevented from being a major issue for
bility of nMOS devices using HfO and HfSiON gate dielectrics the further integration of high- gate dielectric.
[19]. A cross-sectional TEM image of HfSiON in a self-aligned
planar CMOS transistor and an HRTEM image of the HfSiON
III. BIAS TEMPERATURE INSTABILITIES (BTI)
layer show that the film is amorphous after a full CMOS thermal
budget, including anneals at 1000 C and 1050 C. Bias temperature instability (BTI) is a degradation phenom-
This study clearly shows a hysteresis about ten times lower enon in MOS field effect transistors (MOSFETs), known since
shift for hafnium silicate compared to hafnium oxide. the late 1960s on SiO dielectrics [24], [25]. Even though the
RIBES et al.: REVIEW ON HIGH- DIELECTRICS RELIABILITY ISSUES 11

root causes of the degradation are not yet well understood, it is

now commonly admitted that under a constant gate voltage and
an elevated temperature, a build-up of charges occurs either at
the interface Si/SiO or in the oxide layer leading to the reduc-
tion of MOSFET performances. As a consequence of both the
nitridation process step and the use of surface-channel devices,
many researchers ascribed an accelerated BTI-like degradation
of pMOSFETs under negative bias and elevated temperatures,
the so-called negative bias temperature instabilities (NBTI) ef-
fect [26], [27].
Unlike SiO , the high- dielectrics such as Hf-based di-
electrics present serious instabilities for negative and positive
Fig. 13. Schema of the conventional V shift measurement methodology.
bias, after NBT and positive bias temperature (PBT) stresses. During each measurement the stress is stopped and a part of charges recover.
The trapped charges are sufficiently high to represent one of the
high- integration’s most critical showstopper. The instability
is worrying, especially in the case of nMOS PBTI. In this sec-
tion, we present a review of process optimizations found in the
literature. A new experimental methodology is also presented
in order to asses with accuracy the real degradation and allows
us to argue on possible NBTI and PBTI mechanisms.

A. Process Optimizations
Recently, authors have reported sub-15-Å EOT pMOS NBTI
exhibiting sufficient lifetime [28] but until now it is not the case
for nMOS PBTI. Fortunately, even if nMOS PBTI lifetime re-
mains strongly upsetting ( 1000 s), some important process
improvements were reported. It has been found that deuterium
annealing at 600 C improves significantly the shift during Fig. 14. PMOS and nMOS BTI stresses. The nMOS PBTI presents a total
charge recovery and the pMOS NBTI a partial one.
PBTI stress in limiting both, the generation of oxide traps and
interface traps [21]. Recently, Shanware et al. [19] has presented
that nitride hafnium silicate (HfSiON) exhibits about ten times
lower shift than HfO for identical drive current. The same
authors compare TiN and polysilicon gate with HfO dielectrics
and found a factor 5 of shift reduction during PBTI stress with
the metal gate. Such process improvements allow us to expect a
possible future integration.
Nevertheless, the physics of this mechanism is not yet un-
derstood and the reasons for the process improvements not
completely found. In order to succeed in the integration of the
hafnium-based gate dielectrics, it is indispensable to deeper
understand the trapping mechanism. Following this viewpoint,
we will propose in the following section an analysis of trapping Fig. 15. PMOS NBTI V shift measurement without stress break. The V shift
mechanism and try to find the possible origins of the traps dynamic follows a logarithmic rather than a power law.
acting in the BTI stress.
hole trapping and detrapping introduces a significant error on
B. BTI Mechanisms the shift evaluation. A neat measurement methodology re-
1) Experimental Methodology: First, it was discussed in the solving this problem has been proposed by Denais et al. [29],
first section that the high- dielectrics present fast reversible [30]. Using small gate voltage pulses during the stress, the au-
charge trapping. This recovery induces underestimation of the thors measure the shift without any interruption of the stress.
instability since the stress is stopped (Fig. 13). Hence, during Using this methodology, we obtain the degradation character-
a constant voltage stress, conventional methodology of degrada- istics displayed in Fig. 14 which help us to gain better under-
tion measurement is unable to estimate the total instability of the standing of the high- dielectrics instabilities.
MOSFET because of the stress break during measurements. In 2) PMOS NBTI Mechanisms: The pMOS NBTI stress
order to correctly characterize it in the high- , we need to mea- ( V, 125 C) presented in Fig. 14 displays a positive
sure the threshold voltage without interrupting the stress. An charge ( ) trapping dynamic. As for hole trapping on
identical issue is already being dealt with for NBTI degrada- nitride-silicon dioxide [30], a best fit is obtained for logarithmic
tion in nitride-silicon dioxide, where it was observed [29] that law (Fig. 15) and a charge recovery is observed.
12 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 1, MARCH 2005

Fig. 17. Schema summing up the mechanisms taking part in the NBTI
degradation. Hydrogen release induces interface states and oxide traps capture
Fig. 16. Interface states generation during NBTI stress measured by charge holes.
pumping techniques on TiN/HfO stack. (HfO = 30  A;SiO = 10 A).

The trapping dynamic can be well explained by the model

proposed by Shanware et al. [31]. This is explained as follows:

(7)

Hence, the shift during the stress can be well explained by a

hole tunnelling from the interfacial layer/substrate interface to
the hole traps.
After applying a zero gate bias a recovery is observed until
saturation level (Fig. 14). The recovery of corresponds Fig. 18. NMOS PBTI V shift measurement without stress break. The V shift
dynamic follows a logarithmic law.
to holes detrapping and the saturation level corresponds to
interface traps. A similar behavior was found by Huard et al.
[32] on nitride-silicon dioxide. The authors report that the
shift due to NBTI stress is composed of two traps: first, hole
traps (metastable states) which recover, and interface states
(Pb0) which are stable (no recovery). This is in agreement with
the interface states generation measured using charge pumping
measurement during NBTI stress (Fig. 16). The device used is
TiN metal gate with 30 Å HfO layer and 10 Å interfacial layer.
This is not the only common point between SiO and HfO .
Indeed Onishi et al. report that as SiON the NBTI lifetime of
HfO is deteriorated by the introduction of an surface nitri-
dation technique [28]. The observed similarities between high-
dielectrics and nitride silicon dioxide in gate injection mode Fig. 19. Temperature dynamic for nMOS PBTI V shift for the fast electron
(NBTI) are certainly due to the degradation prevalence of the trapping (open squares: V shift measured with pulsed I -V ) and the long
electron trapping (filled squares: V shift measured by the Denais method).
interfacial layer [33], [34]. In fact, this layer being very close
to amorphous silicon dioxide, we can easily understand that the
mechanisms taking part in the degradation (Fig. 17) are similar activation energy of 0.075 eV (Fig. 20). The weak value is in
to these observed in the NBTI silicon dioxide. Hence, under- agreement with the low activation energy of the direct tunnel
standing the NBTI mechanisms in SiO gate oxide undoubtedly current. It confirms the assumption of carriers direct tunneling
will help us to tackle instabilities associated with the High- di- from interface to traps toward the dielectrics [3], [4], [11], [12],
electrics [14].
3) NMOS PBTI Mechanisms: In contrast to NBTI, the Both long-term stress and the fast transient charging charac-
nMOS PBTI displayed in Fig. 2 shows an electron trapping terized by pulsed - technique correspond to electron trap-
( ). The main difference with pMOS NBTI is that the ping. Nevertheless both mechanisms present opposite tempera-
whole shift is recovered. That means that no interface traps ture behavior. Indeed we have already shown that electron trap-
are generated at this gate bias stress. As for the NBTI the PBTI ping characterized by pulsed - decreases versus tempera-
characteristics displays a logarithmic law (Fig. 18) and it can ture (Fig. 9). The opposite evolutions versus temperature mean
be well explained by the direct tunneling electron trapping. that the trapping mechanisms are different: One fast and de-
As exhibited In Fig. 19, the electron trapping increases with creasing with temperature and the others slow and slightly in-
temperature. This increase is very slight and characterized by creasing. The differences, between fast and long-term stresses,
RIBES et al.: REVIEW ON HIGH- DIELECTRICS RELIABILITY ISSUES 13

Fig. 20. Activation energy of the PBTI long-term stress V shift.

Fig. 21. Schema illustrating the trapping mechanism of U-traps for Hf-based
dielectrics. The first electron trapping is a meta-stable state and the electron can
can help us to identify the defect responsible of the PBTI insta- be emitted by Pool-Frenkle detrapping. The second electron trapping transforms
the meta-stable state into a stable one (the trapped electrons emission is strongly
bility. In the first section, it has been reported that the decrease reduced).
of - hysteresis with temperature (Pulsed - ) is explained
by the following assumption. During positive bias the shift
IV. DIELECTRIC BREAKDOWN
is equilibrium between electron trapping assisted by direct tun-
neling and electron-detrapping assisted by Pool-Frenkel mech- In the last few years, competition has driven the pace of
anism. A possible explanation of the different temperature be- decrease the oxide thickness and even leads us to change the
haviors can be found in only one defect type: the -traps [35]. nature of the gate dielectrics ( - dielectrics). Nowadays the
Very recently Kang et al. [36] have reported that hydrogen in margin in term of intrinsic lifetime, as a result of downscaling
monoclinic HfO is negative traps capturing two electrons and dielectrics changes, has disappeared. Hence, an accurate
with eV. The process could be hypothesized as fol- projection of ultrathin gate-oxide and high- dielectrics become
lows: when the electrons are injected into HfO , the neutral va- crucial in order to assess the dielectrics breakdown issue. Area
cancy will first capture one electron, which is meta-stable scaling consistent with Weibull statistics has been shown to
state. Therefore it subsequently captures the second and the de- apply in high- stacks with both metal gate and polysilicon +
fect become stable for positive bias (due to a large lattice re- nitride capping layer, demonstrating that intrinsic effects rather
laxation). Now considering that the fast traps correspond to the than manufacturing induced defects, dominate TDDB [34],
first electron trapping which is meta-stable state, a weak energy [37]. Some controversy remains in substrate injection [33], [34]
is necessary to detrap the electron ( HfO eV but for gate injection, a consistent picture has begun to emerge
[14]). The second electron trapping induces a stabilization of recently indicating that the reliability of high- dielectrics is
the meta-stable traps into a stable one and so the energy neces- dominated by the breakdown of the interfacial layer rather than
sary to release the second electron is higher ( ). the high- layer itself [33], [34]. Hence, the large experience
This increase of energy can explain a limited Pool-Frenkel de- on the silicon dioxide breakdown is a precious background to
trapping for slow traps (Fig. 21). understand the High- stack breakdown.
Hence, the equilibrium between direct tunneling electrons The goal of this section is to give an overview of the High-
trapping and Pool-Frenkel detrapping moves to a strong preva- dielectrics breakdown literature and try to link it with the silicon
lence of the direct tunneling electron trapped. By this way, the dioxide breakdown knowledge.
well known direct tunneling weak temperature activation can be
the root cause of the slight increase of the trapped charge with A. Breakdown Occurrence
higher temperature of the long-term stress. In order to asses an accurate lifetime it is crucial to detect
the first occurrence of the dielectric breakdown. The different
C. Conclusion on BTI occurrence of the wear out was already analyzed and defined in
literature. Furthermore, since some MOS digital circuits could
In this section we have seen that both mechanisms present se- remain functional after gate oxide breakdown (BD) provided
rious issues in terms of high- reliability and need to be reduced that the post-BD resistance is high enough [38], the separate
by process optimization. The principal improvement is found consideration of soft (SBD), progressive (PBD) and hard (HBD)
for hafnium silicate coupled with a metal gate and deuterium an- breakdown events is necessary to set up an adequate application-
nealing. It has been discussed that defects called -traps with specific reliability assessment methodology. The link between
energy distributed and localized in the high- layer could ex- gate oxide failure and device failure is now a major concern for
plain the very efficient electron trapping observed on high- di- the reliability community. So it is important to well identify the
electric for PBTI in long and short term stress (hysteresis). different breakdown occurrence and give an accurate definition.
In the case of NBTI the charge is rather composed by two 1) Definitions of the Different Occurrences: The SBD and
defects as in nitride-silicon dioxide. The first is a stable state the HBD are localized and randomly distributed all over the de-
called the center located at the Si-substrate/interfacial layer vice area [39]. It is now commonly admitted that SBD is not
interface and a meta-stable one: the hole traps. a HBD precursor. Both do coexist, soft and hard breakdowns
14 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 1, MARCH 2005

Fig. 22. Emission microscope measurements displaying SBD(QB) and

HBD(BD) on SiO dielectric shows that both breakdown occurrence are
spatially uncorrelated. [39].
Fig. 24. C -V characteristics measurements on two stacks displaying identical
characteristic.

Fig. 23. Schema illustrating the three different occurrences of the breakdown
(HBD, SBD, PBD).

being spatially uncorrelated (Fig. 22). The prevalence ratio that

is the fraction of each failure mode as a first failure varies with
stress conditions, oxide thickness and gate oxide area [39], [40].
When a hard or a soft breakdown occurs, the current rapidly
reaches a steady level that can last hundreds of seconds. This
state is then interrupted by another failure occurrence (that can
be either soft or hard). Finally, the magnitude of this current Fig. 25. Ig(t) characteristics under CVS stress on the stack 1 nm of interfacial
level (low for SBD and high for HBD) is attributed to a dif- layer and 2.5 nm of silicate.
ference of the size or resistance of the conduction path created
in the oxide by defect percolation [41], [42]. Regardless, these modified. Hence, it is crucial to analyze the breakdown occur-
(HBD and SBD) current levels are oxide thickness, device area rences and perform an accurate phenomenological and statis-
and stress conditions independent [39], [42]. tical study.
For oxide thinner than 25 Å, a new failure manifestation 2) Phenomenological Study: Authors have published that
appears as in increase in the noise level called progressive the three breakdown occurrences appearing in the SiO appears
breakdown PBD [43]. It has been shown that only the noise in high- dielectrics too [37], [47]. The first is a noise increase
occurrence is randomly distributed all over the device area so called the PBD and the second, a fast increase of gate current
(area scaling and Weibull statistics are followed) [43]–[45]. which can be hard or soft. Using a carrier separation analysis
As a result, only the noise detection enables to extrapolate Mizubayashi et al. [48] have reported that in gate injection for
the time to failure occurrence with respect to the device area p-MOSFET the dominant transport after the soft breakdown is
and the cumulative failure percentage. The “noisy breakdown” an electron current. They report that the defect site in the high-
prevalence ratio reaches 100% for oxide thinner than 20 Å. stack after soft breakdown are located at energies near the
After the failure occurrence, the current increases continuously conduction band edge of n+ Poly-Si. But the question remains
till the hard or soft breakdown occurs showing a direct link as to which layer triggers the breakdown.
with the hard or soft breakdown failure mode [46]. Indeed the In order to determine which layer trigger the breakdown we
PBD was reported to be the initiator of the hard or soft [46]. have reproduce these experiments on two stacks one with 0,6
To summarize, the PBD is the occurrence which announces nm of interfacial layer and 3.5 nm of hafnium silicate and the
the percolation path creation toward the layer. It is the initiator other with 1 nm of interfacial layer and 2.5 nm of silicate. As
of a SBD or a HBD. The different occurrence of these two break- it is shown by the - characteristics displayed on the Fig. 24,
down types results from the breakdown spot size or resistance. A the two stacks have the same EOT and the same .
figure illustrating the different breakdown occurrences is given We stress the two stacks of same area at the same gate voltage.
Fig. 23. In the case of high- dielectrics the presence of high- Typical observed are depicted Figs. 25 and 26. PBD is
layer implies that the origin of the PBD, SBD and HBD occur- observed on both but the PBD appears sooner on the physical
rence may be changed and then the definition may have to be thicker stack. It is probably linked to the fact that the physical
RIBES et al.: REVIEW ON HIGH- DIELECTRICS RELIABILITY ISSUES 15

Fig. 27. Time to breakdown Weibull distribution detected at PBD occurrence

displays area scaling from 2500 m to 17.5 m .

Fig. 26. Ig(t) characteristics under CVS stress on the stack 0.6 nm of
interfacial layer and 3.5 nm of silicate.

thicker stack is the one with the thinnest interfacial layer. Hence,
this result could be an indication of the correlation between
PBD and the creation of a percolation path toward the interfa-
cial layer. After the PBD occurrence the SBD appears (Figs. 25
and 26). Surprisingly, in spite of a PBD appearing sooner the
progressiveness is longer for the stack (0.6 nmIL + 3.5 nmHK). Fig. 28. Time to breakdown Weibull distribution detected at SBD occurrence
This is probably due to the higher High- thickness (3.5 nm) of displays area scaling from 2500 m to 17.5 m .
this stack. Hence, the PBD seems to be dependent of the inter-
facial layer breakdown and the SBD of the high- layer.
3) Statistical Analysis: Authors report that the PBD and
SBD have different Weibull slope and that both events are area
scalable [47], [49].
That means that the PBD and the SBD or HBD verify the
Weibull statistic:
– breakdown appears on one site among a lot,
– weakest site determines the breakdown
– breakdown occurrence of one site is independent of others
breakdown sites.
The different Weibull slope between PBD and SBD means
that they correspond with two statistical different events. So
the thickness of the broken layer and, or the defects are not Fig. 29. Weibull distribution on (1 nm SiO and 2.5 nm HK) and (0.6 nm SiO
identical. The area scaling of the two events means that the and 3.5 nm HK) stacks detected for both PBD and SBD.
PBD and the SBD are uncorrelated.
In order to enhance these observations, we have proceeded to occurrence of percolation path appearance toward the interfa-
a statistical analysis of the PBD and SBD observed on the two cial layer.
stacks described above (0.6 nmIL + 3.5 nmHK) and (1 nmIL + In contrast the soft breakdown (SBD) displays different
2.5 nmHK). First we verify that the PBD and the SBD occur- Weibull slope ( and ). This
rence are area scalable (Figs. 27 and 28). Weibull slope increase, with respect to high- layer thickness,
Plotting the distributions of the two stacks PBD and SBD is in agreement with the link between SBD and high- layer.
(Fig. 29), we observe that the two PBD distributions have the The percolation model ( ) [51]–[53] predicts that
same Weibull slope. This result is in agreement with the constant the cross section of the defect is equal to 1.9 nm (Fig. 30). By
Weibull slope measured on SiO layer thinner than 1.2 nm. In- this way, below a thickness of 1.9 nm, the Weibull slope of the
deed the defect cross section in the SiO is supposed to be close SBD should remain constant as SiO below 1.2 nm. Hence, a
to this thickness [50]. In all likelihood the PBD is the electrical ratio close to 1.5 between the silicate defect cross section and the
16 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 1, MARCH 2005

Fig. 31. EOT extracted from NCSU versus physical oxide thickness of high-k
dielectrics exhibits a consistent interfacial layer thickness with the targeted one.
Fig. 30. Plot of high-k thickness versus Weibull slope detected at SBD
displays a 1.9 nm defect cross section.

SiO one is found. So the Weibull slope of the High- at same

thickness must decrease by the same ratio. This is in agreement
with low Weibull slope observed in substrate injection [33] with
respect to those measured on SiO layers.

B. Breakdown Mechanisms
1) Gate Injection:
a) Thick High- Stack: Further indications that the inter-
facial layer plays a strong role in the breakdown in gate injection
have already been published [33], [34]. It has been found that,
for stack with high- layer thicker than 8 nm and carrier energy
higher than 5 eV, the for /SiO stacks are equivalent Fig. 32. Charge to breakdown versus gate voltage for thin SiO (from 14 Å to
with those for SiO with a thickness identical to the interfacial 11 Å) and (30 ÅHK+10 ÅIL) stack.
layer [33]. This result is in agreement with the similarity be-
tween NBTI SiO degradation and NBTI high- stack degra-
dation discussed in the previous section. Moreover, the Weibull
slope of the time to breakdown exhibits a good correlation with
SiO interfacial-layer thickness. The authors explain this mech-
anism by the Anode Hole Injection model, considering that hot
tunnelling electron can give its energy to an electron-hole pair
and release a hot hole which is then able to generate a defect by
inelastic heat. The hydrogen release model could also explain
the breakdown of the SiO interfacial layer. Indeed the process
is similar to the Anode Hole Injection apart from the fact that
the excited element is not the electron-hole pair but interfacial
Si-H bond.
b) Thin High- Stack:
Experimental Investigations: Below 5 eV electron energy,
the interpretation of the results is more complicated. The Fig. 33. Charge to breakdown versus Vox measured on two stacks with 25 Å
HfO and 30 Å HfO thickness and same interfacial layer thickness (1 nm).
Fig. 31 displays the equivalent oxide thickness extracted from A shift of around 3 decades between the two stacks is observed which is in
measurement (NCSU) for two MOS transistors one with agreement with the MVHR prediction.
30 Å high- thickness and 10 Å interfacial layer, the other 20 Å
and 10 Å interfacial layer. As is shown, the EOT’s measured thickness one (10 Å). That means that probably the High- layer
confirm the targeted thicknesses. Knowing the stack layers’ plays a role in the defect generation probability ( ) or in the
thicknesses, we can see that contrary to thick high- stressed critical defect density ( ).
at carrier energy higher than 5 eV [33], the is no longer However, we have to note that the Weibull slopes remain iden-
scalable with interfacial SiO layer thickness. Seen either as tical close to for the two stacks, which is in agreement
electron energy, the gate voltage (Fig. 32), or as the voltage with the breakdown of the interfacial layer. The Weibull slope
drop toward the dielectric, (Fig. 33), the nonscalability is being directly linked to the [53], this result seems to show
verified in the both cases. that the is independent of the high- layer thickness.
As it is shown on Fig. 31, the high- stack charge to break- The temperature behavior of the breakdown can help us to
down is higher than the corresponding SiO interfacial layer determine the first layer broken. On Fig. 34, we present results
RIBES et al.: REVIEW ON HIGH- DIELECTRICS RELIABILITY ISSUES 17

Finally, other degradation mechanism models are favored by

different groups. For reliability projection, the voltage depen-
dence of the failure time must be clarified. Both charge injec-
tion model (HR, MVHR, AHI) predicts a rapidly increasing life
time for high- stacks, as gate voltage is reduced, due to the cur-
rent limiting effect of the high- layer. Recent measurements of
the voltage acceleration with decreasing gate voltage ([58]) are
consistent with a charge injection model. The thermo-chemical
model has also been applied to explain high- breakdown phe-
nomena ([59]), but this model results in more conservative and
pessimistic reliability projection. Experimental investigation in
order to determine which degradation mode gives the appro-
Fig. 34. Time to breakdown at 50% displays similar activation energy on three priate voltage extrapolation appears an important challenge for
different dielectrics (HfO with metal gate, HfSiO with poly gate and SiO with the future. All these results seem to show that answers can be
poly gate).
found in the good understanding of the SiO breakdown.
2) Substrate Injection: Because of the good agreement be-
on HfO with metal gate and HfSiO with polysilicon gate. The tween high- stack and interfacial SiO layer thickness charge
times to breakdown display similar activation energy for both to breakdown, [33] and [60] have first reported that even in
stacks ( eV eV). Furthermore, the activa- substrate injection, the stack breakdown is driven by the inter-
tion energies are in agreement with those measured on SiO . facial oxide layer. This proposition was supported by the low
The temperature behavior similarity between these completely Weibull slope observed with respect to the high- layer thick-
different stacks is an additional indication about the interfacial ness. Nevertheless, study and especially degradation analysis
layer breakdown. This way the high- thickness dependence of such as SILC [33] or trap density in the high- layer charac-
the Weibull slope and the temperature behavior are in agreement terize by charge pumping [60] are in agreement and seems to
with a critical defect density ( ) independent with the high- show that as for in substrate injection the layer which
thickness. drives the stack breakdown is the high- dielectrics. Since it
Hence, the shift between both stacks seems to originate has been proved that the trapped charge ( ) [60] or SILC
rather from a high- thickness dependence of the defect gener- [33] remains constant at breakdown for different stress condi-
ation probability ( ). tions, the authors report that electron trapping into the high-
Discussions: It has been reported that, below 5 eV, only dielectrics would be responsible of the gate stack breakdown.
one electron is not sufficient to break the Si-H bond by direct Hence, the dielectric breakdown and the PBTI could be directly
excitation [54]. Hence, below this carrier energy, the defect correlated. The breakdown assisted by electron trapping in the
generation probability ( ) depends on gate current density high- layer seems to be coherent with degradation analyses but
( ) [55]. This dependence is linked to the the low Weibull slope ( ) with respect to the high- layer thick-
multivibrational excitation of the Si-H bond [54], [56]. It was ness remains surprising. An explanation could be found with a
reported that cooperation between electrons is needed in order percolation model [51]–[53]
to break the bond [54], [56]. This process allows electrons
to further excite the bond until an energy relaxation time. (8)
Hence, following this process, the defect generation probability
depends on gate current density. with a defect cross section ( ) higher for HfO than for SiO
This theory was verified on SiO MOS transistors with SHE resulting from the different nature of the two dielectrics: cova-
and SHH stresses which enable to decorrelate all the stress pa- lent and amorphous for SiO and ionic crystal or poly-crystal
rameters (electric field, gate current, electron energy) [57]. With for HfO .
this model, we explain all CVS stress polarities for pMOS and Further investigations are required in order to understand the
nMOS SiO dielectrics [55]. Hence, according to the multi- high- dielectrics breakdown complexity. Notably, all degrada-
vibrational hydrogen release model (MVHR), below 5 eV the tion mechanisms analysis like interface states, oxide traps gen-
should decrease with decreasing high- layer thickness. eration and temperature behavior appears to be important issues
That way, the current dependence of the defect generation which must be understand before trying to explain the creation
probability predicted by the MVHR model may be an expla- of the breakdown path in the high- dielectrics. Comprehen-
nation. Indeed, considering that the electron energy, in accumu- sion of these mechanisms is crucial in order to make extrapo-
lation regime, is the oxide voltage drop toward the stack ( ) lation models trustworthy and to accurately assess the high-
[55] and that the defect generation probability follows a power dielectrics reliability in the substrate injection regime
law of the gate current density ( ) as predicted by the
MVHR model, the shift between the two stacks depicted C. Conclusion on Dielectrics Breakdown
on Fig. 33 is explained and quantified with accuracy. The degradation, the breakdown occurrence phenomenolog-
Hence, these results confirm that in spite of the nonscal- ical and statistical analyses are found to be consistent.
ability, below 5 eV, with respect to the interfacial layer thick- In gate injection, the first stack wear-out is the interfacial
ness, the breakdown remains driven by the interfacial layer. layer breakdown. It is characterized by a progressive breakdown
18 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 1, MARCH 2005

(PBD). According to the MVHR model the charge to breakdown [14] G. Ribes et al., “Characterization of Vt instability in hafnium based di-
of this event is dependent of the gate current and so to the high- electrics by pulse gate voltage techniques,” in Proc. ESSDERC, 2004,
pp. 89–92.
layer thickness. The gate current increases, until second break- [15] A. Morioka et al., “High mobility MISFET with low trapped charge in
down which can be soft (SBD) or hard (HBD) depending of the HfSiO films,” in Symp. VLSI Technology Dig. Tech. Papers, 2003, pp.
spot size. Both breakdowns were identified as the breakdown of 165–166.
[16] A. Kerber et al., “Origin of the threshold voltage instability in
the high- layer. This event is area scalable and then indepen- SiO /HfO dual layer gate dielectrics,” IEEE Electron Device Lett.,
dent of the interfacial layer breakdown. So probably, it appears vol. 24, no. 2, pp. 87–89, Feb. 2003.
at others breakdown site than the interfacial layer breakdown [17] T. H. Hou et al., “Direct determination of interface and bulk traps in
scaled HfO dielectrics using charge pumping method,” in Proc. Int.
path. Hence, in order to assess the lifetime of the whole high-
Reliability Physics Symp., 2004, pp. 581–582.
stack an accurate detection must be performed, especially to de- [18] M. R. Visokay et al., “Application of HfSiON as a gate dielectric mate-
termine the circuit lifetime. rial,” Appl. Phys. Lett., vol. 80, p. 3183, 2002.
In the case of substrate injection further research is required. [19] A. Shanware et al., “Characterization and comparison of the charge trap-
ping in HfSiON and HfO gate dielectrics,” in IEDM Tech. Dig., 2003,
In all likelihood, the layer responsible of the breakdown event pp. 939–942.
seems to be the high- layer. Accurate statistical analyses, with [20] E. P. Gusev et al., “Charge trapping in aggressively scaled metal
thickness layers discriminations, remain crucial in order to un- gate/high-K stacks,” in IEDM Tech. Dig., 2004, pp. 403–405.
derstand the breakdown in this stress regime.
[21] H.-H. Tseng et al., “ALD HfO using heavy water ( DO ) for improved
MOSFET stability,” in IEDM Tech. Dig., 2003, pp. 411–414.
[22] A. S. Foster, F. L. Gejo, A. L. Shluger, and R. M. Nieminen, “Vacancy
V. CONCLUSION and interstitial defects in hafnia,” Phys. Rev. B, vol. 65, p. 174117, 2002.
[23] A. Y. Kang, P. M. Lenahan, and J. F. Conley, “Electron spin resonance
The reliability of high- gate dielectric stacks is influenced observation of trapped electron centers in atomic-layer-deposited
hafnium oxide on Si,” Appl. Physics Lett., p. 8316, Oct. 2003.
both by the interfacial layer as well as the high- layer. TDDB [24] B. E. Deal, M. Sklar, A. S. Grove, and E. H. Snow, J. Electrochem. Soc.,
results indicate these mechanisms do not pose fundamental lim- vol. 114, p. 266, 1967.
itations but need to be understood deeply. Charge trapping, how- [25] D. Frohman-Bentchkowsky, “A fully decoded 2048-bit electrically pro-
grammable FAMOS read-only memory,” IEEE J. Solid-State Circuits,
ever, presents a serious reliability challenge, primarily as a result vol. 6, no. 5, pp. 301–306, Oct. 1971.
of instabilities. Data is available to show that required levels [26] K. Uwasawa, T. Yamamoto, and T. Mogami, “A new degradation mode
of long-term stability of both nMOS and pMOS devices can of scaled p+ polysilicon gate pMOSFETs induced by bias temperature
be attained, but will require careful process optimizations. How- (BT) instability,” in IEDM Tech. Dig., 1995, pp. 871–874.
[27] G. La Rosa et al., “NBTI-channel hot carrier effects in PMOSFETs in
ever as the basic understanding of hot carrier aging mechanisms advanced CMOS technologies,” in Proc. Int. Reliability Physics Symp.,
and plasma-induced damage (PID) begins to be published, a 1997, p. 282.
deeper understanding is urgently required. It is clear that this [28] K. Onishi et al., IEDM Tech. Dig., 2001, p. 659.
[29] M. Denais et al., “New methodologies of NBTI characterization elimi-
there is a link between the major performance and reliability nating recovery effects,” in Proc. ESSDERC, 2004, p. 265.
factors, so that reliability improvement can be expected to re- [30] M. Denais et al., “On-the-fly characterization of NBTI in ultrathin gate-
sult in continued process improvements. oxide PMOSFETs,” in IEDM Tech. Dig., 2004, pp. 109–111.
[31] A. Shanware et al., “Evaluation of positive bias stress stability in Hf-
SiON gate dielectrics,” in Proc. Int. Reliability Physics Symp., 2003, pp.
REFERENCES 208–213.
[32] V. Huard, F. Monsieur, G. Ribes, and S. Bruyère, “Evidence for hy-
[1] D. A. Buchanan, IBM J. Res. Dev., vol. 43, p. 245, 1999.
drogen-related defects during NBTI stress in p-MOSFETs,” in Proc. Int.
[2] E. P. Gusev, “The physics and chemistry of SiO and the Si-SiO inter-
Reliability Physics Symp., 2003, pp. 178–182.
face,” Electrochem. Soc., pp. 477–485, 2000.
[3] A. Kerber et al., “Characterization of VT instability in SiO /HfO gate
[33] T. Kauerauf et al., “Toward understanding degradation and breakdown
of SiO /high-k stacks,” in IEDM Tech. Dig., 2002, pp. 521–524.
stacks dielectrics,” in Proc. Int. Reliability Physics Symp., 2003, pp.
41–45.
[34] X. Garros et al., “Reliability assessment of ultrathin HFO oxides with
[4] C. Leroux et al., “Characterization and modeling of hysteresis phe- TiN gate and polysilicon-N+ gate,” in Proc. Int. Reliability Physics
nomena in high-k dielectrics,” in IEDM Tech. Dig., 2004, pp. 737–740. Symp., 2004, pp. 176–180.
[5] H. Reisinger et al., “A comparative study of dielectric relaxation of [35] P. W. Anderson et al., Phys. Rev. Lett., vol. 34, p. 953, 1975.
losses in alternative dielectrics,” in IEDM Tech. Dig., 2001, pp. 740–743. [36] A. Y. Kang et al., “An electron spin resonance study of interface defects
[6] J. R. Jameson et al., “Problems with metal-oxide high-k dielectrics due in atomic layer deposited hafnium oxide on Si,,” Appl. Phys. Lett., vol.
to 1/t dielectric relaxation current in amorphous materials,” in IEDM 84, p. 3894, 2004.
Tech. Dig., 2003, pp. 431–434. [37] S. J. Lee, C. H. Lee, C. H. Choi, and D. L. Kwong, “Time-dependent
[7] Z. Xu et al., “A study of relaxation current in high-k dielectric stacks,” dielectric breakdown in poly-Si CVD Hf02 gate stack,” in Proc. Int. Re-
IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 402–408, Mar. 2004. liability Physics Symp., 2002, pp. 402–414.
[8] G. Groeseneken et al., “A reliable approach to charge pumping measure- [38] B. Kaczer et al., “Impact of MOSFET oxide breakdown on digital circuit
ments in MOS transistors,” IEEE Trans. Electron Devices, vol. ED-31, operation and reliability,” in IEDM Tech. Dig., 2000, pp. 553–556.
pp. 42–53, 1984. [39] S. Bruyère, E. Vincent, and G. Ghibaudo, “Quasibreakdown in ultra-
[9] G. Van den Bosch, G. Groeseneken, and H. E. Maes, “On the geometric thin SiO films: Occurrence characterization and reliability assessment
component of charge-pumping current in MOSFETs,” IEEE Electron methodology,” in Proc. Int. Reliability Physics Symp., 2000, pp. 48–54.
Device Lett., vol. 14 , no. 3, pp. 107–109, Mar. 1993. [40] J. Suñé, E. Y. Wu, D. Jiménez, R. P. Vollertsen, and E. Miranda, “Under-
[10] B. Guillaumot et al., IEDM Tech. Dig., 2002, pp. 355–358. standing soft and hard breakdown statistics, prevalence ratios and energy
[11] C. D. Young et al., “Charge trapping in MOCVD Hafnium-based gate dissipation during breakdownrunaway,” in IEDM Tech. Dig., 2001, pp.
dielectric stack structures and its impact on device performance ,” in 611–614.
Integrated Reliability Workshop Final Report, 2003, pp. 28–35. [41] M. A. Alam, B. E. Weir, P. J. Silverman, Y. Ma, and D. Hwang, “The
[12] L. Pantisano et al., “Dynamics of threshold voltage instability in stacked statistical distribution of percolation resistance as a probe into the me-
high-k dielectrics: Role of the interfacial oxide,” in Symp. VLSI Tech- chanics of ultrathin oxide breakdown,” in IEDM Tech. Dig., 2000, p. 529.
nology Dig. Tech. Papers, 2003, pp. 163–164. [42] E. Miranda and J. Suñé, “Analytic modeling ofleakage current through
[13] S. Zafar, A. Callegari, E. Gusev, and M. V. Fischetti, “Charge trapping in multiple breakdown paths in SiO films,” in Proc. Int. Reliability Physics
high-k gate dielectric stacks,” in IEDM Tech. Dig., 2002, pp. 517–520. Symp., 2001, pp. 367–379.
RIBES et al.: REVIEW ON HIGH- DIELECTRICS RELIABILITY ISSUES 19

[43] F. Monsieur, E. Vincent, G. Pananakakis, and G. Ghibaudo, “Wear-out, [54] P. Avouris et al., “Breaking individual chemical bonds via STM-induced
breakdown occurrence and failure detection in 18–25 Å ultrathin ox- excitations,” Surf. Sci., vol. 363, pp. 368–377, 1996.
ides,” Microelectron. Reliab., vol. 41, pp. 1035–1039, 2001. [55] G. Ribes et al., “Evidence and modeling current dependence of defect
[44] J. S. Suehle, E. M. Vogel, B. Wang, and J. B. Bernstein, “Temperature generation probability an dits impact on charge to breakdown,” in
dependence of soft breakdown and wear-out in sub-3 nm SiO films,” WODIM Proc., 2004, pp. 40–42.
in Proc. Int. Reliability Physics Symp., 2000, pp. 33–39. [56] K. Stokbro et al., “First-principles theory of inelastic currents in a scan-
[45] F. Monsieur, E. Vincent, D. Roy, S. Bruyere, J. C. Vildeuil, G. ning tunneling microscope,” Phys. Rev. B, vol. 58, no. 12, 1998.
Pananakakis, and G. Ghibaudo, “A thorough investigation of pro- [57] G. Ribes et al., “Breakdown mechanisms in ultrathin oxides: Impact of
gressive breakdown in ultrathin oxides. Physical understanding and carrier energy and current through substrate hot carrier stress study,” in
application for industrial reliability assessment,” in Proc. Int. Reliability Proc. INFOS, 2003, pp. 40–41.
Physics Symp., 2002, pp. 45–54. [58] Y. Harada et al., “Specific structural factors influencing on reliability of
[46] F. Monsieur, E. Vincent, G. Ribes, V. Huard, S. Bruyere, G. Pananakakis, CVD-HfO ,” in Symp. VLSI Technology Dig. Tech. Papers, 2002, pp.
and G. Ghibaudo, “Evidence for defect-generation-driven wear-out of 26–27.
breakdown conduction path in ultra thin oxides,” in Proc. Int. Reliability [59] J. W. McPherson et al., “Trends in the ultimate breakdown strength of
Physics Symp., 2003, pp. 424–431. high dielectric-constant materials,” IEEE Trans. Electron Devices, vol.
[47] Y. H. Kim et al., “Hard and soft-breakdown characteristics of ultrathin 50, no. 8, pp. 1771–1778, Aug. 2003.
HfO under dynamic and constant voltage stress,” in IEDM Tech. Dig., [60] R. Degraeve, A. Kerber, P. Roussel, E. Cartier, T. Kauerauf, L. Pantisano,
2002, pp. 629–632. and G. Groeseneken, “Effect of bulk trap density on HfO reliability and
[48] W. Mizubayashi et al., “Carrier separation analysis for clarifying yield,” in IEDM Tech. Dig., 2003, pp. 3851–3854.
leakage mechanism in unstressed and stressed HfAlO/SiO stack
dielectrics layers,” in Proc. Int. Reliability Physics Symp., 2004, pp.
188–193.
[49] M. Koyama et al., “Degradation mechanism of HfSiON gate insulator
and effect of nitrogen composition on the statistical distribution of the G. Ribes received the engineer degree in electrical engineering from the Institut
breakdown,” in IEDM Tech. Dig., 2003, pp. 849–852. Supérieur d’Electronique et du Numérique (ISEN), Toulon, France, in 2002. He
[50] J. Sune, “New physics-based analytic approach to the thin-oxide received the M.S.E.E degree in micro- and nanoelectronics from Provence Uni-
breakdown statistics,” IEEE Electron Devices Lett., vol. 22, no. 6, pp. versity, Marseille, France. He is now pursuing the Ph.D degree in the Reliability
296–298, Jun. 2001. group of the Central R&D, STMicroelectronics, Crolles, France.
[51] R. Degraeve et al., “New insights in the relation between electron trap He works in the areas of ultrathin silicon dioxide and high-k dielectrics layers
generation and the statistical properties of oxide breakdown,” IEEE reliability in collaboration with IMEP.
Trans. Electron Devices, vol. 45, no. 4, pp. 904–911, Apr. 1998.
[52] J. H. Stathis, “Percolation models for gate oxide breakdown,” J. Appl.
Phys., vol. 86, pp. 5757–5766, 1999.
[53] D. J. DiMaria and J. H. Stathis, “Explanation for the oxide thickness
dependence of breakdown characteristics of metal-oxide-semiconductor Photographs and biographies of the co-authors not available at the time of pub-
structures,” Appl. Phys. Lett., vol. 70, pp. 2708–2710, 1997. lication.