210246: (DIGITAL ELECTRONICS LAB) EXPT NO.

: STUDY OF LOGIC GATES NOT GATE:

LAB MANUAL DATE : The NOT gate is called an inverter. The output is high when the input is low.
The output is low when the input is high.
SYLLABUS AIM:
To study about logic gates and verify their truth tables.
LIST OF EXPERIMENTS NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both
APPARATUS REQUIRED:
1. Study of logic gates. inputs are low and any one of the input is low .The output is low level when both inputs
SL No. COMPONENT SPECIFICATION QTY
2. Realize Full Adder and Subtractor using a) Basic Gates and b) 1. AND GATE IC 7408 1 are high.

Universal Gates. 2. OR GATE IC 7432 1

3. Design and implement Code converters-Binary to Gray and BCD to 3. NOT GATE IC 7404 1 NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs
4. NAND GATE 2 I/P IC 7400 1
Excess-3
5. NOR GATE IC 7402 1 are low. The output is low when one or both inputs are high.
4. Design of n-bit Carry Save Adder (CSA) and Carry Propagation Adder (CPA).
6. X-OR GATE IC 7486 1
Design and Realization of BCD Adder using 4-bit Binary Adder (IC 7483)
7. NAND GATE 3 I/P IC 7410 1 X-OR GATE:
5. Realization of Boolean Expression for suitable combination logic using MUX The output is high when any one of the inputs is high. The output is low when
8. IC TRAINER KIT - 1
74151 / DMUX 74154. 9. PATCH CORD - 14 both the inputs are low and both the inputs are high.
6. Design & Implement Parity Generator using EX-OR.
7. Flip Flop Conversion: Design and Realization THEORY: PROCEDURE:
(i) Connections are given as per circuit diagram.
8. Design of Ripple Counter using suitable Flip Flops
Circuit that takes the logical decision and the process are called logic gates. Each (ii) Logical inputs are given as per circuit diagram.
a. Realization of 3 bit Up/Down Counter using MS JK Flip Flop / D Flip Flop
gate has one or more input and only one output. (iii) Observe the output and verify the truth table.
b. Realization of Mod -N counter using ( 7490 and 74193 )
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
9. Design and Realization of Ring Counter and Johnson Ring counter.
universal gates. Basic gates form these gates.
10. Design and implement Sequence generator using JK flip-flop.
11. Design and simulation of - Full adder , Flip flop, MUX using VHDL (Any 2) Use AND GATE:
The AND gate performs a logical multiplication commonly known as AND
different modeling styles
function. The output is high when both the inputs are high. The output is low level when
12. Design and simulation of - Full adder , Flip flop, MUX using VHDL (Any 2) Use
any one of the inputs is low.
different modeling styles
13. Study of Shift Registers ( SISO,SIPO, PISO,PIPO )
OR GATE:
14. Study of Microcontroller 8051 : Features, Architecture and Programming Model The OR gate performs a logical addition commonly known as OR function. The
output is high when any one of the inputs is high. The output is low level when both the
inputs are low.

1 2 3

AND GATE: NOT GATE: 2-INPUT NAND GATE:

SYMBOL: PIN DIAGRAM: SYMBOL: PIN DIAGRAM: SYMBOL: PIN DIAGRAM:

X-OR GATE :
OR GATE: 3-INPUT NAND GATE :
SYMBOL : PIN DIAGRAM :

4 5 6
NOR GATE: EXPT NO. : DESIGN OF ADDER AND SUBTRACTOR HALF SUBTRACTOR:
DATE :
The half subtractor is constructed using X-OR and AND Gate. The half subtractor
AIM: has two input and two outputs. The outputs are difference and borrow. The difference can
To design and construct half adder, full adder, half subtractor and full subtractor be applied using X-OR Gate, borrow output can be implemented using an AND Gate and
circuits and verify the truth table using logic gates. an inverter.

APPARATUS REQUIRED: FULL SUBTRACTOR:

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full
Sl.No. COMPONENT SPECIFICATION QTY.
1. AND GATE IC 7408 1 subtractor the logic circuit should have three inputs and two outputs. The two half
2. X-OR GATE IC 7486 1 subtractor put together gives a full subtractor .The first half subtractor will be C and A B.
3. NOT GATE IC 7404 1 The output will be difference output of full subtractor. The expression AB assembles the
4. OR GATE IC 7432 1
borrow output of the half subtractor and the second term is the inverted difference output
3. IC TRAINER KIT - 1
of first X-OR.
4. PATCH CORDS - 23

LOGIC DIAGRAM:
THEORY:
HALF ADDER
HALF ADDER:

A half adder has two inputs for the two bits to be added and two outputs one from
the sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is
RESULT: called as a carry signal from the addition of the less significant bits sum from the X-OR
Gate the carry out from the AND gate.

FULL ADDER:
TRUTH TABLE:
A full adder is a combinational circuit that forms the arithmetic sum of input; it
A B CARRY SUM
consists of three inputs and two outputs. A full adder is useful to add three bits at a time
but a half adder cannot do so. In full adder sum output will be taken from X-OR Gate, 0 0 0 0
0 1 0 1
carry output will be taken from OR Gate. 1 0 0 1
1 1 1 0

7 8 9

K-Map for SUM: K-Map for CARRY: TRUTH TABLE:

K-Map for SUM:
A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

K-Map for DIFFERENCE:

SUM = A’B’C + A’BC’ + ABC’ + ABC
SUM = A’B + AB’ CARRY = AB
K-Map for CARRY:

LOGIC DIAGRAM:

FULL ADDER
DIFFERENCE = A’B + AB’
FULL ADDER USING TWO HALF ADDER
K-Map for BORROW:

CARRY = AB + BC + AC

LOGIC DIAGRAM:

HALF SUBTRACTOR
TRUTH TABLE: BORROW = A’B

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

10 11 12
LOGIC DIAGRAM: K-Map for Difference: EXPT NO. : DESIGN AND IMPLEMENTATION OF CODE CONVERTOR
FULL SUBTRACTOR DATE :
AIM :

To design and implement 4-bit

(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

Difference = A’B’C + A’BC’ + AB’C’ + ABC APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
K-Map for Borrow: 3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:
THEORY:
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion circuit
must be inserted between the two systems if each uses different codes for same
Borrow = A’B + BC + A’C information. Thus, code converter is a circuit that makes the two systems compatible
even though each uses different binary code.
PROCEEDURE:
(i) Connections are given as per circuit diagram. The bit combination assigned to binary code to gray code. Since each code uses
four bits to represent a decimal digit. There are four inputs and four outputs. Gray code is
TRUTH TABLE: (ii) Logical inputs are given as per circuit diagram.
A B C BORROW DIFFERENCE a non-weighted code.
(iii) Observe the output and verify the truth table. The input variable are designated as B3, B2, B1, B0 and the output variables are
0 0 0 0 0
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
0 0 1 1 1
0 1 0 1 1 Boolean functions are obtained from K-Map for each output variable.
0 1 1 1 0 RESULT:
A code converter is a circuit that makes the two systems compatible even though
1 0 0 0 1
1 0 1 0 0 each uses a different binary code. To convert from binary code to Excess-3 code, the
1 1 0 0 0
input lines must supply the bit combination of elements as specified by code and the
1 1 1 1 1
output lines generate the corresponding bit combination of code. Each one of the four

13 14 15

maps represents one of the four outputs of the circuit as a function of the four input K-Map for G2: TRUTH TABLE:
| Binary input | Gray code output |
variables.
A two-level logic diagram may be obtained directly from the Boolean expressions B3 B2 B1 B0 G3 G2 G1 G0
derived by the maps. These are various other possibilities for a logic diagram that
0 0 0 0 0 0 0 0
implements this circuit. Now the OR gate whose output is C+D has been used to 0 0 0 1 0 0 0 1
implement partially each of three outputs. 0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
LOGIC DIAGRAM: 0 1 0 1 0 1 1 1
BINARY TO GRAY CODE CONVERTOR 0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
K-Map for G1: 1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-Map for G3:

K-Map for G0:

G3 = B 3

16 17 18
LOGIC DIAGRAM: K-Map for B2: K-Map for B0:
GRAY CODE TO BINARY CONVERTOR

K-Map for B1:

TRUTH TABLE:

| Gray Code | Binary Code |

K-Map for B3: G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
B3 = G3
1 0 0 0 1 1 1 1

19 20 21

LOGIC DIAGRAM: K-Map for E2: K-Map for E0:

BCD TO EXCESS-3 CONVERTOR

TRUTH TABLE:
K-Map for E3: K-Map for E1:
| BCD input | Excess – 3 output |
B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
E3 = B3 + B2 (B0 + B1)

22 23 24
LOGIC DIAGRAM: K-Map for B: K-Map for D:

EXCESS-3 TO BCD CONVERTOR

K-Map for C: TRUTH TABLE:

| Excess – 3 Input | BCD Output |

K-Map for A:
B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

A = X1 X2 + X3 X4 X1

25 26 27

PROCEDURE: EXPT NO. : DESIGN OF 4-BIT ADDER AND SUBTRACTOR 4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together with an
(i) Connections were given as per circuit diagram. DATE :
input carry from a previous stage. Since each input digit does not exceed 9, the output
(ii) Logical inputs were given as per truth table AIM : sum cannot be greater than 19, the 1 in the sum being an input carry. The output of two
To design and implement 4-bit adder and subtractor using IC 7483.
(iii) Observe the logical output and verify with the truth tables. decimal digits must be represented in BCD and should appear in the form listed in the

APPARATUS REQUIRED: columns.

ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2
Sl.No. COMPONENT SPECIFICATION QTY. decimal digits, together with the input carry, are first added in the top 4 bit adder to
1. IC IC 7483 1
produce the binary sum.
2. EX-OR GATE IC 7486 1
RESULT: 3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
PIN DIAGRAM FOR IC 7483:
4. PATCH CORDS - 40

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output
carry from each full adder connected to the input carry of next full adder in chain. The
augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from
right to left, with subscript 0 denoting the least significant bits. The carries are connected
in chain through the full adder. The input carry to the adder is C0 and it ripples through
the full adder to the output carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed
between each data input ‘B’ and the corresponding input of full adder. The input carry C 0
must be equal to 1 when performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit
is adder circuit. When M=1, it becomes subtractor.

28 29 30
LOGIC DIAGRAM: LOGIC DIAGRAM: LOGIC DIAGRAM:
4-BIT BINARY ADDER 4-BIT BINARY SUBTRACTOR 4-BIT BINARY ADDER/SUBTRACTOR

31 32 33

TRUTH TABLE: LOGIC DIAGRAM: TRUTH TABLE:

BCD ADDER
Input Data A Input Data B Addition Subtraction BCD SUM CARRY
S4 S3 S2 S1 C
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1 0 0 0 0 0
0 0 0 1 0
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 0 0 1 0 0
0 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0
0 1 0 1 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 0
0 1 1 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0
1 0 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1 1 0 1 0 1
1 0 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 0 0 1
1 1 0 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 0 1
1 1 1 1 1

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

K MAP (iii) Observe the logical output and verify with the truth tables.

RESULT:

Y = S4 (S3 + S2)

34 35 36
EXPT NO.: 16 BIT ODD/EVEN PARITY CHECKER /GENERATOR TRUTH TABLE OF PARITY CHECKER: Simplification:

DATE :
INPUTS OUTPUT
AIM: P B2 B1 B0 PEO
To design and implement 16 bit odd/even parity checker generator using IC 0 0 0 0 1
0 0 0 1 0
74180.
0 0 1 0 0
0 0 1 1 1
APPARATUS REQUIRED: 0 1 0 0 0
0 1 0 1 1
Sl.No. COMPONENT SPECIFICATION QTY. 0 1 1 0 1
1. NOT GATE IC 7404 1 0 1 1 1 0
1. IC 74180 2 1 0 0 0 0
2. IC TRAINER KIT - 1 1 0 0 1 1
3. PATCH CORDS - 30 1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
THEORY: 1 1 0 1 0
1 1 1 0 0
A parity bit is used for detecting errors during transmission of binary information. 1 1 1 1 1
A parity bit is an extra bit included with a binary message to make the number is either
even or odd. The message including the parity bit is transmitted and then checked at the
receiver ends for errors. An error is detected if the checked parity bit doesn’t correspond K-MAP FOR PEO:
to the one transmitted. The circuit that generates the parity bit in the transmitter is called
a ‘parity generator’ and the circuit that checks the parity in the receiver is called a ‘parity
B1B0
checker’.
PB2
In even parity, the added parity bit will make the total number is even amount. In
00 01 11 10
odd parity, the added parity bit will make the total number is odd amount. The parity
00
checker circuit checks for possible errors in the transmission. If the information is passed 1 0 1 0
in even parity, then the bits required must have an even number of 1’s. An error occur 01
during transmission, if the received bits have an odd number of 1’s indicating that one bit 0 1 0 1
11
has changed in value during transmission.
1 0 1 0
10
0 1 0 1

37 38 39

PROCEDURE: EXPT NO. : DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:
DEMULTIPLEXER
(i) Connections are given as per circuit diagram. DATE :

(ii) Logical inputs are given as per circuit diagram. AIM:

To design and implement multiplexer and demultiplexer using logic gates and
(iii) Observe the output and verify the truth table. study of IC 74150 and IC 74154.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 8:1 MUX IC IC 74151 2
2. 8:1 MUX IC IC 74154 1
3. 1 FUNCTION TABLE:
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

RESULT: S1 S0 INPUTS Y
THEORY:
MULTIPLEXER: 0 0 D0 → D0 S1’ S0’
Multiplexer means transmitting a large number of information units over a 0 1 D1 → D1 S1’ S0
smaller number of channels or lines. A digital multiplexer is a combinational circuit that
1 0 D2 → D2 S1 S0’
selects binary information from one of many input lines and directs it to a single output
1 1 D3 → D3 S1 S0
line. The selection of a particular input line is controlled by a set of selection lines.
n
Normally there are 2 input line and n selection lines whose bit combination determine
Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0
which input is selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this
reason, the demultiplexer is also known as a data distributor. Decoder can also be used as
demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates.
The data select lines enable only one gate at a time and the data on the data input line will
pass through the selected gate to the associated data output line.

40 41 42
LOGIC DIAGRAM FOR MULTIPLEXER: BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER: LOGIC DIAGRAM FOR DEMULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

TRUTH TABLE:

S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

43 44 45

TRUTH TABLE: PIN DIAGRAM FOR IC 74154: EXPT NO. : CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE
COUNTER AND MOD 10/MOD 12 RIPPLE COUNTER
DATE :
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3 AIM:
To design and verify 4 bit ripple counter mod 10/ mod 12 ripple counter.
0 0 0 0 0 0 0
0 0 1 1 0 0 0
APPARATUS REQUIRED:
0 1 0 0 0 0 0
0 1 1 0 1 0 0 Sl.No. COMPONENT SPECIFICATION QTY.
1 0 0 0 0 0 0 1. JK FLIP FLOP IC 7476 2
1 0 1 0 0 1 0 2. NAND GATE IC 7400 1
3. IC TRAINER KIT - 1
1 1 0 0 0 0 0
4. PATCH CORDS - 30
1 1 1 0 0 0 1

PIN DIAGRAM FOR IC 74150: THEORY:

A counter is a register capable of counting number of clock pulse arriving at its
clock input. Counter represents the number of clock pulses arrived. A specified sequence
of states appears as counter output. This is the main difference between a register and a

PROCEDURE: counter. There are two types of counter, synchronous and asynchronous. In synchronous
(i) Connections are given as per circuit diagram. common clock is given to all flip flop and in asynchronous first flip flop is clocked by
external pulse and then each successive flip flop is clocked by Q or Q output of previous
(ii) Logical inputs are given as per circuit diagram.
stage. A soon the clock of second stage is triggered by output of first stage. Because of
(iii) Observe the output and verify the truth table.
inherent propagation delay time all flip flops are not activated at same time which results
RESULT: in asynchronous operation.

46 47 48
PIN DIAGRAM FOR IC 7476: TRUTH TABLE: LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
TRUTH TABLE:
10 0 1 0 1
11 1 1 0 1
CLK QA QB QC QD
12 0 0 1 1
0 0 0 0 0
LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER: 13 1 0 1 1
1 1 0 0 0
14 0 1 1 1
2 0 1 0 0
15 1 1 1 1
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0

49 50 51

LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER: PROCEDURE: EXPT NO. : DESIGN AND IMPLEMENTATION OF 3 BIT
SYNCHRONOUS UP/DOWN COUNTER
(i) Connections are given as per circuit diagram. DATE :

(ii) Logical inputs are given as per circuit diagram. AIM : To design and implement 3 bit synchronous up/down counter.

(iii) Observe the output and verify the truth table.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
TRUTH TABLE:
7. PATCH CORDS - 35
CLK QA QB QC QD
0 0 0 0 0 RESULT:
1 1 0 0 0 THEORY:
2 0 1 0 0
A counter is a register capable of counting number of clock pulse arriving at its
3 1 1 0 0
clock input. Counter represents the number of clock pulses arrived. An up/down counter
4 0 0 1 0
is one that is capable of progressing in increasing order or decreasing order through a
5 1 0 1 0
certain sequence. An up/down counter is also called bidirectional counter. Usually
6 0 1 1 0
up/down operation of the counter is controlled by up/down signal. When this signal is
7 1 1 1 0
high counter goes through up sequence and when up/down signal is low counter follows
8 0 0 0 1 reverse sequence.
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 0 0

52 53 54
K- MAP CHARACTERISTICS TABLE: TRUTH TABLE:
Q Qt+1 J K Input Present State Next State A B C
Up/Down Q A QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC
0 0 0 X
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
1 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
1 1 X 0 0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
LOGIC DIAGRAM:
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
STATE DIAGRAM:

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

55 56 57

EXPT NO. : DESIGN AND IMPLEMENTATION OF SHIFT REGISTER PIN DIAGRAM: TRUTH TABLE:

DATE :
Serial in Serial out
AIM : CLK
To design and implement
(i) Serial in serial out 1 1 0
(ii) Serial in parallel out 2 0 0
(iii) Parallel in serial out
3 0 0
(iv) Parallel in parallel out
4 1 1
APPARATUS REQUIRED: 5 X 0
6 X 0
Sl.No. COMPONENT SPECIFICATION QTY.
7 X 1
1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1 LOGIC DIAGRAM:
4. PATCH CORDS - 35 SERIAL IN PARALLEL OUT:
LOGIC DIAGRAM:

THEORY:

A register is capable of shifting its binary information in one or both directions is SERIAL IN SERIAL OUT:

known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops
receive common clock pulses which causes the shift in the output of the flip flop. The
simplest possible shift register is one that uses only flip flop. The output of a given flip
flop is connected to the input of next flip flop of the register. Each clock pulse shifts the
content of register one bit position to right. TRUTH TABLE:
OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

58 59 60
LOGIC DIAGRAM: TRUTH TABLE:
PARALLEL IN SERIAL OUT: DATA INPUT OUTPUT
CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

TRUTH TABLE:
(iii) Observe the output and verify the truth table.
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
RESULT:
3 0 0 0 0 1

LOGIC DIAGRAM:

PARALLEL IN PARALLEL OUT:

61 62