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https://doi.org/10.7567/JJAP.57.07MG01

Survey of critical failure events in on-chip interconnect by fault tree analysis

Shinji Yokogawa1* and Kyousuke Kunii2
1
The Info-Powered Energy System Research Center, The University of Electro-Communications, Chofu, Tokyo 182-8585, Japan
2
Graduate School of Informatics and Engineering, The University of Electro-Communications, Chofu, Tokyo 182-8585, Japan
*E-mail: [email protected]
Received November 20, 2017; revised January 10, 2018; accepted January 23, 2018; published online May 21, 2018

In this paper, a framework based on reliability physics is proposed for adopting fault tree analysis (FTA) to the on-chip interconnect system of a
semiconductor. By integrating expert knowledge and experience regarding the possibilities of failure on basic events, critical issues of on-chip
interconnect reliability will be evaluated by FTA. In particular, FTA is used to identify the minimal cut sets with high risk priority. Critical events
affecting the on-chip interconnect reliability are identified and discussed from the viewpoint of long-term reliability assessment. The moisture impact
is evaluated as an external event. © 2018 The Japan Society of Applied Physics

physics [e.g., Refs. 8–28], and the establishment of a frame-

1. Introduction work to summarize reported phenomena resulting from these
Because of the large-scale integration of semiconductor studies will be expected, which will facilitate the adaptation of
devices, their interconnect systems have become well FTA to the prevention of semiconductor failures.
structured and increased in number. However, the complex- In this study, the structural characteristics of on-chip
ities of these systems have made predictions difficult for interconnect reliability of the semiconductor are investigated
the occurrence of faults in design, production, and reliability. and summarized, using FTA and the proposed reliability
Presently, many previous works on several failure physics are physics framework. A framework based on reliability physics
reported. On the basis of enormous knowledge accumulated, is proposed to apply knowledge from previous studies related
each issue will be evaluated to ensure the reliability of a to on-chip interconnect reliability. By FTA and using the
product. In this regard, critical issues corresponding to framework, critical events on failure will be discussed from
product applications should all be identified in an appropriate the viewpoints of minimal cut sets. Moreover, a policy to
order of priority. Therefore, risk assessment of each device ensure the long-term reliability will be discussed on the basis
should be carried out in a structured and consistent manner. of FTA results. This paper is an extension of our previous
Fault tree analysis (FTA) is a powerful technique for conference abstract,29) and the framework and its evaluation
identifying the root causes of an undesired state in system are described in detail in this paper.
failures. FTA has been developed to assess a missile control
system in 1961.1) Since then, it is widely used for identifying 2. FT framework for on-chip interconnect reliability
the root causes of an undesired event within a system 2.1 FTA theory and evaluation
failure.1–7) By constructing a tree of subevents, which spreads Fault tree (FT) is a deductive, structured methodology that
into intermediate and basic events, contributions of the basic is used to identify the potential causes of a top event. In FT,
events to the top event can be logically analyzed. These the relationships between events are described using gate
basic events are understood as the root causes. Furthermore, symbols, as shown in Fig. 1. The constructed FT is useful for
the fault tree (FT) illustrates layered, logical relationships investigating the risks of the top event both qualitatively and
between events for the scenario of the system failure. FTA quantitatively.
involves two processes that can provide two pieces of Qualitatively, an expression is derived for the top event
information that can prevent the failure of systems with through the combinations of primary and basic events and
complicated structures. The first is the identification of the using Boolean algebra. The qualitative evaluation of logic
minimal cut sets, which are the distinct combinations of trees by the accounting of cut or path sets is conceptually
component failures that cause system failure, and the second simple. The OR gate logic in a tree represents the union set of
is the calculation of system reliability. input events. Similarly, the AND gate logic represents the
Despite its merits, FTA is not so widely used in the product set of input events. For example, an OR gate with
semiconductor industry compared with failure mode and three inputs (events A, B, and C) and one output (top event T )
effects analysis (FMEA). Because FMEA uses component can be represented by its equivalent Boolean equation, T =
failure to identify system risks, it is well adapted to A + B + C (Fig. 2). The AND gate with three inputs (events
qualitative predictions and risk assessments of undesired A, B, and C) and one output (top event T ) would be T =
events within the semiconductor manufacturing process. A · B · C (Fig. 3). Determination of cut sets using the above
A process flowchart will be an appropriate framework for expressions is possible through top-down, bottom-up, or
FMEA that defines components of the manufacturing process modularization algorithms.
of the semiconductor. By the simulating a fault or a Quantitatively, the probability of the top event can be
fluctuation of the components in the Process FMEA, it can calculated from the primary and basic events regarding the
evaluate impacts and risks of the failure of semiconductors. minimal cut sets. The quantitative evaluation of logic trees
However, there is no framework available with which can determine the probability of occurrence of the top event.
FTA can be used to investigate the failure events of semi- For the OR gate as shown in Fig. 2, the probability of the
conductors. Many studies have been carried out in reliability top event is Pr(T ) = Pr(A + B + C). If A, B, and C are
07MG01-1 © 2018 The Japan Society of Applied Physics
Jpn. J. Appl. Phys. 57, 07MG01 (2018) S. Yokogawa and K. Kunii

Symbol Name Contents Symbol Name Contents

An event that
Output occurs if a
occurs because
Inter- single event input
of one or more
to produce output
mediate antecedent Inhibit only if a
event causes acting
conditioning event
through logic
input is met.
gates.

A basic event External An event that is

Basic requiring no
further
event normally expected
event to occur.
development. (House)

㸦Output㸧 㸦Output㸧

Output occurs if Output occurs if at

AND gate all of the input OR gate least one of the
events occur. input events occurs.

㸦Input㸧 㸦Input㸧

Fig. 1. Symbols for FTA nodes.

T TE

A B C G
A
q1 q2 q3

Fig. 2. OR gate.

B C

T
Fig. 4. Schematic example of FT diagram.

A B C
q1 q2 q3 2.2 FTA framework for on-chip interconnect reliability
In FTA, it is important to describe flows of events obviously
Fig. 3. AND gate. connected to the top events. Generally, the flows are defined
on the basis of relationships of elemental functions in a
system. For on-chip interconnects in a semiconductor, the
independent, the probability of the top event, Pr(TE), will be functions of elements, e.g., lines, vias, or dielectrics, are quite
determined by the probability of ith events, qi, as simple, such as electrical conduction and insulation,
compared with those in complicated machinery for which
PrðTEÞ ¼ 1  ð1  q1 Þð1  q2 Þð1  q3 Þ: ð1Þ
FTA is widely applied. Therefore, the general FTA procedure
Similarly, for the AND gate as shown in Fig. 3, the that is focused on the functions will tend to keep the
probability of the top event is Pr(T ) = Pr(A · B · C). The interconnect FT simple. However, there are various previous
probability of the top event, Pr(TE), will be determined by works about the causes of failure based on detailed physics in
the probability of ith events, qi, as semiconductor interconnects, and general FTA is unsuitable
for covering them systematically. Therefore, a valid and
PrðTEÞ ¼ q1  q2  q3 : ð2Þ
common framework for utilizing information acquired from
A cut set is a set of units that interrupt all possible previous works will be required to construct the FT for on-
connections between the input and output nodes. Hence, a chip interconnect reliability.
cut set means a condition of failure occurring in the FT. In In this study, we propose the use of a specific FT structure
particular, a minimal cut set is the smallest set of units needed to describe the reliability physics (Fig. 5). To investigate
to guarantee an interruption of flow. In practice, minimal cut an undesired event, the event is analyzed from its visible
sets show a combination of unit events that cause a system observation to its root causes by tracking its physical or
to fail. For example, in Fig. 4, the minimal cut sets are the chemical mechanisms. The relationships between the top
simultaneous occurrence of the basic events A and B ðA; BÞ event and the root causes are classified on the basis of the
and the simultaneous occurrence of basic events A and C following frameworks in series:
ðA; CÞ. Therefore, the FT for on-chip interconnect reliability Failure mode: Failure phenomena are classified (e.g.,
will provide the critical events that will contribute to failure disconnection, short circuit, breakage, friction, or
from the minimal cut sets. deterioration).30) In this study, failure modes are defined
07MG01-2 © 2018 The Japan Society of Applied Physics
Jpn. J. Appl. Phys. 57, 07MG01 (2018) S. Yokogawa and K. Kunii

Manuscript collection
Top
event
(Failure) Digitalize abstracts
First layer
(Failure mode)
Retrieve interconnect related abstracts
e.g., Void growth
Second layer
(Failure mechanism)
e.g., EM/SIV Manually extract failure mode,
Create co-occurrence network
failure mechanism, and
Third layer and beyond for failure modes from abstracts
potential hazards from papers
(Potential hazard)
e.g., Jmax error/Over Tjmax/Internal stress/etc.
Check co-occurrence of failure
Create basic FT on the
mechanisms and potential
Fig. 5. Structural image of the FT for on-chip interconnect reliability proposed framework
failures on the network
constructed using reliability physics.

Adding the co-occurrence failure

to be associated with observable function degradation or
mechanisms and their potential
function loss of the interconnect system. hazards to the related failure mode
Failure mechanism: Physical, chemical, or other processes
leading to a failure are identified.30) In this study,
Qualitative evaluation of FTA
physical and chemical reaction processes are identified to
induce the failure mode. Hence, the satisfaction of failure
Fig. 6. Procedure for constructing the on-chip interconnect reliability FT
mechanism conditions under use conditions does not in this paper.
always correspond to the occurrence of a failure mode.
Potential hazard: A source that can have a damaging effect
or a condition, factor, or scenario that can have a Table I. FT statistics for the on-chip interconnect reliability.
damaging effect is identified.31) In this study, a potential Item Number
hazard is defined as an acceleration factor and an Failure mode 14
activation condition of each failure mechanism. Failure mechanism 29
Specifically, a practical failure will become obvious as a
Total node 489
failure mode that is induced by a failure mechanism with
Total gate 147
stresses in a potential hazard. Most reliability papers define
AND gate 25
this framework to perform predictions and acceleration tests.
OR gate 111
For example, in an electromigration (EM) study, the failure
Inhibit gate 11
mode is defined as a resistance increase due to voiding. The
Intermediate event 146
failure mechanism is electromigration. The potential hazards
Basic event 177
are temperature, current density stress, and other acceleration
Minimal cut set 319
factors and activation conditions. As another example, in a
stress-induced voiding (SIV) study, the failure mode is
defined as a resistance increase due to voiding. The failure
mechanism is stress-induced voiding. The potential hazards technique was used to choose 351 papers that use the word
are temperature-driven stress, metal shape, grain size, and “interconnect” in their abstract from a total of 4263 papers
other acceleration factors and activation conditions. These (“Retrieve interconnect related abstracts” in Fig. 6). To
elements can be similarly extracted from previously reported maintain objectivity, no paper selection was performed.
papers. Hence, papers on both aluminum and copper interconnects
were investigated evenly. The FT is developed with reference
3. Analysis method to the text mining database and the co-occurrence of words.
The interconnect FT is developed on the basis of the For text mining, we used Text Mining Studio 6.0.5.
proposed “failure mode-failure mechanism-potential hazard”
framework. The evaluation of the FT has two obviously 4. Results and discussion
different aspects as previously stated. A logical or qualitative 4.1 s-MCS
evaluation of the logic tree cut sets will be discussed in this The scale of the FT developed from the chosen 351 papers by
study. A probabilistic or quantitative evaluation is beyond the procedure shown in Fig. 6 is indicated in Table I, which
the scope of this study because the probabilities of event shows that the FT covers 14 failure modes and 29 failure
occurrence vary among previously reported papers. For FTA, mechanisms. In total, 147 gates are constructed from OR,
we used FTAStudio Standard 2.0.1710.1323. AND, and inhibit gates. The number of OR gates is larger
The procedure to construct the FT is shown in Fig. 6. In than that of AND gates, which suggests that the character-
this study, published papers about the on-chip interconnect istics of redundancy are weak in the semiconductor structure.
reliability in IEEE International Reliability Physics Sympo- Furthermore, there are 319 minimal cut sets in the reliability
sium (IRPS: 1962–2017) were investigated as previous FT, which are derived by solutions of the Boolean equations
studies (“Manuscript collection” in Fig. 6). A text mining of the FT. Because performing countermeasures for all
07MG01-3 © 2018 The Japan Society of Applied Physics
Jpn. J. Appl. Phys. 57, 07MG01 (2018) S. Yokogawa and K. Kunii

Table II. Top 23 minimal cut sets of the on-chip interconnect reliability FT. Single events are directly linked to the top event.
No. Type of event Hazard event Failure mechanism Failure mode
Lc error
1 Basic event
(Lc: critical line length)
Jmax error EM
2 Basic event
(Jmax: maximum current)
3 Conditional event Edge seal break
Wmax error
4 Basic event
(Wmax: maximum line width)
5 Basic event Metal thickness error
Void growth
6 Basic event Deposition error
7 Basic event Anneal temp. error
CTE of metal SIV
8 Basic event
(CTE: coefficient of thermal expansion)
9 Basic event CTE of dielectrics
10 Basic event Grain size error
11 Basic event Anneal temp. error
12 Conditional event Edge seal break
13 Basic event Inappropriate metal layout
14 Basic event Inappropriate chip size
Metal slide
Inappropriate PKG size
15 Basic event
(PKG: package)
Wire break
16 Basic event Mold absorption
Delamination
17 Basic event Rapid temp. change
18 Basic event Inappropriate metal layout Stepwise
19 Basic event Flatten error break
Time-dependent
20 Conditional event Edge seal break
dielectric breakdown
21 Conditional event Edge seal break Leakage
Time-zero dielectric
EOS
22 Conditional event breakdown
(EOS: electrical over stress)
23 Conditional event Edge seal break Low-k absorption k-value change

minimal cut sets is not realistic, a risk priority should be As shown in the branches of the FT in Fig. 7, the many
evaluated. s-MCS lead to the void growth. The basic events of s-MCS are
In particular, a minimal cut set consisting of a single event generally prevented by the design rule of the circuit. However,
(s-MCS) suggests a high risk qualitatively. If the probabilities the “Edge seal break” as the conditional event is difficult to
of these s-MCSs are not negligible, they should be prevented control by the rules because it is a stochastically generated
as the first priority qualitatively. As shown in Table II, only event. To ensure the on-chip interconnect reliability, additions
23 of the s-MCSs, which were identified by the number of of some redundancy to the conditional event will be efficient if
elements in MCS, were found among 319 MCSs in the FT. there is difficulty in the exclusion of the event. For example,
An “Edge seal break” as a conditional event is common for moisture as the external event in Fig. 7 will be the potential
three failure modes and five failure mechanisms. The edge hazard under the “Edge seal break” condition. It suggests that
seal32) is a moisture barrier formed as a metal stack positioned some countermeasures to achieve moisture tolerance will be
along the outer peripheral edges of the active area of the required for highly reliable interconnects.
chip. It is reported that moisture affects metal and dielectric 4.2 Corrosion-related minimal cut sets
reliability.23,33–37) The edge seal plays a crucial role in Moreover, the conditional event of “Edge seal break” will
preventing moisture under use conditions. Therefore, the contribute to metal corrosion, as shown in Table III. This
“Edge seal break” will be a common cause of each failure suggests that the “Edge seal break” activates “metal
mechanism, and “Edge seal break” will be considered to have corrosion” as the failure mode. The partial FT for metal
a particularly higher priority than other events. corrosion is shown in Fig. 9. Each corrosion mechanism is
Figure 7 shows the partial FT for the first intermediate activated subject to moisture supply as indicated by the AND
event, namely, “void growth” as the failure mode. In a and Inhibit gates to “Edge seal break”. It means that “Edge
semiconductor, EM and SIV are widely known as failure seal break” is considered as the common cause of the metal
mechanisms, and the result of co-occurrence network analy- corrosion in the FT. The priority of improvement of a
sis shown in Fig. 8 supports this common knowledge. The common cause is generally high and a secure method will be
co-occurrence words that correspond to void suggest the required. In particular, because it is difficult to suppress the
potential hazards and are reflected in FT. Therefore, the FT is external event, some redundancy for the conditional event
structured by the two failure mechanisms. will be effective in long-term use.
07MG01-4 © 2018 The Japan Society of Applied Physics
Jpn. J. Appl. Phys. 57, 07MG01 (2018) S. Yokogawa and K. Kunii

First layer Second layer Third layer Fourth layer Fifth layer Sixth layer
(Failure mode) (Failure mechanism) (Hazard 1) (Hazard 2) (Hazard 3) (Hazard 4)

To top event

: s-MCS

Fig. 7. (Color online) Excerpt of the on-chip interconnect reliability FT. “Void growth” as the failure mode is indicated as the first intermediate event.

Fig. 8. (Color online) Co-occurrence network for “void” in IRPS abstracts.

Developing redundancy within an interconnect structure

will be required to withstand some unavoidable stresses such 5. Conclusions
as moisture and to establish a reliability assessment policy for The FTA structure for investigating the on-chip interconnect
the long-term use of semiconductors. The proposed FTA can reliability of semiconductors was proposed on the basis of
support investigations of unavoidable hazards. the reliability physics framework. The interconnect failure,
07MG01-5 © 2018 The Japan Society of Applied Physics
Jpn. J. Appl. Phys. 57, 07MG01 (2018) S. Yokogawa and K. Kunii

Table III. Minimal cut sets related to the failure mode of “metal corrosion”.
No. Type of event Hazard event Failure mechanism Failure mode
Basic event Lack of cleaning
Basic event Contamination
1 Basic event High temperature Chemical corrosion
External event Moisture
Conditional event Edge seal break
Basic event Electric field bias
Basic event Parallel metal layout
2 Basic event High temperature Electrochemical corrosion Metal corrosion
External event Moisture
Conditional event Edge seal break
Basic event Dissimilar metal joint
Basic event Large δ ionization tendency
3 Basic event High temperature Galvanic corrosion
External event Moisture
Conditional event Edge seal break

Fig. 9. (Color online) Excerpt of the “Metal corrosion” FT.

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