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EEF 205E Introduction To Logic Design Homework 4

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EEF 205E Introduction To Logic Design Homework 4

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Nicat Mahmudov
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© © All Rights Reserved
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Student Name: Instructor: Mustafa Altun

Student ID:

EEF 205E Introduction to Logic Design


Homework 4
Deadline: 6/01/2024 (before 23:30)
Grading: 1) 30%, 2) 30%, 3) 40%

1) The logic diagram of JK flip-flop is given in Figure 1.


a) Write the output Boolean functions for the outputs.
b) Draw the timing diagram of the circuit on Figure 2; ignore gate delays.

Figure 1

CP

Figure 2
2) Consider a sequential circuit shown in Figure 3.
a) How many states does the circuit have?
b) Obtain the state transition table.
c) Obtain the state diagram.
d) Is it Mealy or Moore?

Figure 3
3) Consider a Mealy machine based sequential circuit having one input X and one output
Z. The output Z will be 0 except the input sequence 1101 are the last 4 inputs received
on X. The circuit has 7 states defined as follows:

Input State a) Obtain the state table and perform state reduction.
Sequence After state reduction how many states remain?
……...00 A b) Draw the state diagram having the reduced states.
……...11 B c) Start designing the circuit with assigning 0’s and 1’s to
the reduced states. Your design will be based on D-flip-
…….001 C
flops. Derive minimal sum-of-products (SOP) Boolean
…….010 D
expressions for the next states and the output in terms of
…….110 E
the input and the current states.
…...0101 F
d) Draw the circuit using minimal number of D-flip-flops,
…...1101 G and AND, OR, and NOT gates.

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