Proceedings of the Sixth International Conference on Computing Methodologies and Communication (ICCMC 2022)

IEEE Xplore Part Number: CFP22K25-ART; ISBN: 978-1-6654-1028-1

Design and Study of 90nm CMOS Common

Source 2.4GHz Low Noise Amplifier
2022 6th International Conference on Computing Methodologies and Communication (ICCMC) | 978-1-6654-1028-1/22/$31.00 ©2022 IEEE | DOI: 10.1109/ICCMC53470.2022.9753775

Sam chrisvin D Dharshini M Senthilkumar S N

Department of ECE Department of ECE Department of ECE
Kumaraguru College of Technology, Kumaraguru College of Technology, Kumaraguru College of Technology,
Coimbatore,India Coimbatore,India Coimbatore,India
[email protected] [email protected] [email protected]

Jaspar Vinitha Sundari T

Department of ECE
Kumaraguru College of Technology,
Coimbatore,India
[email protected]

Abstract— A systematic and meticulous study on different optimum gain and low noise figure with the low supply
topologies of Common source Low noise amplifiers for low voltage of 1.2 V, thus minimizing the consumption of
power applications is designed at 2.4 GHz for low power power.
wireless applications. The design and analysis of Common
Yet another LNA with ultra-low NF of 0.58 dB,
S ource Inductive load (Type 1), Inductive S ource Degeneration
(Type 2) and Cascode Common S ource LNA (Type 3) is optimum S21 of 11 dB and very high linearity is recorded in
accomplished using cadence virtuoso analog and digital design [4]. The high linearity is achieved via thumb rule to get
environment in 90 nm cmos technology. The proposed LNA high gain for the same current bias, every time overdrive
implemented using a common source with inductive voltage declines. The optimized gain and sustained
degeneration achieves a gain of 25.1783dB. Also, Input linearity is achieved in the recorded work whereas the
Reflection Coefficient (S 11) of -1.826dB, Output Reflection conventional techniques for achieving the same are usually
Coefficient (S 22) of 2.17861dB, Reverse Gain Coefficient (S 12) of accompanied by increased current, thereby high power
-31.6649dB, and noise figure of 1.382dB is recorded which consumption [1]. The Type 2 topology is always known for
emphasizes the efficiency of proposed LNA in efficiently
its good input matching, with minimal trade- off between
managing the trade off between noise figure and gain. Also, the
other two topologies recorded a gain of 5 to 8 dB and noise S21 and linearity which is balanced by the current at the
figure of 3 dB. Further optimization with respect to these biasing network in [3] by using the intermodulation
topologies was accompanied by the degrading performance in distortion (IMD) technique.
terms of low gain and high noise figure. A 5.0 GHz single stage common source low noise
amplifier offering 25.3 dB gain, 2.2 dB noise figure for
Keywords—Low power applications, CMOS, 90nm, Common frequency range of 5 GHz to 6 GHz is obtained for wireless
Source Inductive load, Inductive Source Degeneration and local area network (WLAN) applications employing active
Cascode Common Source LNA. device biasing [6] to achieve such improvised gain. The
Type 2 topology is analyzed mathematically with respect to
I. INT RODUCT ION
space exploration via Hspice to acquire the possible design
LNA, an irreplaceable component in any communication points that give less power, high gain, less NF, and less S11
system finds its applications in mobile phones, GPS at a 2 GHz frequency. [2]
receivers, wireless LAN (WiFi), satellite communications,
biomedical applications like neural, ECG, EEG application The circuit level optimization is always accompanied by
and so on. A low noise amplifier is a device which can limitations in terms of transistor maximum efficiency,
amplify weak signals. The LNA is a significant component
fabrication limits, more area because of passive inductance
of the radio receiver circuit. Being employed at the front
end, its sole purpose is to minimize unnecessary additional and so on. This has demanded deviation towards alternative
noise and to improve the strength of the original signal. device and alternative area effective active inductances.
When any communication system encounters weak sources, Last decade has recorded many numbers of low noise
its performance relies on the S21 and noise introduced by the amplifiers implemented using various emerging nano
first stage. Therefore, choosing the right LNA is important devices like TFET, FINFET, CNT and so on, which paves
for proper working of the communication system. An the way for optimizing the circuit performance metrics like
efficient LNA design can be assured with the help of Gain and noise figure with respect to gm of the device
performance parameters such as Noise Figure, power employed. Such type of common source LNA using
consumption, Gain, figure of merit, and linearity. MOSFET, GaAs HEMT [5] and TFET [15] is designed and
compared specifically for Gain and Noise figure. One such
High gain parameters of LNA for various applications
emerging device topology called HEMT is usually
at wireless sensor networks at 2.4 GHz employing cascode
employed in MMIC for 60 GHz building blocks via two
topology at the first stage with Type 2 and CS amplifier at
stage cascade LNA as reported in [9]. Introducing
the next stage help to improvise the S21 is recorded in [11].
emerging nano transistor topologies has proved remarkable
Major positive outcome in this design was achieving

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 Proceedings of the Sixth International Conference on Computing Methodologies and Communication (ICCMC 2022)
IEEE Xplore Part Number: CFP22K25-ART; ISBN: 978-1-6654-1028-1

improvement in both the parameters with minimal trade off The paper is arranged as follows: section II includes
with respect to parasitic effects. explanation of Common Source LNA. The section III
contains the result and discussion . Ultimately, section IV is
A three-stage LNA is proposed in [7] using cascade the conclusion and emphasization of efficiency of proposed
topology. First stage guarantees high gain whereas the work.
second stage assures better linearity via complementary
II. M ET HODOLOGY
push pull topology and conventional common source
topology adds a good amount of gain to the system. Also, Among CMOS Low noise amplifiers, Common source
forward body bias technique is the reason behind minimum topology is widely preferred when compared to other
threshold voltage of the circuit, thus paving the way for low topologies. Common source topology offers very low noise
power consumption. Yet another wideband low noise figures compared to other existing topologies. In Common
amplifier via an active feedback topology has recorded the Gate topology, the noise figure increases rapidly with
implementation of forward body bias technique to reduce varying frequency, thus making it the least option for
power consumption [13] and shunt peaking is incorporated accurate amplification. Also, Common source topology is
to assure maximum gain and bandwidth. preferred for narrow band applications. Even though the
Adding an inductor to the drain of the biased transistor stability factor of the circuitry demands compensation, only
responsible for amplification minimizes the noise due to negligible trade off between the gain and the linearity is
other cascade transistors in a common source LNA [8], observed.
which also offers optimum gain and improved linearity. A. Common source LNA With Inductive load
The harmonic rejection technique realized via RC
The implementation of Type 1 is shown in fig 1. The
feedback is also one of the predominant techniques used in
enhancement of parameters such as Gain and Noise
efficient management of trade off between improved
performance is improved using the inductive effect on the
linearity and optimal gain as well as noise figure.
load. Inductive load is used because it has less impact on
[10] This provides a focused overview on Type 1, Type
noise figure when compared to resistive load. Load
2 and Type 3 LNA which assists in analyzing the dependent
parameters for employing an efficient LNA in various inductance of 7nH, Voltage divider bias circuit R0= 9.5K
communications. and R1= 15K and Output Capacitance of 600fF has been
included which also helps to get the desired gain and noise
figure.

Fig.1. Schematic of T ype 1 LNA

B. Common source LNA With Inductive Source the CMOS becomes (1/gm). Since the usage of Cascode
Degeneration architecture in the Inductive source degenerated LNA has
shown more improvement of the voltage gain such that it
The schematic of Type 2 is shown in fig 2. In order to
improves amplification. It also provides shielding, increases
enhance gain without trade off in noise figure, this topology
the output impedances of the source current etc. In the
is incorporated with variation in transistor sizing. Though
miller effect, at higher frequencies the total gain can be
most of the LNA topologies have a difficulty in designing
reduced by the miller capacitance due to the inverting
the resistors (high values) with reasonable physical size. But
voltage amplifier. But the cascode architecture reduces the
the latter can handle the small signal resistor if there exists a
miller effect and also the input impedance of the circuit.
short circuit between the gate and the diode, since it
becomes a diode-controlled device. Thus, the impedance of

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 Proceedings of the Sixth International Conference on Computing Methodologies and Communication (ICCMC 2022)
IEEE Xplore Part Number: CFP22K25-ART; ISBN: 978-1-6654-1028-1

Fig. 2. Schematic of T ype 2 LNA

C. Common source cascode LNA matching network is required between 500Ω resonant
network) to 50Ω (Output network).
The schematic implemented in 90 nm technology in
cadence of Type 3 LNA is shown in Fig 3. The input
The oxide capacitance per unit to be calculated,
matching network consists of an inductor (Lg) and an
C =ε ε /t
external capacitor (Cg) at the CMOS M0. To transfer the
ox 0 SiO2 ox

(1)
maximum power to the output there is a matching network
The resistor at input matching value is calculated,
in the output which consists of capacitors connected across
R =g L /C
the output for matching 50Ω resistance. The coupling
s m s gs

(2)
capacitor is added at the input of the Cascode CS LNA. The
bias voltage applied over the LNA is 0.5V followed by a The Gate source Capacitor (Cgs) value calculated from its
biasing resistance of 50KΩ. The biasing resistance should total value and MOSFET value,
be higher for designing the LNA for adding less noise as
input [15], although it should not exceed the value of 50K. C (external)=C (total)-C (MOS)
gs gs gs

Then the NMOS M1 is connected as Common Gate (CG)

which isolates the output resonant network. The output (3)
resistance is the parasitic resistance of the inductor Ld The source and gate inductor are calculated,
which is in parallel with the resistance at the output of the Ls+Lg=1/(ω C ) 0
2
gs

Cascode LNA which is jI02. To transfer maximum power, a (4)

Fig. 3. Schematic of Common Source Cascode LNA

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 Proceedings of the Sixth International Conference on Computing Methodologies and Communication (ICCMC 2022)
IEEE Xplore Part Number: CFP22K25-ART; ISBN: 978-1-6654-1028-1

III. RESULT S A ND DISCUSSION

The Design of Type 1, Type 2 and Type 3 LNAs are
accomplished using cadence in 90nm technology with
optimal Gain and noise figure.

The Results obtained for Common Source Inductive

Load(Type 1) is shown in the fig 4. The S 21 is computed by
S-parameter analysis in cadence and found to be 5dB. By
proper variation of the voltage divider bias and transistor Fig. 6. S21 of T ype 3 LNA in 90nm
sizing, the gain and noise figure is optimized. The input
reflection coefficient (S11 ) is found to be -150.96dB. The
The reflection coefficient at the input (S 11 ) has been
output reflection coefficient (S22) is found to be -2.56dB.
achieved in narrowband input matching in which S 11 is -5.45
Reverse gain coefficient (S12 ) is found to be -35.88dB. The
dB shown in the fig 7.
noise figure is found to be 3.101dB.

Fig. 4. - Performance parameters of Common source inductive load LNA

The Results obtained for Type 2 LNA is shown in the

fig 5. S21 is computed by S-parameter analysis in cadence Fig. 7. S11 of T ype 3 LNA in 90nm
and found to be 25.178dB. By varying the voltage divider
bias circuit and sizing of the transistor the gain is Since the operating point and Source resistance design
altered.The input reflection coefficient (S11 ) is found to be - parameter enhances the minimal noise figure at Cascode CS
1.826dB. The output reflection coefficient (S22 ) is found to LNA, the output reflection coefficient is obtained as -
be -2.178dB. Reverse gain coefficient (S12 ) is found to be - 822.81dBm as shown in fig 8.
31.664dB. The noise figure is minimized and it is found to
be 1.382dB.

Fig. 8. S22 of T ype 3 LNA in 90nm

Fig. 5. Performance parameters of Common source inductive degeneration
LNA Reverse gain coefficient (S12 ) peaked at the desired band
range of 2.4GHz and it is obtained to be -35.7072dB as
The Results obtained for Common Source shown in fig 9.
Cascode(Type 3) LNA are as follows. The Forward Gain
Coefficient (S21 ) of Cascode Common Source LNA is
found to be 7.816dB shown in the fig 6. By varying the
voltage divider bias circuit and sizing of the transistor the
gain is altered.

Fig. 9. S12 of T ype 3 LNA

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 Proceedings of the Sixth International Conference on Computing Methodologies and Communication (ICCMC 2022)
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The obtained Noise Figure is obtained as a flat line in Fig

10 and achieved as a value of 3.48698dB.

Fig. 10. Noise Figure of T ype 3 LNA in 90nm

TABLE I.
PERFO RMANCE CO MPARISO N OF INDUCTIVE DEGENERATIO N AND INDUCTIVE LO AD LNA

REFERENCES TOPOLOG Y NF G AIN S 11 S 22 S 12

(dB) (dB) (dB) (dB) (dB)

[1] Inductive Common Source 0.7 12 -14 -34 -52

Degeneration (250 Nm)

[2] Inductive Common Source -0.063 -31.9 -24 - -

Degeneration (90nm)

[3] Inductive Source Degeneration 2.3 18.3 -22.6 -7.2 -39.5

(45nm)

[4] Inductive Source Degeneration 0.58 11 9.6 -2.2 -16

(90nm)
[6] Inductive Source Degeneration 2.2 25.3 -12.2 -12 -
T echnique(180 Nm)

[7] Inductive Source Degeneration 3.9 21 -5 -10.6 -70.6

T echnique (130 Nm)

Proposed Work Inductive Source Degeneration 1.382 25.1783 -1.826 2.17861 -31.6649
(90 Nm)
Proposed Work Common Source With 3.101 5 -150.96 -2.56 -35.88
Inductive Load
Technique (90nm)

TABLE II.
PERFO RMANCE CO MPARISO N OF CASCO DE CS LNA

REFERENCES TOPOLOG Y NF G AIN S 11 S 22 S 12

(dB) (dB) (dB) (dB) (dB)
[5] Common Source Cascode 2.9 ± 0.58 16.9 ± 1.7 <-10 <-10 <-35
T opology(0.18 𝜇m)

[8] Common Source Cascode LNA 1.92 8.6 -13 - -33

(90 Nm)

[9] T wo Stage CS Cascode LNA 3.57 16.34 -8.75 -2.43 -

(180 Nm)

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 Proceedings of the Sixth International Conference on Computing Methodologies and Communication (ICCMC 2022)
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Proposed Work Cascode CS LNA(90 Nm) 3.48698 7.8168 -5.45 -822.81M -35.7072

IV. CONCLUSION
In this paper, the various topologies of CS low noise of -2.17861dB, S12 of -31.6649dB, and NF of 1.382dB.
amplifiers for low power wireless applications designed at Type 3 topology which achieves a gain of 7.816dB, S 11 of
2.4GHz are studied. The proposed low noise amplifier is -5.45 dB, S22 of -822.81dBm, Gain S12 of -35.7072dB, and
implemented using a Type 1 topology which achieves NF of 3.48698dB which shows the LNA in efficiently
gain 5dB and S11 of -150.96dB, S22 of -2.56dB, S12 of - managing the trade off between noise figure and gain. Th e
35.88dB, and NF of 3.101dB. Type 2 topology which design and analysis are done in the Cadence virtuoso
achieves a gain of 25.1783dB. Also, S11 of -1.826dB, S22 environment in 90 nm CMOS technology.
.
cascode LNA. IEEE Journal of Solid-State Circuits, 43(3), 588-
599.
REFERENCES. [9] Rajendra Chikkanna Gowda, Cyril Prasanna Raj P. Design and
[1] Mustaffa, M. T ., Zayegh, A., Veljanovski, R., & Stojcevski, A. Analysis of Cascode LNA for 60 GHz Wireless Applications.
(2007, November). A 0.8 GHz to 1 GHz 0.25 μm CMOS low noise International Journal of Innovative T echnology and Exploring
amplifier for multi-standard receiver. In 2007 International Engineering (IJITEE), ISSN: 2278-3075, Volume-8 Issue-9, July
Conference on Intelligent and Advanced Systems (pp. 1350-1354). 2019
IEEE. [10] Khisti, M., & T urkane, S. (2016). CMOS LNA using a 130nm
[2] Malathi, D., & Gomathi, M. (2019). Design of inductively process with improved Noise Figure and linearity using Harmonic
degenerated common source RF CMOS Low Noise Amplifier. rejection technique. In 2015 International Conference on Energy
Sādhanā, 44(1), 1-9. Systems and Applications (pp. 411-414). IEEE.
[3] Bansal, M. (2020, January). Cascode Inductive Source [11] S. A. Z. Murad, R. C. Ismail, M. N. M. Isa, M. F. Ahamd and W.
Degenerated.CMOS LNA with Parallel RLC Output Matching B. Han, "High gain 2.4 GHz CMOS low noise amplifier for
Network for IEEE 802.11 Standard in 45 nm T echnology. Wireless Sensor Network Applications," 2013 IEEE International
RF and Microwave Conference.
[4] Gupta, L. Design of a 2.4 GHz Common Source LNA with
Inductive Degeneration for RF-IC. [12] Kusama, M. S., Shanthala, S., & Raj, C. P. (2018). Design of
common source low noise amplifiers with inductive source
[5] El Bakkali, M., T ouhami, N. A., Elhamadi, T . E., Elftouh, H., & degeneration in deep submicron CMOS processes. Int J Appl Eng
Lamsalli, M. (2021). High gain 0.18 μm-GaAs MMIC cascode- Res, 13(6), 4118-4123.
distributed low-noise amplifier for UWB
application. Microelectronics Journal, 108, 104970 [13] Hao, Z., Qing, D., Haitao, L., Shushan, X., Qunli, Z., & Zhigong,
W. (2012, May). A 0.1–8.5 GHz wideband CMOS LNA using
[6] Kumar, R., Kumar, M., & Srivastava, V. M. (2012). Design and forward body bias technology for SDR applications. In 2012
noise optimization of RF low noise amplifier for IEEE standard International Conference on Microwave and Millimeter Wave
802.11 a WLAN. International Journal of VLSI design & T echnology (ICMMT ) (Vol. 3, pp. 1-4). IEEE.
Communication Systems, 3(2), 165.
[14] Jasparvinithasundari, T .. (2019). Performance analysis of low noise
[7] Rastegar, H., Saryazdi, S., & Hakimi, A. (2013). A low power and amplifiers using junction less GAA T FET and conventional
high linearity UWB low noise amplifier (LNA) for 3.1–10.6 GHz MOSFET . International Journal of Recent T echnology and
wireless applications in 0.13 μm CMOS process. Microelectronics Engineering. 7. 449-452.
Journal, 44(3), 201-209.
[15] Chen, W. H., Liu, G., Zdravko, B., & Niknejad, A. M. (2008). A
[8] Fan, X., Zhang, H., & Sánchez-Sinencio, E. (2008). A noise highly linear broadband CMOS LNA employing noise and
reduction and linearity improvement technique for a differential distortion cancellation. IEEE Journal of Solid-State Circuits, 43(5),
1164-1176.

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