Computer Organization and Architecture

Designing for Performance

11th Edition

Chapter 6

Internal Memory

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 Memory Hierarchy
• Memory Hierarchy is to obtain the highest possible access
speed while minimizing the total cost of the memory system

• Memory Hierarchy

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Figure 6.20: Nonvolatile RAM within the
Memory Hierarchy

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 Main Memory
• Main Memory: Relatively large and fast memory to store
programs and data during execution.
Static Dynamic
• RAM chips:
• Flip flops to store binary • Charge on capacitor to store
information binary information
• Volatile • Volatile
• Does not need refresh • Needs to be periodically
recharged (refreshed)
• Faster read and write • Slower read and write
• Larger size per bit • Smaller size per bit
• Expensive (cost/bit) • Less expensive (cost/bit)
• Used to build memory with • Used to build memory with
small capacity, cache memory large capacity, main memory

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Table 6.1: Semiconductor Memory Types

Write
Memory Type Category Erasure Volatility
Mechanism
Read-write Electrically,
Random-access memory (RAM) Electrically Volatile
memory byte-level
Read-only memory (ROM) Read-only Masks
Not possible
Programmable ROM (PROM) memory

UV light,
Erasable PROM (EPROM)
chip-level
Nonvolatile
Electrically Erasable PROM Read-mostly Electrically, Electrically
(EEPROM) memory byte-level
Electrically,
Flash memory
block-level

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Dynamic RAM (DRAM) & Static RAM (SRAM)
• RAM technology is divided into two technologies:
– Dynamic RAM (DRAM)
– Static RAM (SRAM)

DRAM
• Made with cells that store data as charge on capacitors
• Presence or absence of charge in a capacitor is interpreted as a binary 1 or 0
• Requires periodic charge refreshing to maintain data storage
• The term dynamic refers to tendency of the stored charge to leak away, even with
power continuously applied

SRAM
• Digital device that uses the same logic elements used in the processor
• Binary values are stored using traditional flip-flop logic gate configurations
• Will hold its data as long as power is supplied to it

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 Read Only Memory (ROM)
• Contains a permanent pattern of data that cannot be changed or
added to
• No power source is required to maintain the bit values in memory
• Data or program is permanently in main memory and never needs
to be loaded from a secondary storage device
• Data is actually wired into the chip as part of the fabrication
process
– Disadvantages of this:
▪ No room for error, if one bit is wrong the whole batch of ROMs must be thrown
out
▪ Data insertion step includes a relatively large fixed cost

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Programmable ROM (PROM)
• Less expensive alternative
• Nonvolatile and may be written into only once
• Writing process is performed electrically and may be
performed by supplier or customer at a time later than the
original chip fabrication
• Special equipment is required for the writing process
• Provides flexibility and convenience
• Attractive for high volume production runs

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 Double Data Rate SDRAM (DDR SDRAM)

• Developed by the JEDEC Solid State Technology

Association (Electronic Industries Alliance’s semiconductor-
engineering-standardization body)
• Numerous companies make DDR chips, which are widely
used in desktop computers and servers
• DDR achieves higher data rates in three ways:
– First, the data transfer is synchronized to both the rising and falling edge of
the clock, rather than just the rising edge
– Second, DDR uses higher clock rate on the bus to increase the transfer rate
– Third, a buffering scheme is used

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 Embedded DRAM (eDRAM)
• eDRAM is a DRAM integrated on the same chip or MCM of an
application-specific integrated circuit (ASIC) or microprocessor
• For a number of metrics, eDRAM is intermediate between on-
chip SRAM and off-chip DRAM
– For the same surface area, eDRAM provides a larger size memory than
SRAM but smaller than off-chip DRAM
– eDRAM’s cost-per-bit is higher when compared to equivalent stand-
alone DRAM chips used as external memory, but it has a lower cost-per-
bit than SRAM
– Access time to eDRAM is greater than SRAM but, because of its
proximity and the ability to use wider busses, eDRAM provides faster
access than DRAM
• Fundamentally eDRAMs use the same designs and architectures
as DRAM
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 Main Memory
• Main Memory: RAM and ROM chip
• Typical RAM chip

• Typical ROM chip

11

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 Memory Address Map
• Example:
 Assume that a computer system needs 512 bytes of RAM and
512 bytes of ROM, using the chips shown in previous slides:
 Address space assignment to each memory chip
– We need four 128x8bits RAM’s and a 512x8bits ROM

12

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Connection of
Memory to
CPU

13

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 Memory Connection to CPU
•Memory connection to CPU
–RAM and ROM chips are connected to a CPU through
the data and address buses
–The low-order lines in the address bus select the byte
within the chips and other lines in the address bus select
a particular chip through its chip select inputs

14

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 Associative Memory
• Accessed by the content of the data rather than by an address
• Also called Content Addressable Memory (CAM)
• HW organization

• Compare each word in CAM in parallel with the content of A (Argument

Reg.)
• If CAM Word[i] = A, M(i) = 1
• Read sequentially accessing CAM for CAM Word(i) for M(i) = 1
• K(Key Register) provides a mask for choosing a particular field or key in
the argument in A
– (only those bits in the argument that have 1’s in their corresponding
15 position of K are compared)
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 Associative Memory
• Example:
• Suppose that the argument register A and the key
register K have the shown bit configuration. Only the
three most bits are compared with memory words,
because K has 1’s in these positions.
•A 101 111100
•K 111 000000
• Word 1 100 111100 (no match)
• Word 2 101 000001 (match)
16

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 Organization of CAM
• Organization of CAM
• Internal organization of a
typical cell Cij
• Associative memory of m
word, n cells per word.

One cell of associative memory

17

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