Y80 Microprocessor: Technical Manual
Y80 Microprocessor: Technical Manual
Technical Manual
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Every effort has been made to ensure the accuracy of the information contain herein. If you find errors or
inconsistencies please bring them to our attention. In all cases, however, the Verilog HDL source code for
the Y90 design defines “proper operation”.
Notice:
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construed as adjectives, whether or not the noun “microprocessor”, “CPU” or “device” are actually present.
Table of Contents
Introduction .........................................................................................................................3
Features ...............................................................................................................................5
This book documents the operation of the Y80 microprocessor. The Y80 design is sup-
plied in Verilog HDL and can be implemented in any technology supported by a logic
synthesis tool that accepts Verilog HDL. Included in the design package is a test bench
that exercises all instructions, flag settings, and representative data patterns. The test pat-
terns should achieve at least 95% fault coverage.
The Y80 CPU was designed in a clean-room environment and is compatible with the
Zilog Z80 microprocessor. Only publicly available documentation was used to create this
design so there may be minor differences where the public documentation is misleading or
lacking. The instruction execution times are not identical between the two designs. The
Y80 CPU operates with a consistent two-clock-cycle machine cycle, while the Z80
microprocessor uses machine cycles that vary from three to seven clock cycles.
This document should always be used as the final word on the operation of the Y80 CPU,
but it is useful to refer to the Zilog documentation if the description given here is too cryp-
tic. The Z80 architecture is over thirty years old, so it is assumed that it is already at least
somewhat familiar to the reader.
The Y80 CPU is accompanied by full design documentation, in the form of a large spread-
sheet, which describes nearly every facet of the internal operation of the processor. This
provides knowledgeable users the opportunity to customize the design for unique applica-
tion requirements.
3
4
Features
* 189 instructions
* Powerful vectored interrupt capability with separate interrupt vector input bus
5
Shown below are the registers visible to the programmer. The main registers have both a
primary and an alternate version. The primary register set consists of A, F, B, C, D, E, H,
and L, while the alternate register set consists of A', F', B', C', D', E', H', and L'. At any
given time only one bank is active, and care must be used when switching between banks,
as there is no way for the programmer to check which bank is active. The accumulator, A,
is the destination for all 8-bit arithmetic and logic operations, while the Flag register F
contains the flag results of arithmetic and logic operations. The other general-purpose reg-
isters can be paired, BC or DE or HL, to form 16-bit registers. There are two index regis-
ters, IX and IY, used for indexed addressing mode. The I register holds the upper eight bits
of the interrupt vector table address for use in Interrupt Mode 2. The R register is left over
from the original Z80 architecture, where it was used to hold a refresh address for
DRAMs. In the Y80 it is just another general purpose register. The Stack pointer, SP,
holds the address of the stack, and the Program Counter, PC, holds the address of the cur-
rently executing instruction.
A F
B C
D E Main Register Bank
H L
IX
IY
A’ F’
B’ C’ Alternate Register Bank
D’ E’
H’ L’
SP
PC
6
Pin Descriptions
The Y80 design does not attempt to match the signals or timing present on the Z80 micro-
processor. Rather, the interfaces and signals are optimized for use in either an ASIC or an
FPGA.
Memory and I/O use separate address and data buses in addition to the separate control
signals. The memory bus is designed to match typical ASIC and FPGA memory timing,
although it can be used with stand-alone memory devices just as easily. A separate inter-
rupt vector bus is provided for use with an interrupt controller. If desired, this interrupt
vector bus can be tied to either the memory or I/O input bus for operation more closely
resembling that of the original Z80.
The interface signals for the Y80 CPU are detailed below. Note that all inputs except the
two resets are sampled by the rising edge of the clock and all outputs change in response
to the rising edge of the clock.
clearb (input, active-Low) The Master (test) Reset signal is used to initialize all of the
flip-flops that are not initialized by the user reset signal. Most user-visible reg-
isters are not affected by the user reset, so this signal allows full initialization
for testing and simulation. This is an asynchronous signal that should be used
for Power-On Reset.
clkc (input, active-High) The CPU Clock connects to all flip-flops in the design.
dma_req (input, active-High) The DMA Request signal requests that the processor halt to
allow another bus master to transfer data on the bus. The processor only
7
releases the bus between instructions, rather than between individual bus
transactions.
halt_tran (output, active-High) The Halt Transaction signal is activated by the Halt
instruction. While in the Halt state the CPU freezes and waits for an interrupt.
The iack_tran, io_addr_out, io_data_out, io_tran, mem_addr_out,
mem_data_out, mem_tran, reti_tran and t1 signals are all inactive (Low)
during this time.
int_req (input, active-High) The Interrupt Request signal is the maskable interrupt
request. Maskable interrupts can be enabled and disabled under program con-
trol. This interrupt request is not latched, so it should remain active until an
interrupt acknowledge transaction occurs.
io_addr_out (output, 16-bit bus) The I/O Address Output bus carries the address of the I/
O port during an I/O transaction. This bus holds the current value until the
next I/O transaction or until the dma_ack signal is activated.
io_data_in (input, 8-bit bus) The I/O Data Input bus is sampled during the various I/O
input instructions. A separate bus allows peripherals to be connected without
loading the memory data bus.
io_data_out (output, 8-bit bus) The I/O Data Output bus carries the output data for I/O
output instructions. This bus holds the current value until the next I/O transac-
tion or until the dma_ack signal is activated.
io_read (output, active-High) The I/O Read signal indicates the direction of data transfer
during I/O transactions. High signals read and Low signals write. This signal
is valid only during I/O transactions.
io_strobe (output, active-High) The I/O Strobe signal is one clock cycle wide (in the
absence of Wait states) and identifies the data transfer clock cycle for I/O
transactions.
io_tran (output, active-High) The I/O Transaction signal is activated for all I/O transac-
tions.
8
ivec_data_in (input, 8-bit bus) The Interrupt Vector Data Input bus is sampled during
interrupt acknowledge transactions. If the interrupt acknowledge was for a
maskable interrupt and the CPU is in Interrupt Mode 2, this vector is used as a
pointer in the interrupt vector table to find the starting address of the interrupt
service routine.
ivec_read (output, active-High) The Interrupt Vector Read signal is one clock cycle wide
(in the absence of Wait states) and identifies the data transfer clock cycle for
interrupt acknowledge transactions.
mem_addr_out (output, 16-bit bus) The Memory Address Output bus carries the address
during memory read and write transactions. This bus holds the current value
until the next I/O transaction or until the dma_ack signal is activated.
mem_data_in (input, 8-bit bus) The Memory Data Input bus is sampled during memory
read transactions. A separate bus allows peripherals to be connected without
loading the memory data bus.
mem_data_out (output, 8-bit bus) The Memory Data Output bus carries the output data
for memory write transactions. This bus holds the current value until the next
I/O transaction or until the dma_ack signal is activated.
mem_rd (output, active-High) The Memory Read signal is one clock cycle wide (in the
absence of Wait states) and identifies the data transfer clock cycle for memory
read transactions.
mem_tran (output, active-High) The Memory Transaction signal is activated for memory
read and write transactions. The mem_tran signal is active during the Halt
state but is inactive during DMA transfers.
mem_wr (output, active-High) The Memory Write signal is one clock cycle wide (in the
absence of Wait states) and identifies the data transfer clock cycle for memory
write transactions.
resetb (input, active-Low) The User Reset signal is used to initialize all state flip-flops
and some user registers (the I, R, PC and SP registers). This is an asynchro-
nous signal.
reti_tran (output, active-High) The Return From Interrupt transaction signal is activated
immediately after the second stack read transaction during the Return From
9
Interrupt (RETI) instruction. This signal may be used by an external interrupt
controller to re-enable interrupts, for example.
t1 (output, active-High) The T1 signal is active during the first clock cycle of a bus trans-
action. This signal is inactive during the Halt state.
wait_req (input, active-High) The Wait Request signal temporarily halts the CPU, usually
to wait for memory access time to be met. The wait request is not honored
during the bus idle state, or while the halt_tran signal is active.
10
External Timing
The Y80 CPU uses a uniform two-clock-cycle machine cycle. This consistent timing sim-
plifies the design of logic external to the CPU makes it easier to track the state of the CPU.
The memory interface timing and signals are designed to make it easy to interface to stan-
dard ASIC and FPGA memories. It uses separate read and write strobes.
The I/O interface is very close to the AMBA Peripheral Bus (APB) to allow connection to
APB peripherals with a minimum of logic. It uses a single strobe with a separate direction
control. The only difference relative to the APB is the setup time for the write data. In the
APB the write data is setup one clock before the strobe; in this interface the write data
changes coincident with the leading edge of the strobe. In most cases this will not be a
problem.
The separate interrupt vector bus provides an easy way to connect to the optional interrupt
controller. The interrupt vector bus is used for Mode 2 maskable interrupts, so if this mode
is not used the vector input bus can be tied to ground and the vector strobe output ignored.
In the diagrams below only the relevant signals are shown for each transaction. All other
signals are either inactive or hold the previous value. Note that only one of the transaction
identifiers (mem_tran, io_tran, iack_tran, reti_tran, and halt_tran) can be active at a
time. If all are inactive, an idle bus transaction (usually for address calculation) is in
progress. The dma_ack signal also indicates that the bus is idle, in response to the
dma_req signal. The dma_ack signal can be active while halt_tran is active.
The wait_req input is only sampled for memory, I/O and interrupt acknowledge transac-
tions and is ignored in all other cases. Wait states will disrupt the two-clock-cycle machine
cycle rule. If this feature is important but wait states must be used, two wait states per
transaction is recommended. If memory access time is an issue it might be better to stretch
the first clock cycle of a transaction rather than add Wait states. The uniform two-clock
machine cycle makes it relatively straightforward to do this.
11
Memory Read
The figure below shows the memory read transaction, without Wait states and with one
Wait state. Memory read transactions are used for both instruction and data fetch. There is
no separate instruction/data status indicator, although this status exists internally if it is
needed.
T1 T2 T1 Tw T2
lkc
em_tran
em_rd
ait_req
12
Memory Write
The figure below shows the memory write transaction, without Wait states and with one
Wait state.
T1 T2 T1 Tw T2
lkc
em_tran
em_wr
ait_req
13
I/O Read
The figure below shows an I/O read transaction, without Wait states and with one Wait
state.
T1 T2 T1 Tw T2
lkc
o_tran
o_read
o_strobe
ait_req
14
I/O Write
The figure below shows an I/O write transaction, without Wait states and with one Wait
state.
T1 T2 T1 Tw T2
lkc
o_tran
o_tread
o_strobe
ait_req
15
Interrupt Acknowledge
The figure below shows the interrupt acknowledge transaction, without Wait states and
with one Wait state.
T1 T2 T1 Tw T2
lkc
ack_tran
vec_rd
ait_req
16
Non-maskable Interrupt
T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1
clkc
t1
mem_tran
mem_rd
mem_wr
iack_tran
nmi_req
ivec_data_in Ignored
ivec_rd
17
Interrupt Mode 0 or 1
The timing of a Mode 0 or Mode 1 interrupt acknowledge cycle is shown below. The
int_req input needs to remain active until the interrupt acknowledge transaction. The
acknowledge sequence consists of an aborted instruction fetch, the interrupt acknowledge,
and two writes to push the contents of the program counter onto the stack. Execution then
begins at address 0x0038 with an instruction fetch.
T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1
clkc
t1
mem_tran
mem_rd
mem_wr
iack_tran
int_req
ivec_data_in Ignored
ivec_rd
18
Interrupt Mode 2
The timing of a Mode 2 maskable interrupt acknowledge is shown below. The int_req
input needs to remain active until the interrupt acknowledge transaction. The acknowledge
sequence consists of an aborted instruction fetch, the interrupt acknowledge, an address
calculation cycle, two reads of the interrupt vector table and two writes to push the con-
tents of the program counter onto the stack. The processor automatically jumps to the
address fetched from the interrupt vector table for the service routine. The upper eight bits
of the interrupt vector table starting address are held in the I register in the processor. Note
that the vector must be an even number. That is, the least significant bit of the vector must
be a zero.
T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1
clkc
mem_addr_out PC-2 PC-1 PC Vector Table Vector Table+1 SP-1 SP-2 start
t1
mem_tran
mem_rd
mem_wr
iack_tran
int_req
ivec_data_in vector
ivec_rd
19
The interrupt controller in the Y80 MPU necessarily samples the int_req_bus inputs,
which changes the timing slightly. The diagram below illustrates this change for Interrupt
Mode 2. Also shown is the timing of the int_ack_bus and the int_prio_out signals.
T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1
clkc
mem_addr_out PC-2 PC-1 PC Vector Table Vector Table+1 SP-1 SP-2 start
t1
mem_tran
mem_rd
mem_wr
iack_tran
int_req
ivec_data_in vector
ivec_rd
int_req_bus
int_ack_bus
int_prio_out
Although Interrupt Mode 2 is the preferred mode for use with the interrupt controller, the
design allows the use of any interrupt mode. In Interrupt Mode 0 or 1 it will be necessary
to use the int_ack_bus signals to externally latch the information about which interrupt is
being acknowledged. This is because Interrupt Modes 0 and 1 will branch to a common
interrupt service routine, rather than the individual routines possible in Interrupt Mode 2.
20
DMA Request/Acknowledge
The timing of a DMA request and acknowledge is shown below. Note that like an inter-
rupt, the dma_req signal is only sampled at the end of instructions. This guarantees that
all instructions are atomic.
The delay from the dma_req signal to the dma_ack signal is always at least one bus
cycle, irrespective of whether the processor is running, in the Halt state or in the Sleep
state. This implies that it is more efficient to transfer multiple bytes each time that the
dma_req signal is activated.
The dma_req signal can be asserted during the Halt or Sleep states. In this case the active
dma_req signal will take precedence over int_req or nmi_req and inhibit either of these
signals from causing an exit from the Halt or Sleep state. Once the dma_req signal is
deasserted any pending or future interrupt request will cause the exit from the Halt or
Sleep state.
T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1
clkc
mem_data_out 0x00000
io_addr_out 0x00000
io_data_out 0x00000
t1
mem_tran
mem_rd
dma_req
dma_ack
21
The DMA request controller in the Y80 MPU necessarily samples the dma_req_bus
inputs, which changes the timing slightly. The diagram below illustrates this change. Also
shown is the timing of the dma_ack_bus and the dma_prio_out signals. In particular,
note that the leading edge of the dma_ack_bus signals are delayed by one clock cycle
from the normal dma_ack timing. The timing of the trailing edge of these signals is not
affected.
T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1
clkc
mem_data_out 0x00000
io_addr_out 0x00000
io_data_out 0x00000
t1
mem_tran
mem_rd
dma_req
dma_ack
dma_req_bus
dma_ack_bus
drq_prio_out
22
Halt state
The Halt state is entered when the HALT instruction is executed, as shown below. In the
Halt state the processor freezes, for an unlimited number of two clock cycle machine
cycles, with the halt_tran output active. The only way to exit the Halt state is with either
an interrupt (either nmi_req or int_req) or via reset. Note that int_req can only be used to
exit the Halt mode if interrupts are enabled when the HALT instruction is executed. The
timing for exiting the Halt state with an interrupt is also shown below.
If the Halt state is exited by an interrupt, the processor will resume instruction execution
(after the interrupt service routine) at the address of the instruction following the HALT
instruction. The minimum width of the halt_tran signal is two clock cycles.
T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1
clkc
mem_data_out 0x0000
io_addr_out 0x0000
io_data_out 0x0000
t1
mem_tran
mem_rd
iack_tran
halt_tran
int_req
The Halt state in this design is slightly different from that in the Z80 microprocessor. In
that design the processor continues to fetch the Halt instruction during the Halt state, lead-
ing to continued power dissipation. Since this operation requires the special step of
“rewinding” the PC, no attempt was made to match this operation. Rather, the Halt state
reduces the power consumption to a minimum by minimizing the number of signals that
are transitioning during this state.
23
Reset
The Reset state is entered immediately when the resetb signal goes Low, independent of
the current state, and this state continues until the first rising edge of clkc after the resetb
signal is de-asserted. At this rising edge there is a one clock cycle transient state to set up
the internal pipeline controls, and on the next clock the processor begins fetching the first
instruction from address 0x0000.
Software starting at location 0x0000 must be able to distinguish between reset, execution
of an RST 0 instruction, a trap, or watch-dog time-out. All of these cases cause the Pro-
gram Counter to be reset to 0x0000. In the case of the Y90 MPU this information is avail-
able in the System Status Block.
The minimum width of the resetb signal is set by the flip-flops used in the design. The
setup time for the resetb signal to the rising edge of the clkc signal is likewise determined
by the flip-flops used in the design.
The clearb signal has the same timing requirements as the resetb signal. The clearb sig-
nal should only be used in the power-on case, and only affects those flip-flops not affected
by the resetb signal.
Tany Tr Ts T1
clkc
resetb
mem_addr_out 0000
mem_data_out 00
io_addr_out 0000
io_data_out 00
t1
mem_tran
mem_rd
other outputs
24
Instruction Set
This chapter presents the assembly language syntax, addressing modes, flag settings,
binary encoding, and execution time for the Y80 instruction set. The entire instruction set
is presented in alphabetical order.
The assembly language syntax is identical to that used by the original Zilog assembler.
Different assembler programs may or may not use identical syntax. The syntax is pre-
sented generically at the beginning of each instruction, with the details presented for each
addressing mode later in each entry.
The operation of each instruction is specified in a format similar to Verilog HDL for min-
imum ambiguity, but no descriptive text or examples are included.
The effect of the instruction on each flag is listed, with a brief description. Normally the
flags are updated by the main operation of the instruction, but for some complex instruc-
tions different flags may be affected by different parts of the instruction. This is specified
in the description. The flags are organized as below in the F (Flag) register:
S Z U5 H U3 P/V N C
Flag Meaning
S Sign (a copy of the MSB of the result).
Z Zero (indicating that the result was zero).
U5 Unused Bit 5 (an unused Flag register bit).
H Half-Carry (carry out of the lower nibble, used for BCD math).
U3 Unused Bit 3 (an unused Flag register bit).
Parity/Overflow (parity of the result, or arithmetic overflow; depends
P/V
on the instrcuction)
N Negative (add/subtract flag, necessary for BCD math)
C Carry (arithmetic carry, or shift linkage bit)
25
Fields in the instruction are listed using shortcuts for common fields. These shortcuts
should be self-explanatory in most cases, but will be detailed here for completeness.
The most common field in the instruction specifies a CPU register, employing the follow-
ing encoding:
Word registers are similarly encoded, although the exact encoding depends on the instruc-
tion:
26
ADC
Add With Carry
Addressing
Assembly Syntax Encoding Clocks
Modes
R: ADC A, r 10001rrr 2
Notes:
27
ADC
Add With Carry (Word)
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
28
ADD
Add
Addressing
Assembly Syntax Encoding Clocks
Modes
R: ADD A, r 10000rrr 2
Notes:
29
ADD
Add (Word)
Flags: S: Unaffected.
Z: Unaffected.
H: Set if arithmetic carry out of bit 11; cleared otherwise.
P/V: Unaffected.
N: Cleared.
C: Set if arithmetic carry out of bit 15; cleared otherwise.
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
1. The ss, xx and yy fields use the standard word register select encodings.
30
AND
Logical AND
Addressing
Assembly Syntax Encoding Clocks
Modes
R: AND A, r 10100rrr 2
Notes:
31
BIT
Bit Test
Flags: S: Unaffected.
Z: Set if tested bit is zero; cleared otherwise.
H: Set.
P/V: Unaffected.
N: Cleared.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
R: BIT b, r 11001011 4
01bbbrrr
Notes:
32
CALL
Call Subroutine
Operation: SP <= SP - 2
(SP) <= PC
PC <= dst
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
33
CALL
Conditional Call Subroutine
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
34
CCF
Complement Carry Flag
CCF
Flags: S: Unaffected.
Z: Unaffected.
H: Copy of previous value of Carry flag.
P/V: Unaffected.
N: Cleared.
C: Set if previous Carry flag was zero; cleared otherwise.
Addressing
Assembly Syntax Encoding Clocks
Modes
35
CP
Compare
Operation: A - src
Addressing
Assembly Syntax Encoding Clocks
Modes
R: CP A, r 10111rrr 2
IM: CP A, n 11111110 4
----n---
Notes:
36
CPD
Compare and Decrement
CPD
Operation: A - (HL)
HL <= HL - 1
BC <= BC - 1
Addressing
Assembly Syntax Encoding Clocks
Modes
CPD 11101101 10
10101001
37
CPDR
Compare, Decrement and Repeat
CPDR
Operation: A - (HL)
HL <= HL - 1
BC <= BC - 1
repeat if BC != 0 and A - (HL) != 0
Addressing
Assembly Syntax Encoding Clocks
Modes
CPDR 11101101 8 + 4i
10111001
Notes:
1. This instruction can be interrupted after each iteration. The address saved on the stack in this case is the
address of this instruction, allowing completion of the instruction after the interrupt service routine.
38
CPI
Compare and Increment
CPI
Operation: A - (HL)
HL <= HL + 1
BC <= BC - 1
Addressing
Assembly Syntax Encoding Clocks
Modes
CPI 11101101 10
10100001
39
CPIR
Compare, Increment and Repeat
CPIR
Operation: A - (HL)
HL <= HL + 1
BC <= BC - 1
repeat if BC != 0 and A - (HL) != 0
Addressing
Assembly Syntax Encoding Clocks
Modes
CPIR 11101101 8 + 4i
10110001
Notes:
1. This instruction can be interrupted after each iteration. The address saved on the stack in this case is the
address of this instruction, allowing completion of the instruction after the interrupt service routine
40
CPL
Complement
CPL
Operation: A <= ~A
Flags: S: Unaffected.
Z: Unaffected.
H: Set.
P/V: Unaffected.
N: Set.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
CPL 00101111 2
41
DAA
Decimal Adjust Accumulator
DAA
Addressing
Assembly Syntax Encoding Clocks
Modes
DAA 00100111 2
Notes:
42
DEC
Decrement
Addressing
Assembly Syntax Encoding Clocks
Modes
R: DEC r 00rrr101 2
Notes:
43
DEC
Decrement (Word)
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
44
DI
Disable Interrupt
DI
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
DI 11110011 2
Notes:
1. Interrupts are last sampled during the machine cycle that fetches this instruction.
45
DJNZ
Decrement, Jump if Non-zero
DJNZ e
Operation: B <= B - 1
if ( B != 0) PC <= PC + e (where PC is the PC of this instruction)
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
DJNZ e 00010000 6
--(e-2)-
Notes:
1. Relative to the address of this instruction, the jump range is -126 to +129. Relative to the address of the
next instruction, the jump range is -128 to +127.
46
EI
Enable Interrupt
EI
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
EI 11111011 2
Notes:
1. Interrupts are first sampled during the fetch of the next instruction. If an interrupt is pending this instruc-
tion fetch will be ignored and an interrupt acknowledge cycle started.
47
EX
Exchange with Top-of-Stack
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
EX (SP), HL 11100011 12
Notes:
48
EX AF, AF’
Exchange Accumulator
EX AF, AF’
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
49
EX
Exchange (Word)
EX DE, HL
Operation: DE <=> HL
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
EX DE, HL 11101011 2
50
EXX
Exchange Register Bank
EXX
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
EXX 11011001 2
Notes:
51
HALT
Halt
HALT
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
HALT 01110110 4 + 2n
Notes:
1. The CPU halts with an idle bus until an interrupt is requested. The address pushed to the stack during the
interrupt acknowledge is the address of the next instruction. During Halt the mem_addr_out and
io_addr_out are driven with 0x0000, and the mem_data_out and io_data_out are driven with 0x00.
52
IM
Interrupt Mode
IM i
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
IM 0 11101101 4
01000110
IM 1 11101101 4
01010110
IM 2 11101101 4
01011110
Notes:
1. Interrupt Mode 0 always jumps to location 0x0038 in response to a maskable interrupt request.
2. Interrupt Mode 1 always jumps to location 0x0038 in response to a maskable interrupt request.
3. Interrupt Mode 2 uses the interrupt vector returned on the ivec_bus during an interrupt acknowledge
cycle, along with the contents of the I register, to access an interrupt vector table in memory. The address
stored at the selected location in the interrupt vector table is the starting addess of the interrupt service rou-
tine. Note that the least-significant bit of the interrupt vector must be zero to account for the two-byte entries
in the interrupt vector table.
53
IN
Input
IN A, src src: DA
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
IN A, (n) 11011011 8
----n---
54
IN
Input
IN r, (C) dst: R
Addressing
Assembly Syntax Encoding Clocks
Modes
IN r, (C) 11101101 8
01rrr000
Notes:
55
INC
Increment
Addressing
Assembly Syntax Encoding Clocks
Modes
R: INC r 00rrr100 2
Notes:
56
INC
Increment (Word)
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
57
IND
Input and Decrement
IND
Flags: S: Unaffected.
Z: Set if result of decrementing B is zero; cleared otherwise.
H: Unaffected.
P/V: Unaffected.
N: Set.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
IND 11101101 10
10101010
Notes:
1. For the original Z80, the S, H and P/V flags are undefined.
58
INDR
Input, Decrement and Repeat
INDR
Flags: S: Unaffected.
Z: Set if result of decrementing B is zero; cleared otherwise.
H: Unaffected.
P/V: Unaffected.
N: Set.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
INDR 11101101 8 + 4i
10111010
Notes:
1. This instruction can be interrupted after each iteration. The address saved on the stack in this case is the
address of this instruction, allowing completion of the instruction after the interrupt service routine
3. For the original Z80, the S, H and P/V flags are undefined.
59
INI
Input and Increment
INI
Flags: S: Unaffected.
Z: Set if result of decrementing B is zero; cleared otherwise.
H: Unaffected.
P/V: Unaffected.
N: Set.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
INI 11101101 10
10100010
Notes:
1. For the original Z80, the S, H and P/V flags are undefined.
60
INIR
Input, Increment and Repeat
INIR
Flags: S: Unaffected.
Z: Set if result of decrementing B is zero; cleared otherwise.
H: Unaffected.
P/V: Unaffected.
N: Set.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
INIR 11101101 8 + 6i
10110010
Notes:
1. This instruction can be interrupted after each iteration. The address saved on the stack in this case is the
address of this instruction, allowing completion of the instruction after the interrupt service routine
3. For the original Z80, the S, H and P/V flags are undefined.
61
JP
Jump
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
IM: JP mn 11000011 8
----n---
----m---
Notes:
1. The indirect jumps use the contents of the register directly for the jump address.
62
JP
Conditional Jump
JP cc, mn
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
63
JR
Jump Relative
JR e
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
JR e 00011000 6
--(e-2)-
Notes:
1. Relative to the address of this instruction, the jump range is -126 to +129. Relative to the address of the
next instruction, the jump range is -128 to +127.
64
JR
Conditional Jump Relative
JR cc, e
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
1. Relative to the address of this instruction, the jump range is -126 to +129. Relative to the address of the
next instruction, the jump range is -128 to +127.
65
LD
Load Accumulator from Memory
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
LD A, (DE) 00011010 6
66
LD
Load Accumulator from Special Register
Flags: S: Set if the contents of the Special Register is negative; cleared otherwise.
Z: Set if the contents of the Special Register is zero; cleared otherwise.
H: Cleared.
P/V: Loaded with the contents if the IFF2 interrupt enable flag.
N: Cleared.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
LD A, I 11101101 4
01010111
LD A, R 11101101 4
01011111
67
LD
Load Memory from Accumulator
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
LD (DE), A 00010010 6
68
LD
Load Memory with Immediate
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
69
LD
Load Memory from Register
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
70
LD
Load Memory from Register (Word)
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
71
LD
Load Register
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
R: LD rd, rs 01rdrrsr 2
IM LD r, n 00rrr110 4
----n---
Notes:
1. The rdr, rsr and rrr fields use the standard register select encoding
72
LD
Load Register Immediate (Word)
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
73
LD
Load Register (Word)
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
74
LD
Load Special Register from Accumulator
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
LD I, A 11101101 4
01000111
LD R, A 11101101 4
01001111
75
LD
Load Stack pointer
Operation: SP <=src
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
LD SP, HL 11111001 2
Notes:
76
LDD
Load and Decrement
LDD
Flags: S: Unaffected.
Z: Unaffected.
H: Cleared.
P/V: Set if result of decrementing BC is non-zero; cleared otherwise.
N: Cleared.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
LDD 11101101 10
10101000
77
LDDR
Load, Decrement and Repeat
LDDR
Flags: S: Unaffected.
Z: Unaffected
H: Cleared.
P/V: Set if result of decrementing BC is non-zero; cleared otherwise.
N: Cleared.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
LDDR 11101101 8 + 4i
10111010
Notes:
1. This instruction can be interrupted after each iteration. The address saved on the stack in this case is the
address of this instruction, allowing completion of the instruction after the interrupt service routine
78
LDI
Load and Increment
INI
Flags: S: Unaffected.
Z: Unaffected.
H: Cleared.
P/V: Set if result of decrementing BC is non-zero; cleared otherwise.
N: Cleared.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
LDI 11101101 10
10100000
79
LDIR
Input, Increment and Repeat
LDIR
Flags: S: Unaffected.
Z: Unaffected.
H: Cleared.
P/V: Set if result of decrementing BC is non-zero; cleared otherwise.
N: Cleared.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
LDIR 11101101 8 + 4i
10110000
Notes:
1. This instruction can be interrupted after each iteration. The address saved on the stack in this case is the
address of this instruction, allowing completion of the instruction after the interrupt service routine
80
NEG
Negate
NEG
Operation: A <= 0 - A
Addressing
Assembly Syntax Encoding Clocks
Modes
NEG 11101101 4
00100100
81
NOP
No Operation
NOP
Operation: none
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
NOP 00000000 2
82
OR
Logical OR
Addressing
Assembly Syntax Encoding Clocks
Modes
R: OR A, r 10110rrr 2
IM: OR A, n 11110110 4
----n---
Notes:
83
OTDR
Output, Decrement and Repeat
OTDR
Flags: S: Unaffected.
Z: Set if result of decrementing B is zero; cleared otherwise.
H: Unaffected.
P/V: Unaffected.
N: Set.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
OTDR 11101101 8 + 4i
10111011
Notes:
1. This instruction can be interrupted after each iteration. The address saved on the stack in this case is the
address of this instruction, allowing completion of the instruction after the interrupt service routine
3. For the original Z80, the S, H and P/V flags are undefined.
84
OTIR
Output, Increment and Repeat
OTIR
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Set if result of decrementing B is zero; cleared otherwise.
N: Cleared.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
OTIR 11101101 8 + 4i
10110011
Notes:
1. This instruction can be interrupted after each iteration. The address saved on the stack in this case is the
address of this instruction, allowing completion of the instruction after the interrupt service routine
3. For the original Z80, the S, H and P/V flags are undefined.
85
OUT
Output
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
86
OUT
Output
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
87
OUTD
Output and Decrement
OUTD
Flags: S: Unaffected.
Z: Set if result of decrementing B is zero; cleared otherwise.
H: Unaffected.
P/V: Unaffected.
N: Set.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
OUTD 11101101 10
10101011
Notes:
1. For the original Z80, the S, H and P/V flags are undefined.
88
OUTI
Output and Increment
OUTI
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Set if result of decrementing B is zero; cleared otherwise.
N: Cleared.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
OUTI 11101101 10
10100011
Notes:
1. For the original Z80, the S, H and P/V flags are undefined.
89
POP
Pop from Stack
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
90
PUSH
Push to Stack
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
91
RES
Bit Reset
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
R: RES b, r 11001011 4
10bbbrrr
Notes:
92
RET
Return from Subroutine
RET
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
RET 11001001 10
93
RET
Conditional Return from Subroutine
RET cc
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
94
RETI
Return from Interrupt
RETI
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
RETI 11101101 12
01001101
Notes:
1. This instruction activates the dedicated RETI signal out of the core.
95
RETN
Return from Non-Maskable Interrupt
RETN
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
RETN 11001001 12
01000101
96
RL
Rotate Left
Addressing
Assembly Syntax Encoding Clocks
Modes
R: RL r 11001011 4
00010rrr
Notes:
97
RLA
Rotate Left Accumulator
RLA
Flags: S: Unaffected
Z: Unaffected.
H: Cleared.
P/V: Unaffected.
N: Cleared.
C: Data from bit 7.
Addressing
Assembly Syntax Encoding Clocks
Modes
RLA 00010111 2
98
RLC
Rotate Left Circular
Addressing
Assembly Syntax Encoding Clocks
Modes
R: RLC r 11001011 4
00000rrr
Notes:
99
RLCA
Rotate Left Circular Accumulator
RLCA
Flags: S: Unaffected
Z: Unaffected.
H: Cleared.
P/V: Unaffected.
N: Cleared.
C: Data from bit 7.
Addressing
Assembly Syntax Encoding Clocks
Modes
RLCA 00000111 2
100
RLD
Rotate Left Digit
RLD
Addressing
Assembly Syntax Encoding Clocks
Modes
RLD 11101101 10
01101111
101
RR
Rotate Right
Addressing
Assembly Syntax Encoding Clocks
Modes
R: RR r 11001011 4
00011rrr
Notes:
102
RRA
Rotate Right Accumulator
RRA
Flags: S: Unaffected
Z: Unaffected.
H: Cleared.
P/V: Unaffected.
N: Cleared.
C: Data from bit 0.
Addressing
Assembly Syntax Encoding Clocks
Modes
RRA 00011111 2
103
RRC
Rotate Right Circular
Addressing
Assembly Syntax Encoding Clocks
Modes
R: RRC r 11001011 4
00001rrr
Notes:
104
RRCA
Rotate Right Circular Accumulator
RRCA
Flags: S: Unaffected
Z: Unaffected.
H: Cleared.
P/V: Unaffected.
N: Cleared.
C: Data from bit 0.
Addressing
Assembly Syntax Encoding Clocks
Modes
RRCA 00001111 2
105
RRD
Rotate Right Digit
RRD
Addressing
Assembly Syntax Encoding Clocks
Modes
RRD 11101101 10
01100111
106
RST
Restart
RST v
Operation: SP <= SP - 2
(SP) <= PC
PC <= v
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
RST v 11vvv111 8
Notes:
107
SBC
Subtract With Carry
Addressing
Assembly Syntax Encoding Clocks
Modes
R: SBC A, r 10011rrr 2
Notes:
108
SBC
Subtract With Carry (Word)
Addressing
Assembly Syntax Encoding Clocks
Modes
Notes:
109
SCF
Set Carry Flag
CCF
Operation: CF <= 1
Flags: S: Unaffected.
Z: Unaffected.
H: Cleared.
P/V: Unaffected.
N: Cleared.
C: Set.
Addressing
Assembly Syntax Encoding Clocks
Modes
SCF 00110111 2
110
SET
Bit Set
Flags: S: Unaffected.
Z: Unaffected.
H: Unaffected.
P/V: Unaffected.
N: Unaffected.
C: Unaffected.
Addressing
Assembly Syntax Encoding Clocks
Modes
R: SET b, r 11001011 4
11bbbrrr
Notes:
111
SLA
Shift Left Arithmetic
Addressing
Assembly Syntax Encoding Clocks
Modes
R: SLA r 11001011 4
00100rrr
Notes:
112
SRA
Shift Right Arithmetic
Addressing
Assembly Syntax Encoding Clocks
Modes
R: SRA r 11001011 4
00101rrr
Notes:
113
SRL
Shift Right Logical
Addressing
Assembly Syntax Encoding Clocks
Modes
R: SRL r 11001011 4
00111rrr
Notes:
114
SUB
Subtract
Addressing
Assembly Syntax Encoding Clocks
Modes
R: SUB A, r 10010rrr 2
Notes:
115
XOR
Logical Exclusive-OR
Addressing
Assembly Syntax Encoding Clocks
Modes
R: XOR A, r 10101rrr 2
Notes:
116