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Internal Architecture of The 8086 Microprocessor2

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12 views3 pages

Internal Architecture of The 8086 Microprocessor2

Uploaded by

mohamedsal-azzawi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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INTERNAL ARCHITECTURE OF THE 8086 MICROPROCESSOR

Creat by
1- Muhammed salim
2- Tareq zaid
3- Mustafa
4- Ali

Introduction :

 The 8086 microprocessor is an 8-bit/16-bit microprocessor


designed by Intel in the late 1970s. It is the first member of
the x86 family of microprocessors.
 The architecture of the 8086 microprocessor is based on a
complex instruction set computer (CISC) architecture,
which means that it supports a wide range of instructions,
many of which can perform multiple operations in a single
instruction.
 8086 microprocessor has a 20-bit address bus, which can
address up to 1 MB of memory, and a 16-bit data bus.

 The 8086 microprocessor has two main execution units:


the execution unit (EU) and the bus interface unit (BIU).

BIU: Responsible for fetching instructions, generating


addresses, and controlling input/output operations.
Key functions of the BIU include:
1. Fetching instructions.
2. Generating addresses.
3. Managing data transfer between the processor and
memory.
Segment Registers: Used to divide memory into sections such
as Code Segment (CS) , Data Segment (DS) Stack Segment(SS)
and Extra Segment(ES) .

Instruction Pointer (IP): Holds the address of the next


instruction to be executed.

Pre-fetch Queue: Allows instructions to be fetched in advance,


reducing delays and improving processing speed.

Memory segmentation:

In order to increase execution speed and fetching speed, 8086


segments the memory.
Its 20-bit address bus can address 1MB of memory, it
segments it into 16 64kB segments.
8086 works only with four 64KB segments within the whole
1MB memory.
The internal architecture of Intel 8086 is divided into 2 units:
The Bus Interface Unit (BIU), and The Execution Unit (EU).
These are explained as following below.

1. The Bus Interface Unit (BIU):


It provides the interface of 8086 to external memory and I/O
devices via the System Bus. It performs various machine
cycles such as memory read, I/O read, etc. to transfer data
between memory and I/O devices.

Instruction Pointer (IP):

It is a 16-bit register. It holds offset of the next instructions in


the Code Segment.
IP is incremented after every instruction byte is fetched.
IP gets a new value whenever a branch instruction occurs.
CS is multiplied by 10H to give the 20-bit physical address of
the Code Segment.
The address of the next instruction is calculated by using the
formula CS x 10H + IP.

Refrenses:
1- https://www.geeksforgeeks.org/architecture-of-8086/
2- https://www.slideshare.net/slideshow/internal-
architectureof8086/138317120
3-

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