Verilog for

Digital Design
Chapter 3:
Sequential Logic Design

Verilog for Digital Design

Copyright © 2007 1
Frank Vahid and Roman Lysecky
 Register Behavior

Verilog for Digital Design

Copyright © 2007 2
Frank Vahid and Roman Lysecky
 Difference between Combinational and Sequential
Circuits
• In combinational circuits, the output ONLY depends on the inputs.
• In sequential circuits, the output depends on the inputs + internal state

• In combinational circuits, we don’t have the concept of internal state. In other words, they
don’t need any memory to remember their internal state.
• In sequential circuits, we have the concept of internal state. In other words, they MUST
need some memory to remember their internal state.

• As combinational circuits don’t need any memory, so they only contain logic gates such
as and gate, or gate, not gate
• As sequential circuits MUST need memory, so they MUST contain logic gates (such as
and gate, or gate, not gate) as well as some memory element

• An simple example of memory element is flipflop. A single flipflop stores a single bit.
• The combination of flipflops is called a Register.
• It means that sequential circuits MUST have registers in addition to the logic gates.

• Combinational circuits only have logic gates

• Sequential circuits have logic gates as well as registers.
• In order to undrstand, sequential circuits, you must first understand Registers.
Verilog for Digital Design
Copyright © 2007 3
Frank Vahid and Roman Lysecky
 Register Behavior
• Sequential circuits have storage
• Register: most common storage component I3 I2 I1 I0
– N-bit register stores N bits reg(4)
– Structure may consist of connected flip-flops+ Rst
Q3 Q2 Q1 Q0
– You can write in the registers through inputs
– You can read the register through outputs
I3 I2 I1 I0
4-bit register

D D D D

Q Q Q Q
Clk R R R R

Rst
Q3 Q2 Q1 Q0

Verilog for Digital Design

Copyright © 2007 4
Frank Vahid and Roman Lysecky
 Register Behavior
Vectors
• Typically just describe register I3 I2 I1 I0
behaviorally reg(4)
– Declare output Q as reg variable Rst
to achieve storage Q3 Q2 Q1 Q0
• Uses vector types
– Collection of bits
• More convenient than declaring
separate bits like I3, I2, I1, I0 `timescale 1 ns/1 ns
– Vector's bits are numbered
module Reg4(I, Q, Clk, Rst);
• Options: [0:3], [1:4], etc.
• [3:0] input [3:0] I; //vector inputs
– Most-significant bit is on left output [3:0] Q;
– Assign with binary constant (more reg [3:0] Q;
on next slide) input Clk, Rst; //single-bit inputs
module Reg4(I3,I2,I1,I0,Q3,...);
always @(posedge Clk) begin
input I3, I2, I1, I0;
if (Rst == 1 )
I3 I2 I1 I0 Q <= 4'b0000;
else
module Reg4(I, Q, ...); Q <= I;
input [3:0] I; end
I: endmodule
I[3]I[2]I[1]I[0]
Verilog for Digital Design
Copyright © 2007 5
vldd_ch3_Reg4.v
Frank Vahid and Roman Lysecky
 Register Behavior
Constants
• Binary constant I3 I2 I1 I0
– 4'b0000
• 4: size, in number of bits reg(4)
• 'b: binary base Rst
• 0000: binary value Q3 Q2 Q1 Q0
• Other constant bases possible
– d: decimal base, o: octal base, h: hexadecimal
base
– 12'hFA2 `timescale 1 ns/1 ns
• 'h: hexadecimal base
• 12: 3 hex digits require 12 bits module Reg4(I, Q, Clk, Rst);
• FA2: hex value
– Size is always in bits, and optional input [3:0] I;
• 'hFA2 is OK output [3:0] Q;
– For decimal constant, size and 'd optional reg [3:0] Q;
• 8'd255 or just 255 input Clk, Rst;
• In previous uses like “A <= 1;” 1 and 0 are
actually decimal numbers. ‘b1 and ‘b0 would always @(posedge Clk) begin
explicitly represent bits if (Rst == 1 )
• Underscores may be inserted into value for Q <= 4'b0000;
readability else
– 12'b1111_1010_0010 Q <= I;
end
– 8_000_000 endmodule

Verilog for Digital Design

Copyright © 2007 6
vldd_ch3_Reg4.v
Frank Vahid and Roman Lysecky
 Register Behavior
• Procedure's event control I3 I2 I1 I0
involves Clk input reg(4)
– Not the I input. Thus, Rst
Q3 Q2 Q1 Q0
synchronous
– "posedge Clk"
• Event is not just any change
on Clk, but specifically
`timescale 1 ns/1 ns
change from 0 to 1 (positive
edge) module Reg4(I, Q, Clk, Rst);
• negedge also possible
input [3:0] I;
• Process has synchronous output [3:0] Q;
reg [3:0] Q;
reset input Clk, Rst;
– Resets output Q only on rising
always @(posedge Clk) begin
edge of Clk if (Rst == 1 )
• Process writes output Q else
Q <= 4'b0000;

– Q declared as reg variable, Q <= I;

thus stores value too end
endmodule

Verilog for Digital Design

Copyright © 2007 7
vldd_ch3_Reg4.v
Frank Vahid and Roman Lysecky
 `timescale 1 ns/1 ns

Register Behavior module Testbench();

Testbench reg [3:0] I_s; //for vector inputs

reg Clk_s, Rst_s; //for single bit inputs
• reg/wire declarations and wire [3:0] Q_s; // for outputs

module instantiation similar to Reg4 CompToTest(I_s, Q_s, Clk_s, Rst_s); //Inst

previous testbenches // You have to write two procedures in the test be

circuits
• Module uses two procedures
// Clock Procedure (the first one)
– One generates 20 ns clock always begin // in clock procedure always loop
• 0 for 10 ns, 1 for 10 ns Clk_s <= 0;
#10;
• Note: always procedure Clk_s <= 1;
repeats #10;
end // Note: Procedure repeats again nd again
– Other provides values for
inputs Rst and I (i.e., vectors) // Vector Procedure (the second one)
initial begin // in vector procedure initial l
• initial procedure executes just Rst_s <= 1; // making the reset line HIGH
once, does not repeat I_s <= 4'b0000; // assigning 4 bit value to
@(posedge Clk_s); // this is the main contr
• (more on next slide)
#5 Rst_s <= 0; //after 5ns, make the reset
I_s <= 4'b0000; // assigning 4 bit value to
@(posedge Clk_s); // this is the main contro
#5 Rst_s <= 0; //after 5ns, make sure that r
I_s <= 4'b1010; // assigning a new 4 bit val
@(posedge Clk_s);
Verilog for Digital Design #5 Rst_s <= 0;
Copyright © 2007 I_s <= 4'b1111;
end vldd_ch3_Reg4TB.v
8
Frank Vahid and Roman Lysecky
endmodule
 `timescale 1 ns/1 ns

Register Behavior module Testbench();

Testbench reg [3:0] I_s;

reg Clk_s, Rst_s;
• Variables/nets can be shared wire [3:0] Q_s;
between procedures
Reg4 CompToTest(I_s, Q_s, Clk_s, Rst_s);
– Only one procedure should write
to variable // Clock Procedure
• Variable can be read by many always begin
procedures Clk_s <= 0;
• Clock procedure writes to Clk_s #10;
• Vector procedures reads Clk_s Clk_s <= 1;
#10;
• Event control "@(posedge Clk_s)" end // Note: Procedure repeats
– May be prepended to statement
to synchronize execution with // Vector Procedure
event occurrence initial begin
• Statement may be just ";" as in Rst_s <= 1;
example I_s <= 4'b0000;
• In previous examples, the @(posedge Clk_s);
“statement” was a sequential #5 Rst_s <= 0;
block (begin-end) I_s <= 4'b0000;
– Test vectors thus don't include the @(posedge Clk_s);
#5 Rst_s <= 0;
clock's period hard coded I_s <= 4'b1010;
• Care taken to change input values @(posedge Clk_s);
away from clock edges #5 Rst_s <= 0;
I_s <= 4'b1111;
end
Verilog for Digital Design endmodule
Copyright © 2007 9
vldd_ch3_Reg4TB.v
Frank Vahid and Roman Lysecky
 ...
Register Behavior // Vector Procedure

Testbench
initial begin
Rst_s <= 1;
I_posedge s <= 4'b0000;
• Simulation results @(Clk_s); // the first positive edge
#5 Rst_s <= 0;
– Note that Q_s updated only I_s <= 4'b0000;
on rising clock edges @(posedge Clk_s); // the second positive edge
#5 Rst_s <= 0;
– Note Q_s thus unknown until I_s <= 4'b1010;
first clock edge @(posedge Clk_s); //the third positive edge
#5 Rst_s <= 0;
• Q_s is reset to “0000” on I_s <= 4'b1111;
first clock edge end
vldd_ch3_Reg4TB.v

Clk_s

Rst_s

I_s 0000 1010 1111 ...

always @(posedge Clk) begin
Q_s xxxx 0000 1010 1111 if (Rst == 1 )
Q <= 4'b0000; Remember that Q_s is connected to
else Q, and I_s to I, in the testbench
10 20 30 40 50 60 70 80 Q <= I;
time (ns) end
vldd_ch3_Reg4.v
...
Verilog for Digital Design
Copyright © 2007 Initial value of a bit is the 10
Frank Vahid and Roman Lysecky unknown value x
 Common Pitfalls
// Vector Procedure
always begin
• Using "always" instead of "initial" Rst_s <= 1;
I_s <= 4'b0000;
procedure @(posedge Clk_s);
– Causes repeated procedure execution ...
@(posedge Clk_s);
• Not including any delay control or event #5 Rst_s <= 0;
I_s <= 4'b1111;
control in an always procedure end

– May cause infinite loop in the simulator // Vector Procedure

always begin
• Simulator executes those statements Rst_s <= 1;
over and over, never executing I_s <= 4'b0000;
end
statements of another procedure
• Simulation time can never advance Clk_s
– Symptom – Simulator appears to just
Rst_s
hang, generating no waveforms
I_s

Q_s

Verilog for Digital Design

10 20 30 40 50 60 70 80
time (ns)
Copyright © 2007 11
Frank Vahid and Roman Lysecky
 Common Pitfalls
• Not initializing all module inputs
– May cause undefined outputs
// Vector Procedure
– Or simulator may initialize to default always begin
value. Switching simulators may cause Rst_s <= 1;
I_s <= 4'b0000;
design to fail. @(posedge Clk_s);
...
– Tip: Immediately initialize all module @(posedge Clk_s);
inputs when first writing procedure #5 Rst_s <= 0;
I_s <= 4'b1111;
end

Verilog for Digital Design

Copyright © 2007 12
Frank Vahid and Roman Lysecky
 Common Pitfalls
• Forgetting to explicitly declare as a wire
an indentifier used in a port connection
– e.g., Q_s
– Verilog implicitly declares identifier as a
net of the default net type, typically a `timescale 1 ns/1 ns
one-bit wire
module Testbench();
• Intended as shortcut to save typing for
large circuits reg [3:0] I_s;
• May not give warning message during reg Clk_s, Rst_s;
compilation wire [3:0] Q_s;
• Works fine if a one-bit wire was desired Reg4 CompToTest(I_s, Q_s, Clk_s, Rst_s);
• But may be mismatch – in this example,
the wire should have been four bits, not ...
one bit
• Unexpected simulation results
– Always explicitly declare wires
• Best to avoid use of Verilog's implicit
declaration shortcut

Verilog for Digital Design

Copyright © 2007 13
Frank Vahid and Roman Lysecky
 Finite-State Machines (FSMs)—Sequential
Behavior

Verilog for Digital Design

Copyright © 2007 14
Frank Vahid and Roman Lysecky
 Finite-State Machines (FSMs)—Sequential Behavior
• Finite-state machine (FSM) is a Inputs: B; Outputs: X
common model of sequential X=0
behavior Off B
– Example: If B=1, hold X=1 for 3
clock cycles B
X=1 X=1 X=1
• Note: Transitions implicitly ANDed
with rising clock edge On1 On2 On3
– Implementation model has two
parts: outputs

outputs
inputs
B X FSM

FSM

FSM
• State register
Combinational
• Combinational logic logic
– HDL model will reflect those two State
parts
Clk State register

StateNext
Verilog for Digital Design
Copyright © 2007 15
Frank Vahid and Roman Lysecky
 Finite-State Machines (FSMs)—Sequential Behavior
Modules with Multiple Procedures and Shared Variables
`timescale 1 ns/1 ns ...
Inputs: B; Outputs: X S_On1: begin
X=0 module LaserTimer(B, X, Clk, Rst); X <= 1;
StateNext <= S_On2;
Off B input B; end
output reg X; S_On2: begin
B input Clk, Rst; X <= 1;
StateNext <= S_On3;
X=1 X=1 X=1
parameter S_Off = 0, S_On1 = 1, end
On1 On2 On3 S_On2 = 2, S_On3 = 3; S_On3: begin
X <= 1;
reg [1:0] State, StateNext; StateNext <= S_Off;
end
outputs
inputs

X
FSM

B endcase
FSM

// CombLogic
Combinational end
always @(State, B) begin
logic case (State)
S_Off: begin // StateReg
State always @(posedge Clk) begin
X <= 0;
if (B == 0) if (Rst == 1 )
Clk State register State <= S_Off;
StateNext <= S_Off;
else else
StateNext StateNext <= S_On1; State <= StateNext;
end end
... endmodule

• Code will be
Verilog for Digital Design explained on vldd_ch3_LaserTimerBeh.v
Copyright © 2007 following slides 16
Frank Vahid and Roman Lysecky
 Finite-State Machines (FSMs)—Sequential Behavior
• Modules has two procedures `timescale 1 ns/1 ns

– One procedure for combinational module LaserTimer(B, X, Clk, Rst);

logic input B;
output reg X;
– One procedure for state register input Clk, Rst;
– But it's still a behavioral parameter S_Off = 0, S_On1 = 1,
description S_On2 = 2, S_On3 = 3;

reg [1:0] State, StateNext;

outputs
inputs

B X
FSM

FSM
// CombLogic
Combinational always @(State, B) begin
logic ...
end
State
// StateReg
State register always @(posedge Clk) begin
Clk ...
end
StateNext endmodule

Verilog for Digital Design

Copyright © 2007 vldd_ch3_LaserTimerBeh.v 17
Frank Vahid and Roman Lysecky
 Finite-State Machines (FSMs)—Sequential Behavior
Parameters
• parameter declaration `timescale 1 ns/1 ns

– Not a variable or net, but rather a module LaserTimer(B, X, Clk, Rst);

constant input B;
– A constant is a value that must be output reg X;
initialized, and that cannot be input Clk, Rst;

changed within the module’s parameter S_Off = 0, S_On1 = 1,

definition S_On2 = 2, S_On3 = 3;

– Four parameters defined reg [1:0] State, StateNext;

• S_Off, S_On1, S_On2, S_On3
// CombLogic
• Correspond to FSM’s states always @(State, B) begin
– Should be initialized to unique ...
values end

// StateReg
always @(posedge Clk) begin
...
end
endmodule

Verilog for Digital Design

Copyright © 2007 vldd_ch3_LaserTimerBeh.v 18
Frank Vahid and Roman Lysecky
 Finite-State Machines (FSMs)—Sequential Behavior

• Module declares two reg variables `timescale 1 ns/1 ns

– State, StateNext
– Each is 2-bit vector (need two bits to module LaserTimer(B, X, Clk, Rst);
represent four unique state values 0 to 3)
input B;
– Variables are shared between CombLogic
and StateReg procedures output reg X;
input Clk, Rst;
• CombLogic procedure
– Event control sensitive to State and input B parameter S_Off = 0, S_On1 = 1,
– Will output StateNext and X S_On2 = 2, S_On3 = 3;
• StateReg procedure
reg [1:0] State, StateNext;
– Sensitive to Clk input
– Will output State, which it stores // CombLogic
always @(State, B) begin
...
outputs
inputs

B X end
FSM

FSM

Combinational
logic // StateReg
State always @(posedge Clk) begin
...
Clk State register end
endmodule
StateNext

Verilog for Digital Design

Copyright © 2007 vldd_ch3_LaserTimerBeh.v 19
Frank Vahid and Roman Lysecky
 Finite-State Machines (FSMs)—Sequential Behavior
Procedures with Case Statements
• Procedure may use case statement // CombLogic
– Preferred over if-else-if when just one always @(State, B) begin
case (State)
expression determines which statement S_Off: begin
to execute X <= 0;
if (B == 0)
– case (expression) StateNext <= S_Off;
• Execute statement whose case item else
expression value matches case StateNext <= S_On1;
end
expression S_On1: begin
– case item expression : statement X <= 1;
– statement is commonly a begin-end StateNext <= S_On2;
block, as in example end
S_On2: begin
– First case item expression that matches X <= 1;
executes; remaining case items ignored StateNext <= S_On3;
end
– If no item matches, nothing executes S_On3: begin
– Last item may be "default : statement" X <= 1;
StateNext <= S_Off;
• Statement executes if none of the end
previous items matched endcase
end

Verilog for Digital Design

Copyright © 2007 vldd_ch3_LaserTimerBeh.v 20
Frank Vahid and Roman Lysecky
 Finite-State Machines (FSMs)—Sequential Behavior
Procedures with Case Statements
• FSM’s CombLogic procedure reg [1:0] State, StateNext;
– Case statement describes states
– case (State) // CombLogic
always @(State, B) begin
• Executes corresponding statement case (State)
(often a begin-end block) based on Suppose State is S_Off: begin
State's current value S_On1 X <= 0;
– A state's statements consist of if (B == 0)
StateNext <= S_Off;
• Actions of the state else
• Setting of next state (transitions) StateNext <= S_On1;
• Ex: State is S_On1 end
S_On1: begin
– Executes statements for state On1, X <= 1;
jumps to endcase StateNext <= S_On2;
end
Inputs: X; Outputs: B S_On2: begin
X=0 X <= 1;
StateNext <= S_On3;
Off B' end
S_On3: begin
X <= 1;
B StateNext <= S_Off;
X=1 X=1 X=1 end
endcase
On1 On2 On3
end
Verilog for Digital Design
Copyright © 2007 vldd_ch3_LaserTimerBeh.v 21
Frank Vahid and Roman Lysecky
 Finite-State Machines (FSMs)—Sequential Behavior

• FSM StateReg Procedure ...

parameter S_Off = 0, S_On1 = 1,
– Similar to 4-bit register S_On2 = 2, S_On3 = 3;
• Register for State is 2-bit vector reg reg [1:0] State, StateNext;
variable
– Procedure has synchronous reset ...

• Resets State to FSM’s initial state, // StateReg

S_Off always @(posedge Clk) begin
if (Rst == 1 )
State <= S_Off;
else
State <= StateNext;
end
...

Verilog for Digital Design

Copyright © 2007 vldd_ch3_LaserTimerBeh.v 22
Frank Vahid and Roman Lysecky
 Finite-State Machines (FSMs)—Sequential Behavior
Modules with Multiple Procedures and Shared Variables
`timescale 1 ns/1 ns ...
Inputs: B; Outputs: X S_On1: begin
X=0 module LaserTimer(B, X, Clk, Rst); X <= 1;
StateNext <= S_On2;
Off B input B; end
output reg X; S_On2: begin
B input Clk, Rst; X <= 1;
StateNext <= S_On3;
X=1 X=1 X=1
parameter S_Off = 0, S_On1 = 1, end
On1 On2 On3 S_On2 = 2, S_On3 = 3; S_On3: begin
X <= 1;
reg [1:0] State, StateNext; StateNext <= S_Off;
end
outputs
inputs

X
FSM

B endcase
FSM

// CombLogic
Combinational end
always @(State, B) begin
logic case (State)
S_Off: begin // StateReg
State always @(posedge Clk) begin
X <= 0;
if (B == 0) if (Rst == 1 )
Clk State register State <= S_Off;
StateNext <= S_Off;
else else
StateNext StateNext <= S_On1; State <= StateNext;
end end
... endmodule

Verilog for Digital Design

• Code should
Copyright © 2007 now be clear vldd_ch3_LaserTimerBeh.v
23
Frank Vahid and Roman Lysecky
 Finite-State Machines (FSMs)—Sequential Behavior
Self-Checking Testbenches
...
• FSM testbench // Clock Procedure
always begin
– First part of file (variable/net declarations, Clk_s <= 0;
module instantiations) similar to before #10;
Clk_s <= 1;
– Vector Procedure #10;
• Resets FSM end // Note: Procedure repeats
• Sets FSM's input values (“test vectors”)
// Vector Procedure
• Waits for specific clock cycles
initial begin
– We observe the resulting waveforms to Rst_s <= 1;
determine if FSM behaves correctly B_s <= 0;
@(posedge Clk_s);
#5 Rst_s <= 0;
Clk_s @(posedge Clk_s);
#5 B_s <= 1;
Rst_s @(posedge Clk_s);
#5 B_s <= 0;
@(posedge Clk_s);
B_s @(posedge Clk_s);
@(posedge Clk_s);
X_s end
endmodule

10 20 30 40 50 60 70 80 90 100 110
time (ns)
Verilog for Digital Design
Copyright © 2007 vldd_ch3_LaserTimerTB.v 24
Frank Vahid and Roman Lysecky
 Finite-State Machines (FSMs)—Sequential Behavior
Self-Checking Testbenches
• Reading waveforms is error-prone // Vector Procedure
• Create self-checking testbench initial begin
Rst_s <= 1;
– Use if statements to check for B_s <= 0;
@(posedge Clk_s);
expected values #5 if (X_s != 0)
• If a check fails, print error message $display("%t: Reset failed", $time);
• Ex: if X_s fell to 0 one cycle too Rst_s <= 0;
@(posedge Clk_s);
early, simulation might output: #5 B_s <= 1;
– 95: Third X=1 failed @(posedge Clk_s);
#5 B_s <= 0;
if (X_s != 1)
Clk_s $display("%t: First X=1 failed", $time);
@(posedge Clk_s);
#5 if (X_s != 1)
Rst_s $display("%t: Second X=1 failed", $time);
@(posedge Clk_s);
B_s #5 if (X_s != 1)
$display("%t: Third X=1 failed", $time);
X_s @(posedge Clk_s);
#5 if (X_s != 0)
$display("%t: Final X=0 failed", $time);
end
10 20 30 40 50 60 70 80 90 100 110
time (ns)
Verilog for Digital Design
Copyright © 2007 25
Frank Vahid and Roman Lysecky vldd_ch3_LaserTimerTBDisplay.v
 Finite-State Machines (FSMs)—Sequential Behavior
$display System Procedure
// Vector Procedure
• $display – built-in Verilog system initial begin
procedure for printing information to Rst_s <= 1;
display during simulation B_s <= 0;
– A system procedure interacts with the @(posedge Clk_s);
simulator and/or host computer system #5 if (X_s != 0)
$display("%t: Reset failed", $time);
• To write to a display, read a file, get the Rst_s <= 0;
current simulation time, etc.
@(posedge Clk_s);
• Starts with $ to distinguish from regular #5 B_s <= 1;
procedures @(posedge Clk_s);
• String argument is printed literally... #5 B_s <= 0;
– $display("Hello") will print "Hello" if (X_s != 1)
$display("%t: First X=1 failed", $time);
– Automatically adds newline character @(posedge Clk_s);
• ...except when special sequences appear #5 if (X_s != 1)
$display("%t: Second X=1 failed", $time);
– %t: Display a time expression @(posedge Clk_s);
– Time expression must be next argument #5 if (X_s != 1)
• $time – Built-in system procedure that $display("%t: Third X=1 failed", $time);
returns the current simulation time @(posedge Clk_s);
– 95: Third X=1 failed #5 if (X_s != 0)
$display("%t: Final X=0 failed", $time);
end

Verilog for Digital Design

Copyright © 2007 26
Frank Vahid and Roman Lysecky vldd_ch3_LaserTimerTBDisplay.v
Top-Down Design – FSMs to Controller Structure

Verilog for Digital Design

Copyright © 2007 27
Frank Vahid and Roman Lysecky
 Top-Down Design – FSMs to Controller Structure
K_s
• Recall from Chapter 2 Capture
Simulate P_s
behavior S_s
– Top-down design W_s
• Capture behavior, and simulate Should be
• Capture structure (circuit), K_s the same
Capture P_s
simulate again Simulate S_s
structure
• Gets behavior right first, W_s
unfettered by complexity of
outputs

outputs
inputs
creating structure B X

FSM
FSM

FSM
Combinational N1
• Capture behavior: FSM logic
N0
• Capture structure: Controller S1 S0
– Create architecture (state Clk State register
register and combinational logic)
– Encode states
– Create stable table (describes Inputs: B; Outputs: X LaserTimer example
combinational logic) X=0
– Implement combinational logic 00
B'
Off

B
Verilog for Digital Design X=1 X=1 X=1
Copyright © 2007 01 On1 10 On2 11 On3 28
Frank Vahid and Roman Lysecky
 Top-Down Design – FSMs to Controller Structure s
tp
u
o

inputs

outputs
M
S
F

FSM
b x

FSM
Combinational n1 outpu
FSM
•
logic
Recall from Chapter 2 Inputs: B; Outputs: X s1 s0
n0

– Top-down design X=0 clk State register

00
• Capture behavior, and simulate Off B'
• Capture structure (circuit),
simulate again B
X=1 X=1 X=1
• Gets behavior right first,
unfettered by complexity of 01 On1 10 On2 11 On3
creating structure
• Capture behavior: FSM
• Capture structure: Controller
– Create architecture (state
register and combinational logic)
– Encode states
– Create stable table (describes
combinational logic)
– Implement combinational logic

Verilog for Digital Design

Copyright © 2007 29
Frank Vahid and Roman Lysecky
 Top-Down Design – FSMs to Controller Structure s
tp
u
o

inputs

outputs
M
S
F

FSM
b x

FSM
Combinational n1 outpu
FSM
•
logic
Recall from Chapter 2 Inputs: B; Outputs: X s1 s0
n0

– Top-down design X=0 clk State register

00
• Capture behavior, and simulate Off B'
• Capture structure (circuit),
simulate again B
X=1 X=1 X=1
• Gets behavior right first,
unfettered by complexity of 01 On1 10 On2 11 On3
creating structure
• Capture behavior: FSM
• Capture structure: Controller
– Create architecture (state
register and combinational logic)
– Encode states
– Create stable table (describes
combinational logic)
– Implement combinational logic

X = S1 + S0
Verilog for Digital Design N1 = S1’S0 + S1S0’
Copyright © 2007 30
Frank Vahid and Roman Lysecky N0 = S1’S0’B + S1S0’
 Controller `timescale 1 ns/1 ns

module LaserTimer(B, X, Clk, Rst);

Structure input B;
output reg X;
input Clk, Rst;
outpu
FSM
• Structural description
• Test with LaserTimerTB parameter S_Off = 2'b00;

– Same results reg [1:0] State, StateNext;

// State encodings:
// S_Off 00, S_On1 01, S_On2 10, S_On3 11

X = S1 + S0 // CombLogic
N1 = S1’S0 + S1S0’ always @(State, B) begin
X <= State[1] | State[0];
N0 = S1’S0’B + S1S0’ StateNext[1] <= (~State[1] & State[0])
| (State[1] & ~State[0]);
outputs StateNext[0] <= (~State[1] & ~State[0] & B)
outputs
inputs

B X
FSM

FSM | (State[1] & ~State[0]);

FSM

Combinational N1 end
logic
Clk_s
N0 // StateReg
S1 S0 always @(posedge Clk) begin
Rst_s
if (Rst == 1 )
Clk State register State <= S_Off;
B_s
else
State <= StateNext;
X_s
end
endmodule
10 20 30 40 50 60 70 80 90 100 110
time (ns)
Verilog for Digital Design
Copyright © 2007 31
Frank Vahid and Roman Lysecky vldd_ch3_LaserTimerStruct.v
 Controller `timescale 1 ns/1 ns

module LaserTimer(B, X, Clk, Rst);

Structure input B;
output reg X;
input Clk, Rst;
outpu
FSM
• Initial state is S_Off
– Encoded as "00" parameter S_Off = 2'b00;
– State register set to reg [1:0] State, StateNext;
S_Off during FSM // State encodings:
reset // S_Off 00, S_On1 01, S_On2 10, S_On3 11
• Note that CombLogic // CombLogic
uses equations, not always @(State, B) begin
case statement X <= State[1] | State[0];
StateNext[1] <= (~State[1] & State[0])
– Actually CombLogic | (State[1] & ~State[0]);
is still behavioral StateNext[0] <= (~State[1] & ~State[0] & B)
– Do top-down design | (State[1] & ~State[0]);
end
again, this time on
CombLogic, to get // StateReg
structure always @(posedge Clk) begin
if (Rst == 1 )
State <= S_Off;
else
State <= StateNext;
end
endmodule

Verilog for Digital Design

Copyright © 2007 32
Frank Vahid and Roman Lysecky vldd_ch3_LaserTimerStruct.v
 Common Pitfall: Not Assigning Every Output in Every State
• FSM outputs should be
combinational function of // CombLogic
always @(State, B) begin
current state (for Moore FSM) X <= 0;
• Not assigning output in given case (State)
S_Off: begin
state means previous value is X <= 0;
if (B == 0)
remembered Could delete this StateNext <= S_Off;
– Output has memory without changing else
behavior (but StateNext <= S_On1;
– Behavior is not an FSM probably clearer to end
S_On1: begin
• Solution 1 keep it)
X <= 1;
– Be sure to assign every output StateNext <= S_On2;
end
in every state S_On2: begin
• Solution 2 X <= 1;
StateNext <= S_On3;
– Assign default values before end
S_On3: begin
case statement X <= 1;
– Later assignment in state StateNext <= S_Off;
end
overwrites default endcase
end
Verilog for Digital Design
Copyright © 2007 33
Frank Vahid and Roman Lysecky
 Common Pitfall: Not Assigning Every Output in Every State
• Solution 2
case State
– Assign default values before S: begin
A <= 0;
case statement B <= 1;
C <= 0; S T
– Later assignment in state end A=0 A=0
overwrites default T: begin B=1 B=0
A <= 0;
– Helps clarify which actions are B <= 0; C=0 C=1
C <= 1;
important in which state end
endcase
– Corresponds directly to the
common simplifying FSM A <= 0;
B <= 0;
diagram notation of implicitly C <= 0;
setting unassigned outputs to 0 case State S T
S: begin
B <= 1; B=1 C=1
end
T: begin
C <= 1;
end
endcase

Verilog for Digital Design

Copyright © 2007 34
Frank Vahid and Roman Lysecky
 More Simulation Concepts

Verilog for Digital Design

Copyright © 2007 35
Frank Vahid and Roman Lysecky
 The Simulation Cycle `timescale 1 ns/1 ns

module SimEx1(Q);
• Instructive to consider how an HDL
output reg Q;
simulator works reg Clk, S;
– HDL simulation is complex; we'll introduce // P1
simplified form always begin
Clk <= 0;
• Consider example SimEx1 #10;
– Three reg variables – Q, Clk, S Clk <= 1;
#10;
– Three procedures – P1, P2, P3 end

• Simulator's job: Determine values for // P2

nets and variables over time always @(S) begin
Q <= ~S;
– Repeatedly executes and suspends end
procedures
// P3
• Note: Actually considers more objects, initial begin
known collectively as processes, but we'll @ (posedge Clk);
keep matters simple here to get just the S <= 1;
basic idea of simulation @ (posedge Clk);
S <= 0;
– Maintains a simulation time Time end

endmodule
Verilog for Digital Design
Copyright © 2007 vldd_ch3_SimEx1.v
36
Frank Vahid and Roman Lysecky
 The Simulation Cycle `timescale 1 ns/1 ns

• Start of simulation module SimEx1(Q);

– Simulation time Time is 0 output reg Q;

– Bit variables/nets initialized to the unknown value x reg Clk, S;

– Execute each procedure // P1

• In any order, until stops at a delay or event control We'll use arrow always begin
to show where a Clk <= 0;
procedure stops
Clk <= 0, then stop. #10;
P1 Clk <= 1;
Procedures

Activate when Time is 0+10=10 ns.

#10;
P2 No actions, then stop. end
Activate when S changes.
No actions, then stop. // P2
P3 always @(S) begin
Activate when Clk changes to 1
Q <= ~S;
end
Time (ns): Start 0 // P3
initial begin
Q x x
Variables

@ (posedge Clk);
S <= 1;
Clk x 0 @ (posedge Clk);
S <= 0;
S x x end

endmodule
Verilog for Digital Design
Copyright © 2007 vldd_ch3_SimEx1.v 37
Frank Vahid and Roman Lysecky
 The Simulation Cycle `timescale 1 ns/1 ns

• Simulation cycle module SimEx1(Q);

– Set time to next time at which a procedure activates
output reg Q;
(note: could be same as current time) reg Clk, S;
• In this case, time = 10 ns (P1 activates)
– Execute active procedures (in any order) until stops // P1
always begin
Clk <= 0;
Activate when Time is 10 ns. #10;
P1 Clk <= 1;
Procedures

Clk <= 1, stop, activate when Time=10+10=20 ns. #10;

P2 Activate when S changes. end

// P2
P3 Activate when Clk changes to 1. always @(S) begin
Q <= ~S;
end
Time (ns): Start 0 10 // P3
initial begin
Q x x x @ (posedge Clk);
Variables

S <= 1;
Clk x 0 1 @ (posedge Clk);
S <= 0;
S x x x end

endmodule
Verilog for Digital Design
Copyright © 2007 vldd_ch3_SimEx1.v 38
Frank Vahid and Roman Lysecky
 The Simulation Cycle `timescale 1 ns/1 ns

• Simulation cycle module SimEx1(Q);

– Set time to next time at which a procedure activates output reg Q;

reg Clk, S;
• Still 10 ns; Clk just changed to 1 (P3 activates)
– Execute active procedures (in any order) until stops // P1
always begin
Clk <= 0;
Activate when Time is 20 ns. #10;
P1 Clk <= 1;
Procedures

#10;
P2 Activate when S changes. end

Activate when Clk changes to 1 // P2

P3 always @(S) begin
S <= 1, stop, activate when Clk changes to 1 again Q <= ~S;
end
Time (ns): Start 0 10 10 // P3
initial begin
Q x x x x
Variables

@ (posedge Clk);
S <= 1;
Clk x 0 1 1 @ (posedge Clk);
S <= 0;
S x x x 1 end

endmodule
Verilog for Digital Design
Copyright © 2007 vldd_ch3_SimEx1.v 39
Frank Vahid and Roman Lysecky
 The Simulation Cycle `timescale 1 ns/1 ns

• Simulation cycle module SimEx1(Q);

– Set time to next time at which a procedure output reg Q;

activates reg Clk, S;
• Still 10 ns; S just changed (P2 activates)
// P1
– Execute active procedures until stops always begin
Clk <= 0;
Activate when Time is 20 ns. #10;
P1 Clk <= 1;
Procedures

#10;
P2 Activate when S changes. end
Q <= 0 (~S), stop, activate when S changes.
// P2
P3 Activate when change on Clk to 1. always @(S) begin
Q <= ~S;
end
Time (ns): Start 0 10 10 10 // P3
initial begin
Variables

Q x x x x 0 @ (posedge Clk);
S <= 1;
Clk x 0 1 1 1 @ (posedge Clk);
S <= 0;
S x x x 1 1 end

endmodule
Verilog for Digital Design
Copyright © 2007 vldd_ch3_SimEx1.v 40
Frank Vahid and Roman Lysecky
 The Simulation Cycle `timescale 1 ns/1 ns

• Simulation cycle module SimEx1(Q);

– Set time to next time at which a procedure output reg Q;

activates reg Clk, S;
• In this case, set Time = 20 ns (P1 activates)
// P1
– Execute active procedures until stops always begin
Clk <= 0;
Activate when Time is 20 ns. #10;
P1 Clk <= 1;
Procedures

Clk <= 0, stop, activate when T=20+10=30ns. #10;

P2 Activate when S changes. end

// P2
P3 Activate when change on Clk to 1. always @(S) begin
Q <= ~S;
end
Time (ns): Init 0 10 10 10 20 // P3
initial begin
Variables

Q x x x x 0 0 @ (posedge Clk);
S <= 1;
Clk x 0 1 1 1 0 @ (posedge Clk);
S <= 0;
S x x x 1 1 1 end

endmodule
Verilog for Digital Design
Copyright © 2007 vldd_ch3_SimEx1.v 41
Frank Vahid and Roman Lysecky
 The Simulation Cycle `timescale 1 ns/1 ns

• Simulation ends when user-specified time is module SimEx1(Q);

reached output reg Q;

reg Clk, S;
• Variable/net values translate to waveforms
// P1
Q always begin
x Clk <= 0;
Variables

#10;
Clk Clk <= 1;
#10;
S x end

// P2
0 10 20 30 40 50 Time (ns) always @(S) begin
Q <= ~S;
end
Time (ns): Init 0 10 10 10 20 30 30 30 40 50 // P3
initial begin
Variables

Q x x x x 0 0 0 0 1 1 1 @ (posedge Clk);
S <= 1;
Clk x 0 1 1 1 0 1 1 1 0 1 @ (posedge Clk);
S <= 0;
S x x x 1 1 1 1 0 0 0 0 end

endmodule
Verilog for Digital Design
Copyright © 2007 vldd_ch3_SimEx1.v 42
Frank Vahid and Roman Lysecky
 Variable Updates
• Assignment using "<=" ("non blocking assignment") • Simulation cycle (revised)
doesn't change variable's value immediately – Set time to next time at
which a procedure resumes
– Instead, schedules a change of value by placing an
event on an event queue – Execute active procedures
– Scheduled changes occur at end of simulation cycle – Update variables with
schedule values
• Important implications
– Procedure execution order in a simulation cycle doesn't Assume B is 0.
matter
Proc1:
• Assume procedures 1 and 2 are both active
B <= ~B;
– Proc1 schedules B to be 1, but does not change the present
value of B. B is still 0. Proc2:
– Proc2 schedules A to be 0 (the present value of B). A <= B;
– At end of simulation cycle, B is updated to 1 and A to 0 A will be 0, not 1.
– Order of assignments to different variables in a
procedure doesn't matter Proc3a: Same Proc3b:
• Assume C was 0. Scheduled values will be C=1 and D=0, C <= ~C; D <= C;
for either Proc3a or Proc3b. D <= C; C <= ~C;
– Later assignment in procedure effectively overwrites
earlier assignment
Proc4:
• E will be updated with 0, but then by 1; so E is 1 at the E <= 0;
end of the simulation cycle. ...
Verilog for Digital Design E <= 1;
Copyright © 2007 Recall FSM output assignment example,
43
Frank Vahid and Roman Lysecky in which default assignments were added
before the case statement.
 Resets

Verilog for Digital Design

Copyright © 2007 44
Frank Vahid and Roman Lysecky
 Resets
I3 I2 I1 I0
• Reset – Behavior of a register when reg(4)
a reset input is asserted Rst
Q3 Q2 Q1 Q0
• Good practice dictates having
defined reset behavior for every
register `timescale 1 ns/1 ns
• Reset behavior should always have module Reg4(I, Q, Clk, Rst);
priority over normal register behavior
input [3:0] I;
• Reset behavior output [3:0] Q;
– Usually clears register to 0s reg [3:0] Q;
input Clk, Rst;
– May initialize to other value
• e.g., state register of a controller always @(posedge Clk) begin
if (Rst == 1 )
may be initialized to encoding of Q <= 4'b0000;
initial state of FSM else
• Reset usually asserted externally at Q <= I;
end
start of sequential circuit operation, endmodule
but also to restart due to failure, user
request, or other reason

Verilog for Digital Design

Copyright © 2007 45
vldd_ch3_Reg4.v
Frank Vahid and Roman Lysecky
 Synchronous Reset
I3 I2 I1 I0
reg(4)
• Previous examples used Rst
synchronous resets Q3 Q2 Q1 Q0
– Rst input only considered
`timescale 1 ns/1 ns
during rising clock
module Reg4(I, Q, Clk, Rst);
I
input [3:0] I;
Q xxxx output [3:0] Q;
Clk reg [3:0] Q;
Rst input Clk, Rst;

always @(posedge Clk) begin

if (Rst == 1 )
Rst=1 has no effect until rising clock Q <= 4'b0000;
else
Q <= I;
end
endmodule

Verilog for Digital Design

Copyright © 2007 46
vldd_ch3_Reg4.v
Frank Vahid and Roman Lysecky
 Asynchronous Reset
I3 I2 I1 I0
• Can also use asynchronous reg(4)
Rst
reset Q3 Q2 Q1 Q0
– Rst input considered
independently from clock
• Add "posedge Rst" to `timescale 1 ns/1 ns

sensitivity list module Reg4(I, Q, Clk, Rst);

I input [3:0] I;
Q output [3:0] Q;
reg [3:0] Q;
Clk
input Clk, Rst;
Rst
Asynchronous reset always @(posedge Clk, posedge Rst) begin
Rst=1 has almost immediate effect if (Rst == 1 )
Q <= 4'b0000;
I else
Q xxxx Q <= I;
end
Clk endmodule
Rst
Synchronous reset
Rst=1 has no effect until next rising clock
Verilog for Digital Design
Copyright © 2007 47
vldd_ch3_Reg4AsyRst.v
Frank Vahid and Roman Lysecky
 Asynchronous Reset
...
• Could have used // StateReg
always @(posedge Clk) begin
asynchronous reset for FSM if (Rst == 1 )
state register too State <= S_Off;
else
Synchronous
State <= StateNext;
end
...

...
// StateReg
always @(posedge Clk, posedge Rst) begin
if (Rst == 1 )
State <= S_Off;
else Asynchronous
State <= StateNext;
end
...
vldd_ch3_LaserTimerBehAsyRst.v

Verilog for Digital Design

Copyright © 2007 48
Frank Vahid and Roman Lysecky
 Synchronous versus Asynchronous Resets
• Which is better – synchronous or asynchronous reset?
– Hotly debated in design community
• Each has pros and cons
– e.g., asynchronous can still reset even if clock is not functioning,
synchronous avoids timing analysis problems sometimes
accompanying asynchronous designs
• We won’t try to settle the debate here
– What’s important is to be consistent throughout a design
• All registers should have defined reset behavior that takes priority
over normal register behavior
• That behavior should all be synchronous reset or all be
asynchronous reset
– We will use synchronous resets in all of our remaining examples

Verilog for Digital Design

Copyright © 2007 49
Frank Vahid and Roman Lysecky
 Describing Safe FSMs

Verilog for Digital Design

Copyright © 2007 50
Frank Vahid and Roman Lysecky
 Describing Safe FSMs
• Safe FSM – If enters illegal state,
transitions to a legal state
• Example
– Suppose example has only three
states
– Two-bit encoding has illegal state
encoding "11"
• Also known as "unreachable" state Inputs: B; Outputs: X
• Not possible to enter that state under X=0
00
normal FSM operation
Off B'
• But actually possible to enter that
state due to circuit error – e.g., B
electrical noise that causes state X=1 X=1
register bit to switch 01 On1 10 On2

Verilog for Digital Design

Copyright © 2007 51
Frank Vahid and Roman Lysecky
 Describing Safe FSMs
• Safe FSM – If enters illegal state,
transitions to a legal state
• Example
– Suppose example has only three
states
– Two-bit encoding has illegal state
encoding "11"
– Safe implementation Inputs: B; Outputs: X
X=0 X=0
• Transition to appropriate legal state
00 11
• Even though that undefined state Off B'
appears to be unreachable
B
• Thus, FSM recovers from the error X=1 X=1
01 On1 10 On2

Verilog for Digital Design

Copyright © 2007 52
Frank Vahid and Roman Lysecky
 Describing Safe FSMs in VHDL
...
• Unsafe FSM description reg [1:0] State, StateNext;

– Only describes legal states, ignores always @(State, B) begin

case (State)
illegal states S_Off: begin
X <= 0;
• Some synthesis tools support "safe" if (B == 0)
option during synthesis StateNext <= S_Off;
else
– Automatically creates safe FSM from StateNext <= S_On1;
end
an unsafe FSM description S_On1: begin
X <= 1;
StateNext <= S_On2;
end
S_On2: begin
X <= 1;
StateNext <= S_Off;
end
endcase
end
...

Verilog for Digital Design

Copyright © 2007 53
Frank Vahid and Roman Lysecky
 Describing Safe FSMs in VHDL
...
• Explicitly describing a safe FSM reg [1:0] State, StateNext;
– Include case item(s) to describe illegal
always @(State, B) begin
states case (State)
– Can use "default" case item S_Off: begin
• Executes if State equals anything other X <= 0;
if (B == 0)
than S_Off, S_On1, or S_On2
StateNext <= S_Off;
• Note: Use of default is wise regardless else
of number of states StateNext <= S_On1;
end
– Even if number is power of two, S_On1: begin
because state encoding may use more X <= 1;
than minimum number of bits StateNext <= S_On2;
end
• e.g., one-hot encoding has many more S_On2: begin
illegal states than legal states X <= 1;
• Note: If synthesis tool support "safe" StateNext <= S_Off;
end
option, use it default: begin
– Otherwise, tool may automatically X <= 0;
optimize away unreachable states to StateNext <= S_Off;
end
improve performance and size, but endcase
making state machine unsafe end
Verilog for Digital Design ...
Copyright © 2007 vldd_ch3_LaserTimerBehSafe.v 54
Frank Vahid and Roman Lysecky