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CSE 491
Computer Interfacing and Peripherals

DIRECT MEMORY ACCESS CONTROLLER Introduction To Computer

(DMAC – 8237)
Architecture

1 2

Definition
Typical hardware structure of a computer system
 Microprocessor is like a function. Its takes an instruction then
4
process it & return the result .

 Without Microprocessor , no one can process anything that is the

input will return to the user without processing .

Task of Microprocessor

 Data Transfer between itself & I/O devices.

 Arithmetic and logic operations.

 Program flow via instructions.

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Block Diagram  Bus Definition

5 In computer architecture, a bus is a communication system that
transfers data between components inside a computer, or
between computers. This expression covers all related hardware
components (wire, optical fiber, etc.) and software, including
communication protocols.

Types of bus

 Address bus

 Data Bus
The block diagram of Computer system showing the address, data bus and Control
5 bus structure . 6  Control bus

Address Bus
 It request a memory location from the Memory or i/o put location Typical structure of a computer system
from the i/o devices .
7
 If the address bus is 16bit it can locate address of 0000H‐FFFFH

Data Bus
 Data bus transfer information from microprocessor & I/O devices .
 Data bus vary in size from 8 bit – 64 bit in Intel microprocessors.

Control Bus
The Control bus contains lines that select the memory or I/O devices
and causes them to perform a read or a write operation .
• MWTC
• MRDC
• IOWC
• IORC
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Introduction to Microcontrollers

 A microcontroller (MCU) is a small computer on a

single integrated circuit consisting of a relatively
Introduction To Microcontroller simple central processing unit (CPU) combined with
peripheral devices such as memories, I/O devices, and
timers.

 By some accounts, more than half of all CPUs sold

worldwide are microcontrollers

9 10

Microcontroller VS Microprocessor Microcontroller VS Microprocessor

 A microcontroller is a small computer on a single

integrated circuit containing a processor core, memory,
and programmable input/output peripherals.

 A microprocessor incorporates the functions of a

computer’s central processing unit (CPU) on a single
integrated circuit.

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Types of Microcontrollers

DIRECT MEMORY ACCESS CONTROLLER

(DMAC – 8237)

13 14

External Devices can be group into three categories:

 External Devices 1. Human readable: Appropriate for communicating with the computer user.
• Screen, printer, keyboard
 I/O Modules
2. Machine readable: Appropriate for communicating with the equipment.
• Monitoring and control
 Programmed I/O
3. Communication: Appropriate for communicating with remote devices.
• Modem
 Interrupts • Network Interface Card (NIC)

 DMA
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Techniques to synchronize data rate of

processor with peripherals
 Control signals: Establish the function
that the device will execute.
 Status signal: Indicates the state of the
device.
 Control logic: Connected with the
device controls ; the device’s operation Technique
in response to direction from the I/O
module.
 Transducer: Converts data from
electrical to other forms of energy
through output and from other forms to Direct memory
electrical through input. Polling Interrupt
 Buffer: Associated with the transducer access
to temporarily hold data being
transferred between the I/O module and
the external environment ; it is very
often 8 to 16 bits.
 Data bits: In the form of a set of bits are
17 the data , and it is sent to or received 18
from the I/O module.

I/O Data Transfer Major functions for an I/O module:

1. Control and Timing: To organize the flow of interchange

between internal resources and external devices.

2. Processor Communication: Includes command decoding , data

exchange , status reporting , address recognition.

3. Device Communication: This communication contains

commands , status information , and data.

4. Data Buffering: It is the fundamental assignment of an I/O

module.

5. Error Detection: It is usually a responsibility of the I/O module to

19 20 report errors to the CPU.
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The control of the transfer of data from an external device to the processor
consists in the following steps:

1. Processor interrogates I/O module to verify the condition of the device

connected.

2. I/O module informs the situation of the installed device .

3. If the device is prepared to transmit, the processor asks data transfer.

4. I/O module achieves a unit of data such as 8 or 16 bits from the external
device.

5. Data are moved from the I/O module to the processor.

6. Variations for output, Direct Memory Access, and so on.

21 22

I/O module communicates with the processor: 1. The processor has direct control over I/O.
 Command decoding: The I/O module accepts commands • Sensing status
from the processor.
• Read/write commands
 Data: Data are exchange between the processor and the • Transferring data
I/O module over the data bus

 Status reporting: Due to peripherals are so slow , it is 2. The processor waits for I/O module to
important to know the status of the I/O module. complete operation.

 Address recognition: As each word of memory has an

address , so does each I/O device.
3. With programmed I/O , data are exchange
23 24 between the processor and the I/O module.
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1. The processor requests I/O operation.

2. I/O module performs operation. 1. With this interrupt , the processor issues an I/O command and
continues to execute other instructions ; but is interrupted by the
I/O module when the latter has completed its work.
3. I/O module sets status bits.
2. Overcomes the processor waiting.
4. The processor checks status bits periodically.
3. The processor does not repeat checking of device.
5. I/O module does not inform the processor directly.
4. This interrupt is used when an I/O to memory transfer occurs across
the processor.
6. I/O module does not interrupt the processor.

25 7. The processor may wait or come back later. 26

1. CPU issues read command

2. I/O module gets data from peripheral while CPU does other work
3. I/O module interrupts CPU
1. Interrupt driven and programmed I/O require
4. CPU requests data
5. I/O module transfers data active CPU intervention

CPU Viewpoint • Transfer rate is limited

Issue read command • CPU is tied up
Do other work
Check for interrupt at end of each instruction cycle
If interrupted:-
Save context (registers) 2. DMA is the answer
Process interrupt
Fetch data & store
27 See Operating Systems notes 28
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BASIC DMA TERMINOLOGY

Basic DMA concept
Direct memory access (DMA) is a feature of modern computer DMA channel: system pathway used by a device to transfer
systems that allows certain hardware subsystems to read/write data
to/from memory without microprocessor intervention, allowing the
information directly to and from memory. There are usually
processor to do other work. 8 in a computer system

Used in disk controllers, video/sound cards etc, or DMA controller: dedicated hardware used for controlling
between memory locations the DMA operation
.
Typically, the CPU initiates DMA transfer, does other operations while Single‐cycle mode: DMA data transfer is done one byte at a
the transfer is in progress, and receives an interrupt from the DMA time
controller once the operation is complete.
Burst‐mode: DMA transfer is finished when all data has
been moved
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DMA pins and timing 8237 pins

 CLK: System clock

 x86 Interrupt Pins  CS΄: Chip select (decoder output)
RESET: Clears registers, sets mask register
 HOLD: DMA request. 

 READY: 0 for inserting wait states

 Sampled in the middle of any clocking cycle  HLDA: Signals that the μp has relinquished buses
 DREQ3 – DREQ0: DMA request input for each channel
 HLDA: DMA acknowledge signal.  DB7-DB0: Data bus pins
 IOR΄: Bidirectional pin used during programming and during a DMA write cycle
 Theaddress, data and control buses are set to high-Z, so the  IOW΄: Bidirectional pin used during programming and during a DMA read cycle
 EOP΄: End of process is a bidirectional signal used as input to terminate a DMA process
I/O devices can control the system bus or as output to signal the end of the DMA transfer
 A3-A0: Address pins for selecting internal registers
1 2 3 4 5 6 7 8 9  A7-A4: Outputs that provide part of the DMA transfer address
CLK  HRQ: DMA request output
HOLD  DACK3-DACK0: DMA acknowledge for each channel.
 AEN: Address enable signal
HLDA  ADSTB: Address strobe
31  MEMR΄: Memory read output used in DMA read cycle
31 32  MEMW΄: Memory write output used in DMA write cycle
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8237 DMA controller

8237

33 34

THE 8237 DMA CONTROLLER

 8237 is not a discrete component in modern

 The 8237 supplies memory & I/O with control signals and microprocessor-based systems.
memory address information during the DMA transfer.
 it appears within many system controller chip sets
 actually a special-purpose microprocessor whose job is high-
speed data transfer between memory and I/O  8237 is a four-channel device compatible
with 8086/8088, adequate for small systems.
 Previous figure shows the pin-out and block diagram of
 expandable to any number of DMA channel inputs
the 8237 programmable DMA controller.
 8237 is capable of DMA transfers at rates up to 1.6M
bytes per second.
 each channel is capable of addressing a full
64K-byte section of memory and transfer up to 64K bytes
35 36 with a single programming
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8237 Pin Definitions 8237 Pin Definitions

 Chip select enables 8237 for programming.
CLK  The CS pin is normally connected to the output of a decoder.
 The decoder does not use the 8086/8088 control signal IO/M(M/IO)
 Clock input is connected to the system clock signal as because it
contains the new memory and I/O control signals (MEMR, MEMW,
long as that signal is 5 MHz or less.  IOR and IOW).
 in the 8086/8088 system, the clock must be inverted for
the proper operation of the 8237

37 38

8237 Pin Definitions 8237 Pin Definitions

RESET READY
 The reset pin clears the command, status, request, and  A logic 0 on the ready input causes the 8237 to enter wait
temporary registers.
states for slower memory components.
 It also clears the first/last flip-flop and sets
the mask register.
 this input primes the 8237 so it is disabled
until programmed otherwise
HLDA
• A hold acknowledge signals 8237 that the microprocessor has
relinquished control of the address, data, and control buses.

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8237 Pin Definitions 8237 Pin Definitions

DREQ0–DREQ3 IOR
 DMA request inputs are used to request a transfer for  I/O read is a bidirectional pin used during programming
each of the four DMA channels.
and during a DMA write cycle.
 the polarity of these inputs is programmable, so
they are either active-high or active-low inputs

DB0–DB7 IOW
• Data bus pins are connected to the processor data • I/O write is a bidirectional pin used during
bus connections and used during the programming programming and during a DMA read cycle.
of the DMA controller.
41 42

8237 Pin Definitions 8237 Pin Definitions

A0–A3
EOP
 These address pins select an internal
 End-of-process is a bidirectional signal register during programming and provide
used as an input to terminate a DMA part of the DMA transfer address during a DMA action.
process or as an output to signal the
end of the DMA transfer.  address pins are outputs that provide part of
 often used to interrupt a DMA transfer at the DMA transfer address during a DMA action
the end of a DMA cycle
HRQ
 Hold request is an output that connects to the HOLD
input of the microprocessor in order to request a DMA
43 44
transfer.
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8237 Pin Definitions 8237 Pin Definitions

DACK0–DACK3 AEN
 Address enable signal enables the DMA address latch
 DMA channel acknowledge outputs acknowledge a channel connected to the DB7–DB0 pins on the 8237.
DMA request.  also used to disable any buffers in the system connected to
 These outputs are programmable as either active-high or active- the microprocessor
low signals.
 DACK outputs are often used to
DMA- controlled I/O device during the DMA transfer.
select the ADSTB
 Address strobe functions as ALE, except
it is used by the DMA controller to latch
address bits A15–A8 during the DMA transfer.
45 46

8237 block diagram

8237 Pin Definitions

MEMR
• Memory read is an output that causes
memory to read data during a DMA read
cycle.
MEMW
 Memory write is an output that causes memory to
write data during a DMA write cycle.

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Description
DATA BUS BUFFER:
 Five main Blocks  It contain tristate ,8 bit bi‐directional buffer.

1. Data bus buffer  Slave mode, it transfers data between microprocessor

and internal data bus.
2. Read/Control logic
 Master mode, the outputs A8‐A15 bits of memory
3. Control logic block address on data lines (Unidirectional).
4. Priority resolver READ/CONTROL LOGIC:
 It control all internal Read/Write operation.
5. DMA channels.
 Slave mode, it accepts address bits and control signal
from microprocessor.
 Master mode, it generate address bits and control signal.
49 50

8237 Internal Registers

Control logic block:
 It contains ,
CWCR
 The current word count register programs a channel for the
1. Control logic number of bytes (up to 64K) transferred during a DMA action.
2. Mode set register and  The number loaded into this register is one less than the number of
3. Status Register. bytes transferred.
CONTROL LOGIC:  for example, if a 10 is loaded to CWCR, then
 Master mode ‐It controls the sequence of DMA operation 11 bytes are transferred during the DMA action
during all DMA cycles.
 It generates address and control signals. CAR
 It increments 16 bit address and decrement 14 bit counter  The current address register (CAR) is used to hold the 16-bit
registers.
memory address used for the DMA transfer.
 It activates a HRQ signal on DMA channel Request.
51 52
 Slave mode ‐ it is disabled.
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8237 Internal Registers 8237 Internal Registers

BA and BWC CR
 The base address (BA) and base word count (BWC)  The command register programs the operation of the
registers are used when auto-initialization is selected 8237 DMA controller.
for a channel.  The register uses bit position 0 to select the memory-to-
 In auto-initialization mode, these registers memory DMA transfer mode.
are used to reload the CAR and CWCR  memory-to-memory DMA transfers use DMA channel 0 to
after the DMA action is completed. hold the source address
 allows the same count and address to be used  DMA channel 1 holds the destination address

to transfer data from the same memory area  Similar to operation of a MOVSB instruction.
53 54

8237A-5 command register. (Courtesy of Intel Corporation.)

8237 Internal Registers

MR
 The mode register programs the mode of operation
for a channel.
 Each channel has its own mode register as selected
by bit positions 1 and 0.
 remaining bits of the mode register select operation,
auto-initialization, increment/decrement, and mode for
the channel

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8237A-5 mode register. (Courtesy of Intel Corporation.)

8237 Internal Registers

BR
 The bus request register is used to request
a DMA transfer via software.
 very useful in memory-to-memory transfers,
where an external signal is not available to
begin the DMA transfer

57 58

8237A-5 request register. (Courtesy of Intel Corporation.)

8237 Internal Registers

MRSR
 The mask register set/reset sets or clears the
channel mask.
 if the mask is set, the channel is disabled
 the RESET signal sets all channel masks
to disable them

59 60
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8237A-5 mask register set/reset mode. (Courtesy of Intel Corporation.)

8237 Internal Registers

MSR

 The mask register clears or sets all of

the masks with one command instead of individual
channels, as with the MRSR.

61 62

mask register. (Courtesy of Intel Corporation.)

8237 Internal Registers

SR
 The status register shows status of each DMA
channel. The TC bits indicate if the channel has
reached its terminal count (transferred all its bytes).
 When the terminal count is reached, the DMA
transfer is terminated for most modes of operation.
 the request bits indicate whether the DREQ input for a
given channel is active

63 64
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8237A-5 status register. (Courtesy of Intel Corporation.)

Software Commands

 Three software commands are used to control the

operation of the 8237.
 These commands do not have a binary bit pattern, as
do various control registers within the 8237.
 a simple output to the correct port number enables the
software command
 Fig shows I/O port assignments that access all registers
and the software commands.

65 66

8237A-5 command and control port assignments. (Courtesy of Intel Corporation.)

8237 Software Commands

Master clear
 Acts exactly the same as the RESET signal to the 8237.
 as with the RESET signal, this command disables all channels

Clear mask register

• Enables all four DMA channels.

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8237 Software Commands Programming the Address and Count Registers

Clear the first/last flip-flop  Figure shows I/O port locations for programming the
 Clears the first/last (F/L) flip-flop within 8237.
count and address registers for each channel.
 The F/L flip-flop selects which byte (low or high order) is read/written in  The state of the F/L flip-flop determines whether the
the current address and current count registers.
 if F/L = 0, the low-order byte is selected LSB or MSB is programmed.
if F/L = 1, the high-order byte is selected

 if the state is unknown, count and address could be
 Any read or write to the address or count register automatically toggles the
F/L flip-flop. programmed incorrectly
 It is important to disable the DMA channel before
address and count are programmed.

69 70

8237A-5 DMA channel I/O port addresses. (Courtesy of Intel Corporation.)

 Four steps are required to program the 8237:

 (1) The F/L flip-flop is cleared using a clear F/L
command
 (2) the channel is disabled

 (3) LSB & MSB of the address are programmed

 (4) LSB & MSB of the count are programmed

 Once these four operations are performed, the

channel is programmed and ready to use.
 additional programming is required to select
the mode of operation before the channel is enabled and
71 72 started
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The 8237 Connected to the 80X86 Complete 8088 minimum mode DMA system.

 The address enable (AEN) output of 8237 controls the

output pins of the latches and outputs of the 74LS257 (E).
 during normal operation (AEN=0), latches A & C and
the multiplexer (E) provide address bus bits A19–A16
and A7–A0
 See Figure in next slide

73 74

Memory-to-Memory Transfer with the 8237

 The multiplexer provides the system control signals as

 Memory-to-memory transfer is much more powerful
long as the 80X86 is in control of the system.
than the automatically repeated MOVSB instruction.
 during a DMA action (AEN=1), latches A & C
 most modern chip sets do not support the memory-to-
are disabled along with the multiplexer (E)
memory feature
 latches D and B now provide address bits
A19–A16 and A15–A8  8237 requires only 2.0 µs per byte, which is over
twice as fast as a software data transfer.
 Address bus bits A7–A0 are provided directly by the
8237 and contain part of the DMA transfer address.  This is not true if an 80386, 80846, or Pentium is in
use in the system.
 The DMA controller provides control signals.

75 76
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Three methods (MODES) of DMA operation: (a) byte; (b)

A DMA controller allows the peripheral to interface directly with
memory without processor intervention. This allows the data transfer burst; (c) block.
rate to approach the access time of memory.

Types:
Sequential DMA
77 78
Simultaneous DMA

Steps in a DMA operation Modes of Operation

 Processor initiates the DMA controller  Rotating priority Mode:
 Gives device number, memory buffer pointer, …
 Called channel initialization  The priority of the channels has a circular sequence.
 Once initialized, it is ready for data transfer
 Fixed Priority Rotating Mode:
 When ready, I/O device informs the DMA  The priority is fixed.
controller
 DMA controller starts the data transfer process  TC Stop Mode
 Obtains bus by going through bus arbitration
 Auto Load mode
 Places memory address and appropriate control signals
 Completes transfer and releases the bus  Extended Write mode
 Updates memory address and count value
 If more to read, loops back to repeat the process Three DMA CYCLES: READ,WRITE,VERIFY
 Notify the processor when done
79  Typically uses an interrupt 80