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logic system design module 4

Logic System Design (APJ Abdul Kalam Technological University)

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APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY

LOGIC SYSTEM DESIGN (CST-203)

MODULE 4
NOTES
PREPARED BY : JIBIN EP, ASSISTANT PROFESSOR, EKC TC MANJERI

INDEX
SL No Topic Slide Link Video Link

1 INTRODUCTION TO INTRODUCTION TO https://youtu.be/9NitpW-

SEQUENTIAL CIRCUITS SEQUENTIAL CIRCUITS Rmzs

2 SR LATCH SR LATCH LATCH VS https://youtu.be/y8NewzE4

LATCH VS FLIPFLOP FLIPFLOP DqA

3 SR FLIPFLOP SR FLIPFLOP https://youtu.be/23C2FGN_

wts

4 D FLIPFLOP D FLIPFLOP https://youtu.be/tyV1RLUSs

AM

5 JK FLIPFLOP JK FLIPFLOP https://youtu.be/zuH42Y7d

H3M

6 T FLIPFLOP T FLIPFLOP https://youtu.be/zuH42Y7d

H3M

YOUTUBE : SHASTRA TECHNICIAL INSTITUTE

JIBIN EP, EKC TC MANJERI, 9633908979 2

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SL No Topic
INDEXSlide Link Video Link

7 RACE AROUND CONDITION AND RACE AROUND CONDITION https://youtu.be/cRjDzE11

MASTER SLAVE JK FLIPFLOP AND MASTER SLAVE JK Pk4
FLIPFLOP
8 TRUTH TABLE , CHARACTERISTIC TABLE, TRUTH TABLE , https://youtu.be/nDnfLDj
EXCITATION TABLE CHARACTERISTIC TABLE, Oxv0
CHARACTERISTIC EQUATION OF FLIPFLOP EXCITATION TABLE CHAR...

9 INTRODUCTION TO COUNTERS INTRODUCTION TO https://youtu.be/LP4844O

COUNTERS m570

10 ASYNCHRONOUS UP AND DOWN COUNTER ASYNCHRONOUS UP AND https://youtu.be/LP4844O

DOWN COUNTER m570

11 MODULO COUNTER MODULO COUNTER https://youtu.be/LP4844O

m570

12 SYNCHONOUS COUNTER SYNCHONOUS COUNTER 1https://youtu.be/PF39iLI

1r4g
https://youtu.be/PF39iLI1r
YOUTUBE : SHASTRA TECHNICIAL INSTITUTE 4g

JIBIN EP, EKC TC MANJERI, 9633908979 3

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JIBIN EP, EKC TC MANJERI, 9633908979 4

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MODULE 4
(TOPIC-1)

INTRODUCTION TO
SEQUENTIAL CIRCUITS

https://youtu.be/9NitpW-Rmzs
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JIBIN EP, EKC TC MANJERI, 9633908979 5

SEQUENTIAL CIRCUIT
• Sequential Circuit is a combinational circuit with Memory
• The output of Sequential Circuit depends upon the Present
Input and Past Output [ Present State ]
• The Information stored in the circuit represent Preset State
• The Present State and Present Input Will define the Output
and Next State
In Sequential Circuit the Present Output depends
on Present Input as well as Past Output / Past
Outputs
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SEQUENTIAL LOGIC CIRCUIT

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Combinational Circuit Sequential Circuit

Output is Only depends on the Present Output depends on Present input and
Input Past Output
Memory Element is Absent Presence of Memory Element
No Clock Signal is Applied Clock signal is Required

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Example : Half Adder , Full Adder, Examples : Flpflop , Counters and
Multiplexer Registers

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TYPES OF SEQUENTIAL CIRCUIT

Flipflop
Counter
Shift Register
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TRIGGERING METHODS

Edge Triggering Level Triggering

Types of triggering that allows a circuit
Types of triggering that allows a circuit
to become active when the clock pulse
to become active at positive edge or
is on a particular level
negative edge of the clock signal

An Event occurs at the rising edge or An Event occurs during the high voltage
falling edge level or low voltage level

Flipflops are edge triggered Latches are level triggered

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TYPES OF FLIPFLOPS

SR FLIPFLOP

D FLIPFLOP

JK FLIPFLOP

T FLIPFLOP

MASTER SLAVE JK FLIPFLOP

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MODULE 4
(TOPIC-2)

SR LATCH
LATCH VS FLIPFLOP

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Latch Flipflop
Building block of sequential circuit, Building block of sequential circuit,
Built using Logic Gates built using Latches
Check input continuously and Changes Check the input continuously and check
output correspondingly the output in a continuous manner only
with clock signal
Work with only binary inputs Work with binary input and clock signal
Can not used as register Can be used as a register

No Clock Signal FF has clock signal

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SR LATCH

Active Low SR Latch can be constructed using two cross coupled

NAND Gate

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Case 1 : S=0 , R=0

SR LATCH Invalid State
(𝑄 = 1, 𝑄 − = 1)
Case 2 : S=0, R=1
(𝑄 = 1, 𝑄 − = 0)
Set State
Case 3: S=1 , R=0
(𝑄 = 0 𝑄− = 1)
Reset State

Case 4: S=1 , R=1

Memory State
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MODULE 4
(TOPIC-3)

SR FLIPFLOP

https://youtu.be/23C2FGN_wts
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FLIPFLOP CIRCUITS
• Flip flops are actually an application of logic gates. With the
help of Boolean logic you can create memory with them.
• Flip flops can also be considered as the most basic idea of a
Random Access Memory [RAM]. When a certain input value is
given to them, they will be remembered and executed, if the
logic gates are designed correctly.
• A higher application of flip flops is helpful in designing better
electronic circuits.
• The most commonly used application of flip flops is in the
implementation of a feedback circuit. As a memory relies on
the feedback concept, flip flops can be used to design it.
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SR FLIPFLOP

• In the SR Latch we have seen that output changes occurs immediately

after the input changes occurs
• I.e., the latch is sensitive to its S and R inputs at all times
• However it can easily be modified to create a latch that is sensitive to
these inputs only when a clock input is active Such a circuit is called SR
Flipflop

S R QN+1 STATE
0 0 QN MEMORY
0 1 0 RESET
1 0 1 SET
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INSTITUTE 1 X INVALID

SR FLIPFLOP
S R QN+1 STATE
0 0 QN MEMORY
0 1 0 RESET
1 0 1 SET
1 1 X INVALID

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MODULE 4
(TOPIC-4)

D FLIPFLOP

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D FF
• The basic building block of D Flipflop is SR Flipflop
• The SR FF has two inputs S and R. The S Input is made
high to store 1 in the flipflop and R input made high to
store 0 in the flipflop
• Looking at the truth table of SR Flipflop we can realize
that when both inputs are same the output either does
not change or its invalid
• In many practical applications, these inputs are not
required
• These inputs conditions can be avoided by making them
complement of each other. This modified SR Flipflop is
known as D Flipflop
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D FF
Case 1 : D=0
Here Output 𝑄𝑁+1 Will be 0, the condition is
called Reset State

Case 2 : D=0
Here Output 𝑄𝑁+1 Will be 1, the condition is
called Set State

D QN+1 STATE
0 0 RESET
1
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1 SET

MODULE 4
(TOPIC-5)

JK FLIPFLOP

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JK FLIPFLOP
• The unnecessary in the state of SR Flipflop When S=1,R=1 can be
eliminated by converting it into JK Flipflop.
• The data input are J and K which are ANDed with
𝑄− 𝑎𝑛𝑑 𝑄 respectively, to obtain S and R inputs . Thus
•

𝑆 = 𝐽 𝑄−
𝑅=𝐾𝑄

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JK FLIPFLOP

J K QN+1 STATE
0 0 QN MEMORY
0 1 0 RESET
1 0 1 SET
1 1 QN BAR TOGGLE

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JK FLIPFLOP

J K QN+1 STATE
0 0 QN MEMORY
0 1 0 RESET
1 0 1 SET
1 1 QN BAR TOGGLE

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MODULE 4
(TOPIC-6)

T FLIPFLOP

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T FLIPFLOP
• T Flipflop is also known as Toggle Flipflop. The T Flipflop is the
modification of JK Flipflop
• The T Flipflop is obtained from JK Flipflop by connecting both inputs J
and K together
• When T=0, J=K=0 , hence there is no change in the output
• When T=1, J=K=1, and hence output Toggles

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T FLIPFLOP
When T=0, J=K=0 , hence there is no change in the output
When T=1, J=K=1, and hence output Toggles

T QN+1 STATE
0 QN MEMORY
1 QN BAR TOGGLE

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MODULE 4
(TOPIC-7)
RACE AROUND CONDITION
AND
MASTER SLAVE JK FLIPFLOP

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What is Race Around Condition

• For JK Flipflop, When J=1
and K=1 , clock is too long
then the state of FF keeps on
Toggle which leads to
uncertainty in determining
the output state of flipflop
• This Problem is called Race
Around Condition

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Methods of Eliminating Race Around Condition

T/2 < Propagation Delay
( Half Time Period is less than Propagation Delay)

Use of Negative Edge

Triggering

Master Slave JK
Flipflop
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MASTER SLAVE JK FLIPFLOP

• It Consist of Clocked JK Flipflop as master and Clocked JK Flipflop as
slave
• Output of the master FF is fed as an input of slave Flipflop
• Clock is connected directly to master flipflop, but it is connected
through inverter to slave flipflop
• In the master slave JK Flipflop the State change occurs when flipflop
goes through both positive transition of clock and negative transition
of the clock. Thus race around condition does not exist in master
slave JK Flipflop

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MASTER SLAVE JK FLIPFLOP

• Figure shows master slave JK
Flipflop. Positive clock pulses are
applied to first flipflop and
inverted clock pulses are applied
to second flipflop
• When CLK=1 first FF is enabled,
the second flipflop is inhibited
because of its clock is low
• When CLK=0, first FF is Inhibited
and Second FF is enabled
• Since the Second flipflop follows
first one , it is referred
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and the first one is called Master

MASTER SLAVE JK FLIPFLOP

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MODULE 3
(TOPIC-8)

TRUTH TABLE , CHARACTERISTIC TABLE, EXCITATION TABLE

CHARACTERISTIC EQUATION OF FLIPFLOP

https://youtu.be/nDnfLDjOxv0
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JIBIN EP, EKC TC MANJERI, 9633908979 37

SR FLIPFLOP
2
1
TRUTH TABLE CHARACTERISTIC TABLE
S R QN+1 QN S Q QN+1
0 0 QN 0 0 0 0
0 1 0
0 0 1 0
1 0 1
1 1 INVALID 0 1 0 1
3
0 1 1 X
EXCITATION
On Qn+1 S R 1 0 0 1
0 0 0 X 1 0 1 0
0 1 1 0
1 0 0 1
YOUTUBE 1
: SHASTRA TECHNICIAL 1
INSTITUTE 0 1
1 1 X 0
1 1 1 X

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D FLIPFLOP
2
1 CHARACTERITIC TABLE
TRUTH TABLE Qn D Qn+1
D QN+1 0 0 0
0 1 1
0 0 1 0 0
1 1 1 1 1

EXCITATION TABLE
3
Qn QN+1 T
0 0 0
0 1 1
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YOUTUBE

1 1 0

JK FLIPFLOP

1 TRUTH TABLE 2
CHARACTERISTIC TABLE
J K QN+1 QN J K QN+1
0 0 QN
0 0 0 0
0 1 0
0 0 1 0
1 0 1
1 1 QN BAR 0 1 0 1
0 1 1 1
3
EXCITATION
On Qn+1 J K
1 0 0 1
0 0 0 X 1 0 1 0
0 1 1 X
1 0 X 1 1 1 0 1
1 1 X YOUTUBE 1 INSTITUTE1
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T FLIPFLOP
2
1
CHARACTERITIC TABLE
TRUTH TABLE Qn T Qn+1
T QN+1 0 0 0
0 1 1
0 Qn 1 0 1
1 Qn bar 1 1 0

3 EXCITATION TABLE
Qn QN+1 T
0 0 0
0 1 1
1 0 1
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1 1 0

STATE DIAGRAMS

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MODULE 4
(TOPIC-9)

INTRODUCTION TO COUNTERS

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COUNTERS
• Counter is a sequential circuit. A digital circuit which is used
for a counting pulses is known counter. Counter is the widest
application of flip-flops. It is a group of flip-flops with a clock
signal applied. Counters are of two types.

ASYNCHRONOUS COUNTER
/ RIPPLE COUNTER
SYNCHRONOUS COUNTER
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Synchronous vs Asynchronous Counter

Synchronous Counter Asynchronous Counter
In synchronous counter, all flip flops are triggered In asynchronous counter, different flip flops are
with same clock simultaneously. triggered with different clock, not
simultaneously.
Synchronous Counter is faster than asynchronous Asynchronous Counter is slower than synchronous
counter in operation. counter in operation.
Synchronous Counter does not produce any Asynchronous Counter produces decoding error.
decoding errors.
Synchronous Counter is also called Parallel Asynchronous Counter is also called Serial
Counter. Counter.
Synchronous Counter designing as well Asynchronous Counter designing as well as
implementation are complex due to increasing implementation is very easy.
the number of states.
Synchronous Counter will operate in any desired Asynchronous Counter will operate only in fixed
count sequence. count sequence (UP/DOWN).
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In synchronous counter, propagation delay is less. In asynchronous counter, there is high
propagation delay.

MODULE 4
(TOPIC-10)

ASYNCHRONOUS UP AND DOWN COUNTER

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Asynchronous counter
• If the flip-flops do not receive the same clock signal, then that
counter is called as Asynchronous counter. The output of
system clock is applied as clock signal only to first flip-flop.
The remaining flip-flops receive the clock signal from output
of its previous stage flip-flop. Hence, the outputs of all flip-
flops do not change

Up Down Modulo
Counter Counter Counter
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3 Bit Asynchronous Up Counter

• It Consist of 3 JK Flipflops.
• In order to achieve Toggle condition, all the inputs are connected to logical high
input (J=1, K=1)
• The initial clock is applied to first flipflop directly. The clock is negative edge
triggered in order to eliminate race around condition
• The output of 1st flipflop is connected to Clock of 2nd flipflop
• The output of 2nd Flipflop is act as clock of 3rd flipflop and so on.

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Timing Diagram and Truth table

CLOCK QC QB QA
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

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Asynchronous Down Counter

• The Down Counter will count downwards from a maximum
count to zero
• In 4 bit asynchronous down counter, the clock signal is
connected to clock of first flipflop
• The clock of remaining flipflop is triggered by QA bar output of
previous stage

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4 Bit Asynchronous Down Counter

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Asynchronous Down Counter

• The Down Counter will count downwards from a maximum
count to zero
• In 4 bit asynchronous down counter, the clock signal is
connected to clock of first flipflop
• The clock of remaining flipflop is triggered by QA bar output of
previous stage

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Timing Diagram and Truth table

CLOCK QD QC QB QA
0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0
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MODULE 4
(TOPIC-11)

MODULO COUNTER

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Asynchronous Decade Counter

• This type of asynchronous counter counts upwards on each leading edge of
the input clock signal starting from "0000" until it reaches an output "1010"
(decimal 10). Both outputs QB and QD are now equal to logic "1" and the
output from the NAND gate changes state from logic "1" to a logic "0" level
and whose output is also connected to the CLEAR (CLR) inputs of all the J-K
Flip-flops. This causes all of the Q outputs to be reset back to binary "0000"
on the count of 10. Once QB and QD are both equal to logic "0" the output
of the NAND gate returns back to a logic level "1" and the counter restarts
again from "0000". We now have a decade or Modulo-10 counter

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JIBIN EP, EKC TC MANJERI, 9633908979 56

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YOUTUBE : SHASTRA TECHNICIAL INSTITUTE

JIBIN EP, EKC TC MANJERI, 9633908979 57

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MODULO-10 COUNTER (BCD Counter)

• A good example of a modulo-m counter circuit which uses external
combinational circuits to produce a counter with a modulus of 10 is
the Decade Counter. Decade (divide-by-10) counters such as the TTL
74LS90, have 10 states in its counting sequence making it suitable for
human interfacing where a digital display is required.
• The decade counter has four outputs producing a 4-bit binary number
and by using external AND and OR gates we can detect the
occurrence of the 9th counting state to reset the counter back to
zero. As with other mod counters, it receives an input clock pulse,
one by one, and counts up from 0 to 9 repeatedly.
• Once it reaches the count 9 (1001 in binary), the counter goes back
to 0000 instead of continuing on to 1010. The basic circuit of a
decade counter can be made from JK flip-flops that switch state on
the negative trailing-edge of the
YOUTUBE : SHASTRA clock signal
TECHNICIAL as shown.
INSTITUTE

MODULO-10 COUNTER (BCD Counter)

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MODULE 4
(TOPIC-12)

SYNCHONOUS COUNTER

https://youtu.be/PF39iLI1r4g
https://youtu.be/pPMXScXy0ZE
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Steps to design synchronous counter

Decide the number of flipflops

Excitation table of Flipflop

State diagram and circuit excitation table

Obtain simplified equation using kmap

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Draw the logic diagram

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Synchronous Counter

Synchronous Synchronous
Synchronous Up Synchronous
Down Up-Down
counter BCD Counter
Counter Counter

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JK Excitation Table T Excitation Table

Qn Qn+1 J K Qn Qn+1 T
0 0 0 X 0 0 0
0 1 1 X 0 1 1
1 0 X 1 1 0 1
1 1 X 0 1 1 0

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1- Design Mod-5 Synchronous Counter using JK Flipflop

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1- Design Mod-5 Synchronous Counter using JK Flipflop

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1- Design Mod-5 Synchronous Counter using JK Flipflop

YOUTUBE : SHASTRA TECHNICIAL INSTITUTE

1- Design Mod-5 Synchronous Counter using JK Flipflop

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2- Using Positive Triggering SR Flipflop design a counter counts in the

following sequence 000,111,110,101,100,011,010,001,000….

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2- Using Positive Triggering SR Flipflop design a counter counts in the

following sequence 000,111,110,101,100,011,010,001,000….

YOUTUBE : SHASTRA TECHNICIAL INSTITUTE

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2- Using Positive Triggering SR Flipflop design a counter counts in the

following sequence 000,111,110,101,100,011,010,001,000….

YOUTUBE : SHASTRA TECHNICIAL INSTITUTE

2- Using Positive Triggering SR Flipflop design a counter counts in the

following sequence 000,111,110,101,100,011,010,001,000….

YOUTUBE : SHASTRA TECHNICIAL INSTITUTE

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2- Using Positive Triggering SR Flipflop design a counter counts in the

following sequence 000,111,110,101,100,011,010,001,000….

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3- Design 3 Bit Synchronous UP-Down Counter using T Flipflop

Step 1 : Determine Number of Flipflops

It require 3 T Flipflops

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3- Design 3 Bit Synchronous UP-Down Counter using T Flipflop

Step 2 : The Excitation Table

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3- Design 3 Bit Synchronous UP-Down Counter using JK Flipflop

Step 3 : Draw the State Diagram

11
1
00
0
11
0
M=0
UPCOUNTER
00 10
1 1

01
0
10
0
M=1
01
1
DOWN COUNTER
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3- Design 3 Bit Synchronous UP-Down Counter using T Flipflop

Step 3B : The Circuit Excitation Table

Present State Next State Required Excitation
Mode
Q2 Q1 Q0 Q2* Q1* Q0* T2 T1 T0
0 0 0 0 0 0 1 0 0 1
0 0 0 1 0 1 0 0 1 1
0 0 1 0 0 1 1 0 0 1
0 0 1 1 1 0 0 1 1 1
0 1 0 0 1 0 1 0 0 1
0 1 0 1 1 1 0 0 1 1
0 1 1 0 1 1 1 0 0 1
0 1 1 1 0 0 0 1 1 1
1 0 0 0 1 1 1 1 1 1
1 0 0 1 0 0 0 0 0 1
1 0 1 0 0 0 1 0 1 1
1 0 1 1 0 1 0 0 0 1
1 1 0 0 0 1 1 1 1 1
1 1 0 1 YOUTUBE
1 0 : SHASTRA
0 TECHNICIAL
0 0 INSTITUTE
1
1 1 1 0 1 0 1 0 1 1
1 1 1 1 1 1 0 0 0 1

Design 3 Bit Asynchronous UP-Down Counter using T Flipflop

K Map Simplification and Logic Diagram

(Kindly Workout)

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PREPARED BY

Jibin EP
Assistant Professor
Department of Electronics and Communication
Eranad Knowledge City Technical Campus Manjeri
Contact :9633908979, 70121716607
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Email : [email protected], [email protected] https://www.youtube.com/ShastraTechnicalInstitute
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