UNIT IV

INTRODUCTION TO VHDL

1
Describing Hardware in VHDL
VHDL Descriptions consist of primary design units
and secondary design units.
The primary design units are the Entity and the
Package.
The secondary design units are the Architecture and
the Package Body.
Secondary design units are always related to a
primary design unit.
Libraries are collections of primary and secondary
design units.
A typical design usually contains one or more
libraries of design units.
Entity
A VHDL entity specifies the name of the entity, the
ports of the entity, and entity-related information.
ENTITY mux IS
PORT ( a, b, c, d : IN BIT;
s0, s1 : IN BIT;
x, : OUT BIT);
END mux;

2
Therefore, the entity describes the interface to the
outside world. It specifies the number of ports, the
direction of the ports, and the type of the ports.
Architectures
The architecture describes the underlying
functionality of the entity and contains the
statements that model the behavior of the entity.
An architecture is always related to an entity and
describes the behavior of that entity.
ARCHITECTURE dataflow OF mux IS
SIGNAL select : INTEGER;
BEGIN
select <= 0 WHEN s0 = ‘0’ AND s1 = ‘0’ ELSE
1 WHEN s0 = ‘1’ AND s1 = ‘0’ ELSE
2 WHEN s0 = ‘0’ AND s1 = ‘1’ ELSE
3;
x <= a AFTER 0.5 NS WHEN select = 0 ELSE
b AFTER 0.5 NS WHEN select = 1 ELSE
c AFTER 0.5 NS WHEN select = 2 ELSE
d AFTER 0.5 NS;
END dataflow;

The keywords ARCHITECTURE, BEGIN, END,

WHEN, AND, ELSE

3
All statements between the BEGIN and the END
netlist statement are called concurrent statements,
because all the statements execute concurrently.
Concurrent Signal Assignment
Inside a VHDL architecture, there is no specified
ordering of the assignment statements. The order of
execution is solely specified by events occurring on
signals that the assignment statements are sensitive
to.
A signal assignment is identified by the symbol <=.
select <= 0 WHEN s0 = ‘0’ AND s1 = ‘0’ ELSE
1 WHEN s0 = ‘1’ AND s1 = ‘0’ ELSE
2 WHEN s0 = ‘0’ AND s1 = ‘1’ ELSE
3;
Event Scheduling
The assignment to signal x does not happen
instantly. Each of the values assigned to signal x
contain an AFTER clause. The mechanism for
delaying the new value is called scheduling an event.
By assigning port x a new value, an event was
scheduled 0.5 nanoseconds in the future that
contains the new value for signal x. When the event
matures (0.5 nanoseconds in the future), signal x
receives the new value.

4
Statement Concurrency
The first assignment is the only statement to execute
when events occur on ports s0 or s1. The second
signal assignment statement does not execute unless
an event on signal select occurs or an event occurs
on ports a, b, c, d.
Structural Designs
Another way to write the mux design is to
instantiate subcomponents that perform smaller
operations of the complete model. With a model as
simple as the 4-input-1 multiplexer that we have
been using, a simple gate level description can be
generated to show how components are described
and instantiated.

5
The architecture shown below is a structural
description of the mux entity.
ARCHITECTURE netlist OF mux IS
COMPONENT andgate
PORT(a, b, c : IN bit; c : OUT BIT);
END COMPONENT;
COMPONENT inverter
PORT(in1 : IN BIT; x : OUT BIT);
END COMPONENT;
COMPONENT orgate
PORT(a, b, c, d : IN bit; x : OUT BIT);
END COMPONENT;
SIGNAL s0_inv, s1_inv, x1, x2, x3, x4 : BIT;
BEGIN
6
U1 : inverter(s0, s0_inv);
U2 : inverter(s1, s1_inv);
U3 : andgate(a, s0_inv, s1_inv, x1);
U4 : andgate(b, s0, s1_inv, x2);
U5 : andgate(c, s0_inv, s1, x3);
U6 : andgate(d, s0, s1, x4);
U7 : orgate(x2 => b, x1 => a, x4 => d, x3 => c, x => x);
END netlist;
This description uses a number of lower-level
components to model the behavior of the mux
device.
There is an inverter component, an andgate
component and an orgate component.
Each of these components is declared in the
architecture declaration section, which is between
the architecture statement and the BEGIN keyword.
A number of local signals are used to connect each
of the components to form the architecture
description. These local signals are declared using
the SIGNAL declaration.

7
Sequential Behavior
The third way to describe the functionality of the
mux is to use a process statement to describe the
functionality in an algorithmic representation.

ARCHITECTURE sequential OF mux IS

PROCESS (a, b, c, d, s0, s1)-Sensitivity List if
activated then only the statements within the
process execute the sequential statements
VARIABLE sel : INTEGER;
BEGIN
IF s0 = ‘0’ and s1 = ‘0’ THEN
sel := 0;
ELSIF s0 = ‘1’ and s1 = ‘0’ THEN
sel := 1;
ELSIF s0 = ‘0’ and s1 = ‘1’ THEN
1. Process statement – Sensitivity list means any change in the event occurring
sel := 2; inside the process list then only the sequential statements inside the process
ELSE Will be executed.
S1 ->1->0 S0->0
sel := 3; 2. Declaration part
END IF; 3. Sequential Statements are statements which will be executed in strictly in
sequential manner similarly to our programming language.
CASE sel IS
WHEN 0 =>
x <= a;
WHEN 1 =>
x <= b;
8
 WHEN 2 =>
x <= c;
WHEN OTHERS =>
x <= d;
END CASE;
END PROCESS;
END sequential;

Process Statements
The first part is called the sensitivity list; the second
part is called the process declarative part; and the
third is the statement part.
In this example, the list consists of a, b, c, d, s0, and
s1. Only events on these signals cause the process
statement to be executed.
Process Declarative Region
The process declarative part consists of the area
between the end of the sensitivity list and the
keyword BEGIN.
In this example, the declarative part contains a
variable declaration that declares local variable sel.
This variable is used locally to contain the value
computed based on ports s0 and s1.
Process Statement Part

9
The statement part of the process starts at the
keyword BEGIN and ends at the END PROCESS
line. All the statements enclosed by the process are
sequential statements. This means that any
statements enclosed by the process are executed one
after the other in a sequential order just like a typical
programming language.

Process Execution
To be consistent, let’s assume that s0 changes to 0.
Because s0 is in the sensitivity list for the process
statement, the process is invoked. Each statement in
the process is then executed sequentially.
Sequential Statements
This statement will execute sequentially. Once it is
executed, the next check of the IF statement is not
performed. Whenever a check succeeds, no other
checks are done. The IF statement has completed
and now the CASE statement will execute.
The CASE statement will evaluate the value of sel
computed earlier by the IF statement and then
execute the appropriate statement that matches the
value of sel.

10
In this example the value of sel is 1 therefore the
following statement will be executed:
x <= b;
The value of port b will be assigned to port x and
process execution will terminate because there are
no more statements in the architecture

Architecture Selection
Three architectures have been described for single
entity
Structural architecture: (i) Accuracy required.
(ii) If the model is going to be used to drive a layout
tool.
Architectures dataflow and sequential are probably
more efficient in memory space required and speed
of execution.
Typically, modelers are more familiar with
sequential coding styles, but concurrent statements
are very powerful tools for writing small efficient
models.
Configuration Statements
An entity can have more than one architecture With
this powerful statement, the modeler can pick and
choose which architectures are used to model an
entity at every level in the design.
11
The following is an example configuration:

CONFIGURATION muxcon1 OF mux IS

FOR netlist
FOR U1,U2 :
inverter USE ENTITY WORK.myinv(version1);
END FOR;
FOR U3,U4,U5,U6 :
andgate USE ENTITY WORK.myand(version1);
END FOR;
FOR U7 :
orgate USE ENTITYWORK.myor(version1);
END FOR;
END FOR;
END muxcon1;
The function of the configuration statement is to spell
out exactly which architecture to use for every
component instance in the model. This occurs in a
hierarchical fashion. The highest-level entity in the design
needs to have the architecture to use specified, as well
as any components instantiated in the design.

Introduction to Behavioral Modeling

The signal assignment statement is the most basic
form of behavioral modeling in VHDL.
12
 b

Following is an example: a <= b; a

This statement is read as follows: a gets the value of

b. The effect of this statement is that the current
value of signal b is assigned to signal a. This
statement is executed whenever signal b changes
value. Signal b is in the sensitivity list of this
statement.
The next example shows how to introduce a
nonzero delay value for the assignment:
a <= INERTIAL b after 10 ns;
This statement is read as follows: a gets the value of
b when 10 nanoseconds of time have elapsed.

Transport Versus Inertial Delay

In VHDL, there are two types of delay that can be
used for modeling behaviors.
Inertial Delay
Inertial delay is the default in VHDL. If no delay type
is specified, inertial delay is used. Inertial delay is
the default because, in most cases, it behaves
similarly to the actual device.

13
Transport Delay
Transport delay is not the default in VHDL and must be
specified. It represents a wire delay in which any pulse,
no matter how small, is propagated to the output signal
delayed by the delay value specified.

14
0 5 10 15 20 25 30 35

15
Drivers
VHDL has a unique way of handling multiply driven
signals. Multiple driven signals are very useful for
modeling a data bus, a bidirectional bus, and so on.
Correctly modeling these kinds of circuits in VHDL
requires the concept of signal drivers. A VHDL driver
is one contributor to the overall value of a signal. A
multiply driven signal has many drivers. The values
of all of the drivers are resolved together to create a
single value for the signal. The method of resolving
all of the contributors into a single value is through
a resolution function.
A resolution function is a designer-written function
that is called whenever a driver of a signal changes
value.
Consider the following architecture:
ARCHITECTURE test OF test IS
BEGIN
a <= b AFTER 10 ns;
a <= c AFTER 10 ns;
END test;

16
Signal a is being driven from two sources, b and c.
Each concurrent signal assignment statement
creates a driver for signal a. The first statement
creates a driver that contains the value of signal b
delayed by 10 nanoseconds. The second statement
creates a driver that contains the value of signal c
delayed by 10 nanoseconds. How these two drivers
are resolved is left to the designer.

17
Generics
- Generics are a general mechanism used to pass
information to an instance of an entity.
- The information passed to an entity is delay
times for rising and falling delays of the device
being modeled.
- Generics can also be used to pass any user-
defined data types, including information such
as load capacitance, resistance, and so on.
- Synthesis parameters such as datapath widths,
signal widths, and so on, can be passed in as
generics.
The following is an example of an entity for an AND
gate that has three generics associated with it:
ENTITY and2 IS
GENERIC(rise, fall : TIME; load : INTEGER);
PORT (a, b: IN BIT;
c: OUT BIT);
END AND2;
This entity allows the designer to pass in a value for
the rise and fall delays, as well as the loading that
the device has on its output.

18
Block Statements
Blocks are a partitioning mechanism within VHDL
that allow the designer to logically group areas of
the model.
Subprogram(delay)
For example, if you are designing a CPU, Main program
- one block might be an ALU, Subprogram(delay)
- another a register bank,
- and another a shifter.
Therefore, each block represents a self-contained
area of the model.
- Each block can declare local signals, types,
constants, and so on.
- Any object that can be declared in the
architecture declaration section can be declared
in the block declaration section.

19
Consider an example
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
PACKAGE bit32 IS TYPE tw32 IS ARRAY(31 DOWNTO 0) OF std_logic;
END bit32;
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
USE WORK.bit32.ALL;
ENTITY cpu IS
PORT( clk, interrupt : IN std_logic;
addr : OUT tw32; data : INOUT tw32 );
END cpu;

ARCHITECTURE cpu_blk OF cpu IS

SIGNAL ibus, dbus : tw32;
BEGIN
ALU : BLOCK
SIGNAL qbus : tw32;
BEGIN
-- alu behavior statements
END BLOCK ALU;

REG8 : BLOCK
SIGNAL zbus : tw32;
BEGIN
REG1: BLOCK
20
 SIGNAL qbus : tw32;
BEGIN
- reg1 behavioral statement
END BLOCK REG8;
END cpu_blk;

21
Guarded Blocks
Block statements have another interesting behavior
known as guarded blocks. A guarded block contains
a guard expression that can enable and disable
drivers inside the block. The guard expression is a
boolean expression: when true, drivers contained in
the block are enabled, and when false, the drivers
are disabled.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY latch IS
PORT( d, clk : IN std_logic;
q, qb : OUT std_logic);
END latch;
d 1 q=0
ARCHITECTURE latch_guard OF latch IS
CLK =0 qb=1
BEGIN
G1 : BLOCK( clk = ‘1’)
BEGIN
q <= GUARDED d AFTER 5 ns;
qb <= GUARDED NOT(d) AFTER 7 ns;
END BLOCK G1;
END latch_guard;
22
Process Statement
The process statement that contains only sequential
statements. The process statement is itself a
concurrent statement. A process statement can
exist in an architecture and define regions in the
architecture where all statements are sequential.
A process statement has a declaration section and a
statement part.
In the declaration section, types, variables,
constants, subprograms, and so on can be declared.
The statement part contains only sequential
statements.
Sequential statements consist of CASE statements,
IF THEN ELSE statements, LOOP statements, and so
on.
Sensitivity List
The process statement can have an explicit
sensitivity list. This list defines the signals that cause
the statements inside the process statement to
execute whenever one or more elements of the list
change value. The sensitivity list is a list of the
signals that will cause the process to execute.

23
ARCHITECTURE nand2 OF nand2 IS
BEGIN
PROCESS (a, b )
VARIABLE temp: std_logic;
BEGIN
temp:= NOT (a and b);
IF (temp = ‘1’) THEN c <= temp AFTER 6 ns;
ELSIF (temp = ‘0’) THEN c <= temp AFTER 5 ns;
ELSE c <= temp AFTER 6 ns;
END IF;
END PROCESS; END nand2;

Signal Assignment Versus Variable Assignment

Signals received values that were scheduled either
after an amount of time or after a delta delay.
q <= GUARDED d AFTER 5 ns;
A variable assignment happens immediately when
the statement is executed.
temp:= NOT (a and b);

Sequential Statements
Sequential statements exist inside the boundaries of
a process statement as well as in subprograms.
IF ■ CASE ■ LOOP ■ EXIT ■ ASSERT ■ WAIT
24
IF condition THEN
sequence_of_statements
{ELSIF condition THEN
sequence_of_statements}
[ELSE
sequence_of_statements]
END IF;

The first example shows how to write a simple IF

statement:
IF (x < 10) THEN
a := b;
END IF;
IF (day = sunday) THEN
weekend := TRUE;
ELSIF (day = saturday) THEN
weekend := TRUE;
ELSE
weekday := TRUE;
END IF;

25
The CASE statement is used whenever a single
expression value can be used to select between a
number of actions.
CASE expression IS
{case_statement_alternative}
END CASE
TYPE vectype IS ARRAY(0 TO 1) OF BIT;
VARIABLE bit_vec : vectype;
..
CASE bit_vec IS
WHEN “00” => RETURN 0;
WHEN “01” => RETURN 1;
WHEN “10” => RETURN 2;
WHEN “11” => RETURN 3;
END CASE;

The LOOP statement is used whenever an operation

needs to be repeated
[LOOP_label : ] [iteration_scheme] LOOP
sequence_of_statements
END LOOP[LOOP_label];
WHILE (day = weekday) LOOP
day := get_next_day(day);
26
END LOOP;
NEXT Statement
There are cases when it is necessary to stop
executing the statements in the loop for this
iteration and go to the next iteration.

EXIT Statement
During the execution of a LOOP statement, it may
be necessary to jump out of the loop.

Object Types
A VHDL object consists of one of the following:
■ Signal, which represents interconnection wires
that connect component instantiation ports
together. a <= b
■ Variable, which is used for local storage of
temporary data, visible only inside a process. I:=a,10
■ Constant, which names specific values

27
 - Signal objects are used to connect entities
together to form models.
- Signals are the means for communication of
dynamic data between entities.
SIGNAL signal_name: signal_type [:= initial_value];
For example;
- Signals can be declared in entity declaration
sections, architecture declarations, and package
declarations.
- Signals in package declarations are also referred
to as global signals because they can be shared
among entities. Following is an example
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
PACKAGE sigdecl IS
TYPE bus_type IS ARRAY(0 to 7) OF std_logic;
SIGNAL vcc : std_logic := ‘1’;
SIGNAL ground : std_logic := ‘0’;
FUNCTION magic_function( a : IN bus_type)
RETURN bus_type;
END sigdecl;

28
 Variables
Variables are used for local storage in process
statements and subprograms.
A variable declaration looks like this:
VARIABLE variable_name {,variable_name} :
variable_type[:= value];
The keyword VARIABLE is followed by one or
more variable names.
Each name creates a new variable.
The construct variable_type defines the data
type of the variable, and an optional initial
value can be specified
For example
ARCHITECTURE and5 OF and5 IS
BEGIN PROCESS(a, b, c, d, e)
VARIABLE state : std_logic;
VARIABLE delay : time
Constants
Constant objects are names assigned to specific
values of a type.
Constants give the designer the ability to have a
better-documented model, and a model that is easy
to update.
A constant declaration looks like this:
29
CONSTANT constant_name {,constant_name} :
type_name[:= value];
CONSTANT PI: REAL := 3.1414;

Data types
Type declarations are allowed in package
declaration sections, entity declaration sections,
architecture declaration sections, subprogram
declaration sections, and process declaration
sections.
A type declaration looks like this:
TYPE type_name IS type_mark;
A type_mark construct encompasses a wide range
of methods for specifying a type

30
An example of an enumerated type is shown here:
TYPE color IS ( red, yellow, blue, green, orange );
- In this example, the type values are very
abstract—that is, not representing physical
values that a signal might attain. The type
values in type color are also all identifiers.
- Each identifier in the type has a specific position
in the type, determined by the order in which
the identifier appears in the type. The first
identifier has a position number of 0, the next a
position number of 1, and so on.
31
PHYSICAL TYPES Physical types are used to
represent physical quantities such as distance,
current, time, and so on.
TYPE current IS RANGE 0 to 1000000000
UNITS
na; --nano amps
ua = 1000 na; --micro amps
ma = 1000 ua; --milli amps
a = 1000 ma; --amps
END UNITS;
Composite types consist of array and record
types.
- Array types are groups of elements of the same
type,
- Record types allow the grouping of elements of
different types.
- Arrays are useful for modeling linear structures
such as RAMs and ROMs,
- Records are useful for modeling data packets,
instructions, and so on.
The following example shows a type declaration
for a single dimensional array of bits:
TYPE data_bus IS ARRAY(0 TO 31) OF BIT;

32
This declaration declares a data type called
data_bus that is an array of 32 bits.
Following is an example of a record type
declaration:
TYPE optype IS ( add, sub, mpy, div, jmp);
TYPE instruction IS
RECORD
opcode : optype;
src : INTEGER;
dst : INTEGER;
END RECORD;
The first line declares the enumerated type
optype, which is used as one of the record field
types. The second line starts the declaration of
the record. The record type declaration begins
with the keyword RECORD and ends with the
clause END RECORD. All of the declarations
between these two keywords are field
declarations for the record. Each field of the
record represents a unique storage.
Subprograms
Subprograms consist of procedures and
functions.

33
- A procedure can return more than one
argument;
- A function always returns just one.
- In a function, all parameters are input
parameters;
- A procedure can have input parameters, output
parameters, and inout parameters.
- There are two versions of procedures and
functions: a concurrent procedure and
concurrent function, and a sequential
procedure and sequential function.
- The concurrent procedure and function exist
outside of a process statement or another
subprogram;
- The sequential function and procedure exist
only in a process statement or another
subprogram statement.
All statements inside of a subprogram are
sequential.
A procedure exists as a separate statement in
an architecture or process;
A function is usually used in an assignment
statement or expression.

34
Packages
The primary purpose of a package is to
encapsulate elements that can be shared
(globally) among two or more design units. A
package is a common storage area used to hold
data to be shared among a number of entities.

35