CO QUESTION BANK ANSWERS

UNIT - I
Short answer Questions :-
1. Differentiate multiprocessors and multicomputer

2. What is fetch cycle and execution cycle?

 3. List various types of computer with example

4. What is processor clock ?

A processor clock in computer organization refers to the timing signal that regulates the
speed at which a processor executes instructions. It determines how many clock cycles
per second the processor can perform, typically measured in gigahertz (GHz). The faster
the clock, the more operations the processor can complete in a given time.

5. Write about performance equation of the processor

The performance equation of a processor is defined as:

CPU Time = Instruction Count × CPI × Clock Cycle Time,

where CPI is the average cycles per instruction.

6. What are Big endian and little endian formats ?

• Big Endian and Little Endian are methods of storing multi-byte data.
 • In Big Endian, the most significant byte (MSB) is stored first (at the lowest memory
address).
• In Little Endian, the least significant byte (LSB) is stored first. These formats are
used to determine the order in which bytes are arranged in memory.

7. List different Types of Instructions used in Computer

Organization with an example.

8. Explain Instruction Cycle with the help of a flowchart.

9. What is the purpose of addressing modes ?

• The purpose of addressing modes is to specify the location of operands for

instructions in a program, allowing for flexible data access.
• They help in determining how the CPU interprets the addresses of the data in
memory during instruction execution.

10. Explain general register organization?

• General register organization refers to a CPU architecture where multiple
registers are available for data storage and manipulation, allowing for efficient
instruction execution.
• It enhances processing speed by reducing the need to access slower main
memory frequently.

11. What is the purpose of conditional codes?

Condition codes, or flags, are special bits set by the CPU after operations to indicate the
result of arithmetic or logic operations. They are used for decision-making in program
control. Common flags include:

• Zero Flag (Z): Set if the result is zero.

• Carry Flag (C): Set if there's a carry out from the most significant bit.
• Overflow Flag (O): Set if the result exceeds the allowed range in signed
arithmetic.

12. What is a subroutine?

• A subroutine in Computer Organization is a reusable block of code that

performs a specific task.
• It can be called from different parts of a program, helping to avoid code
repetition.
 • Subroutines often use a stack to store return addresses and local variables.

13. Differentiate rotate and shift operations.

Long answer Questions :-

1. Draw and explain Block Diagram of Digital Computers.
 • Input Unit: This unit is responsible for receiving data and instructions from external
sources (like keyboards, mice, or scanners) and converting them into a form that
the computer can process.
• Central Processing Unit (CPU): The CPU is the brain of the computer that
processes instructions. It consists of:
• Control Unit (CU): Manages and coordinates the activities of all other units in the
computer, directing the flow of data and instructions.
• Arithmetic Logic Unit (ALU): Performs all arithmetic (addition, subtraction) and
logical (AND, OR, NOT) operations.
• Memory Unit: This unit stores data and instructions temporarily or permanently. It
includes both volatile memory (like RAM) for temporary storage and non-volatile
memory (like ROM or hard drives) for permanent storage.
• Output Unit: Responsible for delivering processed data to the user in a readable
form, such as displaying on a monitor, printing on paper, or generating audio
signals.

2. Explain generations of computers

1st Generation (1940-1956) :

Technology : Vacuum tubes.

Characteristics : Large and cumbersome; primarily used for scientific and military
applications; limited programming capabilities.

Examples : ENIAC, UNIVAC.

2nd Generation (1956-1963)

Technology: Transistors.

Characteristics : Smaller and faster; more reliable and energy-efficient; introduced

higher-level programming languages.

Examples: IBM 1401, PDP-8.

3rd Generation (1964-1971)

Technology: Integrated circuits (ICs).

Characteristics: Increased circuit density; improved speed and reliability; rise of

operating systems.

Examples: IBM System/360, DEC PDP-11.

4th Generation (1971-Present)

Technology: Microprocessors.

Characteristics: Marked the advent of personal computers; significant advancements in

software and user interfaces; made computing accessible to the public.

Examples: Intel 4004, Apple Macintosh, IBM PC.

5th Generation (Present and Beyond)

Technology: Artificial intelligence and quantum computing.

Characteristics: Focus on intelligent behavior; aims for natural language processing and
machine learning; exploring quantum computing for complex problem-solving.

Examples: IBM Watson, Google Quantum AI.

3. Explain various types of Buses.

1. Data Bus

• Function: Transfers actual data between the CPU, memory, and input/output
devices.
• Characteristics: The width of the data bus (e.g., 8, 16, 32, or 64 bits) affects the
data transfer rate.
• Additional Points: Higher data bus width allows for faster data transfer; it operates
in parallel to increase throughput.

2. Control Bus

• Function: Carries control signals from the CPU to other components, managing
operations and timing of data transfers.
• Characteristics: Includes signals for read/write operations, interrupts, and other
status signals.
• Additional Points: Synchronizes actions across different components; it is
essential for coordinating data flow and maintaining system integrity.
3. Address Bus

• Function: Carries the addresses of data so that the CPU can communicate with
memory and other devices.
• Characteristics: The width of the address bus determines the maximum
addressing capacity (e.g., a 32-bit address bus can address up to 4 GB of memory).
• Additional Points: It operates unidirectionally, carrying addresses from the CPU to
memory; it influences the overall capacity of the system’s memory architecture.

4. Explain Registers of basic computer.

Registers are small, high-speed storage locations within a CPU that hold temporary data
and instructions during processing. Here’s an overview of the key types of registers in a
basic computer:

1. Accumulator Register (AC)

• Function: Stores intermediate results of arithmetic and logic operations

performed by the ALU (Arithmetic Logic Unit).
• Characteristics: Frequently used for calculations; the output from the ALU is
often stored here before being sent to memory.

2. Program Counter (PC)

• Function: Holds the address of the next instruction to be executed in the

program.
• Characteristics: Automatically increments after fetching an instruction, ensuring
the CPU processes instructions sequentially.

3. Instruction Register (IR)

• Function: Holds the current instruction being executed.

• Characteristics: After fetching an instruction from memory, it is stored here for
decoding and execution.

4. Memory Address Register (MAR)

• Function: Contains the address of the memory location to be accessed for

reading or writing data.
 • Characteristics: Works closely with the memory unit; it helps in fetching
instructions and data from the specified address.

5. Memory Data Register (MDR)

• Function: Temporarily holds the data being transferred to or from memory.

• Characteristics: It acts as a buffer between the CPU and memory, ensuring that
data is accurately written to or read from the memory.

6. Status Register (or Flag Register)

• Function: Stores flags that indicate the status of the CPU and the outcome of
operations (e.g., zero, carry, overflow).
• Characteristics: These flags help in decision-making during conditional
operations and control flow.

7. General Purpose Registers

• Function: Can be used for various purposes, such as holding temporary data,
addresses, or results.
• Characteristics: Typically more than one, allowing flexibility in operations;
commonly used in programming for variable storage.

5. Discuss the functions of system software.

System software is essential for managing hardware and providing a platform for
application software. Here are the primary functions of system software:

1. Operating System Management

• Function: Acts as an intermediary between users and hardware, managing

system resources and providing a user interface.
• Characteristics: Controls input/output operations, manages memory, and
handles file systems.
2. Hardware Control

• Function: Facilitates communication between the operating system and

hardware components (such as CPU, memory, and peripherals).
• Characteristics: Device drivers are part of system software, enabling the OS to
control hardware devices effectively.

3. Resource Allocation

• Function: Manages system resources, including CPU time, memory space, and
I/O devices, to ensure efficient utilization.
• Characteristics: Implements scheduling algorithms to optimize performance and
maintain system stability.

4. File Management

• Function: Provides a framework for creating, storing, organizing, and accessing

files on storage devices.
• Characteristics: Manages file permissions and ensures data integrity through
access control mechanisms.

5. Security and Access Control

• Function: Protects the system against unauthorized access and data breaches.
• Characteristics: Implements user authentication, encryption, and other security
measures to safeguard data.

6. Error Detection and Handling

• Function: Monitors the system for errors and manages recovery processes when
failures occur.
• Characteristics: Provides debugging tools and logs for diagnosing issues and
improving system reliability.

7. System Utilities

• Function: Includes various programs that perform maintenance tasks, such as

disk management, performance monitoring, and data backup.
• Characteristics: These utilities enhance system functionality and user experience
by optimizing performance and simplifying tasks.
8. Interfacing with Application Software

• Function: Provides an environment for running application software by managing

system resources and facilitating communication.
• Characteristics: Ensures compatibility and efficient operation of applications
across different hardware configurations.

6. Give characteristics of RISC and CISC.

7. Describe various addressing modes of the instruction used during

program execution.

Immediate Addressing Mode:

• The operand is specified directly in the instruction.
• Example: MOV R1, #10 (Move the immediate value 10 to register R1).
 Register Addressing Mode:
• The operand is located in a register, and the register address is specified in the
instruction.
• Example: MOV R1, R2 (Move the contents of R2 to R1).

Direct Addressing Mode:

• The memory address of the operand is given directly in the instruction.
• Example: MOV R1, [1000] (Move the value from memory address 1000 to R1).

Indirect Addressing Mode:

• The effective address of the operand is held in a register or memory location, and
the instruction refers to this register or location.
• Example: MOV R1, [R2] (Move the value from the memory location pointed to
by R2 to R1).

Indexed Addressing Mode:

• The effective address of the operand is obtained by adding an index value to a
base address stored in a register.
• Example: MOV R1, [R2 + #4] (Move the value from the memory location at R2
plus an offset of 4 to R1).

Base-Register Addressing Mode:

• The operand's address is determined by adding a base register value to an
offset.
• Example: MOV R1, [Base + Offset] (Move the value from the memory
location calculated by adding the base register and offset).

Relative Addressing Mode:

• The effective address is determined by adding the current program counter (PC)
value to an offset value.
• Example: JMP [PC + #5] (Jump to the address that is 5 units away from the
current PC value).

Auto-increment/Auto-decrement Addressing Mode:

• The operand is accessed from a register, which is then automatically
incremented or decremented after the operation.
 • Example: MOV R1, [R2]+ (Move the value from the memory location at R2 to R1,
then increment R2).

8. Illustrate the following arithmetic expression using three and two

address instructions.

X= (A+B) * (C+D).

9. Find the suitable addressing mode type for the below instructions. i)
MOV R #20 ii) CMA iii) ADD X iv) ADD 10 v) ADD AL,[0302] vi)Add R1, (R2)+
vii) Add R1,-(R2)

A) MOV R, #20
 • Addressing Mode: Immediate Addressing
• Reason: The operand 20 is provided directly in the instruction.

B) CMA

• Addressing Mode: Implicit Addressing

• Reason: The operand is implied (CMA typically complements the accumulator, and
the accumulator is implied by the instruction).

C) ADD X

• Addressing Mode: Direct Addressing

• Reason: The address of X is explicitly specified, and the value at that memory
address is used.

D) ADD 10

• Addressing Mode: Immediate Addressing

• Reason: The constant 10 is given directly in the instruction as the operand.

E) ADD AL, [0302]

• Addressing Mode: Direct Addressing

• Reason: The instruction adds the value from memory location 0302 to the register
AL.

F) ADD R1, (R2)+

• Addressing Mode: Auto-increment Addressing

• Reason: The contents of the memory location pointed to by R2 are used, and R2 is
incremented automatically after the operation.

G) ADD R1, -(R2)

• Addressing Mode: Auto-decrement Addressing

 • Reason: The register R2 is decremented first, and then the operand is fetched from
the new address.

10. How Stack is organized in computer? Explain?

1. Structure: A stack is a LIFO (Last In, First Out) data structure that stores data in a
linear format.
2. Memory Layout: Organized in a dedicated memory section called the stack
segment, with a stack pointer (SP) indicating the top.
3. Push Operation: Pushing a value decreases the stack pointer and stores the
value at the new top of the stack.
4. Pop Operation: Popping retrieves the top value and increases the stack pointer to
point to the next element.
5. Function Calls: The stack manages function calls by pushing the return address
and local variables onto it.
6. Stack Frame: Each function call creates a stack frame for its own return address
and local data, isolated from other functions.
7. Overflow and Underflow: Stack overflow occurs with excessive data, while
underflow happens when popping from an empty stack.
8. Uses: Stacks are essential for function calls, recursion, interrupt handling, and
expression evaluation in programs.

UNIT – II

Short answer Questions :-

1. Define the following
i) Micro Operation

A micro operation is the smallest unit of work performed on data in registers during a
machine cycle.

ii) Microinstruction

A microinstruction directs the control unit to execute specific micro operations with
associated control signals.

iii) Micro Routine

A micro routine is a sequence of microinstructions that perform a specific task or

operation.

iv) Control Word

A control word is a binary code that specifies the operations for the control unit during
microinstruction execution.

v) Control Store

A control store is a memory unit that holds microinstructions or control words for the
control unit’s operations.

2. How does the conditional branching supported by micro program

control organization.
• In microprogrammed control, conditional branching is supported by checking
specific condition flags or status bits during execution.

• Based on the condition (like zero, carry, or overflow), the microprogram counter
is updated to branch to a different microinstruction address.

• This enables dynamic decision-making within the control unit.

3. How micro programme sequencing is implemented in micro
programmed control

4. What is the use of WMFC?

• MFC (Write Microcode from Control) is used in microprogrammed control
systems to facilitate the writing of microinstructions into the control store.
• It allows for updating and modifying the microcode dynamically during system
operation or development.

5. Draw the input and output gating for the registers

6. Write the control sequence for register transfer operation
Long answer Questions :-
1. Describe the Single-bus Organization of the data path inside a
processor with a neat diagram?

• MDR has 2 inputs and 2 outputs. Data may be loaded

→ into MDR either from memory-bus (external) or

→ from processor-bus (internal).

• MAR‟s input is connected to internal-bus, and

MAR‟s output is connected to external-bus.

• Instruction-decoder & control-unit is responsible for

→ issuing the signals that control the operation of all the units inside the processor.

• Registers R0 through R(n-1) are provided for general purpose use by programmer.

• Three registers Y, Z & TEMP are used by processor for temporary storage during
execution of some instructions.

MUX(Multiplexer) selects either

→ output of Y or

→ constant-value 4

This is provided as input A of ALU.

• B input of ALU is obtained directly from processor-bus.

• Data are transferred from one register to another, often passing through
ALU to perform arithmetic or logic operation.

2. Construct the control sequence (micro operations) for storing a

word in Memory.
• Fetch the Word from Register
• Activate Input Gate of Register: Enable the output of the source register (e.g., Reg
A) to place data onto the data bus.
• Place Data on Bus: The word to be stored is placed onto the data bus.
• Set Memory Address
• Load Memory Address: Place the address where the word should be stored onto
the address bus.
• Activate Address Bus: Enable the address bus to send the memory address to the
memory unit.
• Memory Write Operation
• Enable Memory Write Signal: Activate the write control signal to indicate that data
should be written to the specified memory address.
• Data Transfer to Memory: The data present on the data bus is written into the
specified memory location.
 • Disable Write Operation
• Deactivate Memory Write Signal: Disable the write control signal to complete the
operation and secure the data in memory.

3. Construct the control sequence (micro operations) for reading a

word in Memory.
• Set Memory Address :-
• Load Memory Address: Place the address of the word to be read onto the address
bus.
• Activate Address Bus: Enable the address bus to send the memory address to the
memory unit.
• Memory Read Operation:-
• Enable Memory Read Signal: Activate the read control signal to indicate that data
should be read from the specified memory address.
• Data Transfer from Memory to Bus:-
• Place Data on Bus: The data from the specified memory location is placed onto the
data bus.
• Fetch Data into Register:-
• Activate Input Gate of Destination Register: Enable the input gate of the
destination register (e.g., Reg A) to capture the data from the bus.
• Transfer Data from Bus to Register: The data present on the bus is transferred into
the destination register.
• Disable Read Operation:-
• Deactivate Memory Read Signal: Disable the read control signal to complete the
operation.

4. Explain the multiple bus Organization of the Data path with the
help of a neat diagram?
Explanation :-

• All general-purpose registers are combined into a single block called the register file.

• Register-file has 3 ports. There are 2 outputs allowing the contents of 2 different registers
to be simultaneously placed on the buses A and B.

• Register-file has 3 ports.

• Buses A and B are used to transfer source-operands to A & B inputs of ALU.

• Result is transferred to destination over bus C.

• Incrementer-unit is used to increment PC by 4.

• Control sequence for the instruction Add R4,R5,R6

5. Show the connection and control signals for register MDR with a
diagram.
The Memory Data Register (MDR) serves as a critical buffer in the data path of a CPU,
connecting memory with various components.

Control Signals for MDR:

• Read Control Signal

• Write Control Signal
• Input Control Signal
• Output Control Signal
Connection Titles:

• Memory Data Register (MDR)

• Control Unit
• Data Bus
• Registers (e.g., Reg A, Reg B)
• Memory
• ALU

6. Discuss the Hardwired Control Unit Organization with a neat

diagram.

• Function: Generates control outputs based on input signals.

• Step-Decoder: Has separate signal lines for each control sequence step.
• Instruction Decoder: Activates one output line for the instruction in the IR.
• Control Signals: Generates signals like Yin, PCout, Add, and End.
• Signal Assertion:
• Zin asserted during T1 for all instructions, T6 for Add, and T4 for unconditional
branch.
• Counter Operation:
 • RUN = 1: Counter increments; RUN = 0: Counter stops.
• Hardwired Control: Operation sequence defined by logic wiring.
• Advantages: High-speed operation.
• Disadvantages: Limited flexibility.

7. Discuss the Micro programmed Control Unit Organization with a

neat diagram.

• Control Signals: Generated by a program similar to machine language programs.

• Control Word (CW): Represents control signals (e.g., Add, End, Zin) using individual
bits.
• Microinstructions: Individual control words in a microroutine.
• Microroutine: A sequence of CWs corresponding to the control sequence of a
machine instruction.
• Control Store (CS): Stores microroutines for all instructions in the instruction set.
• Control Unit: Generates control signals by reading CWs from CS sequentially.
• Microprogram Counter (μPC): Reads CWs sequentially from CS.
• Starting Address Generator: Loads the μPC with the starting address when a new
instruction is in the IR.
• Clock Increment: μPC is incremented by the clock to read successive
microinstructions, delivering control signals in the correct sequence.

8. List the control sequence (micro operations) for execution of the

instruction Add (R3), R1
 • Activate Input Gate of R3
• Activate Memory Read Signal
• Transfer Data to MDR
• Activate Input Gate of MDR
• Load Data into ALU
• Activate Input Gate of R1
• Activate ALU Add Operation
• Transfer Result from ALU to R1

9. List the control sequence (micro operations) for execution of the

instruction Move (R s ), R d

• Activate Input Gate of R_s

• Activate Input Gate of MDR
• Transfer Data to MDR
• Activate Input Gate of R_d
• Transfer Data from MDR to R_d

10. Describe the block diagram of a complete processor.

• Separate Processing Units: Distinct units for handling integer and floating-point
data.
• Data Cache: Positioned between processing units and main memory for efficiency.
• Instruction Fetching:
• Instructions are fetched from an instruction cache.
• If not available in cache, they are fetched from main memory.
• Bus Interface: Connects the processor to the system bus and the rest of the
computer.
• Separate Caches: Using distinct caches for instructions and data is common in
modern processors.
• Concurrent Operations: Processors may include multiple units of each type to
enhance concurrency.
11. Distinguish Hardwired control and Micro programmed control.

Note :- Summarize the answer 6 & 8 given above.

UNIT - III
Short answer Questions :-
1) What is shared data and control lines memory mapped I/O?
• Memory-mapped I/O shares the same address space for both memory and I/O
devices.
• Data and control lines are shared between memory and I/O operations.
• The CPU can access I/O devices using standard memory instructions.
• This design simplifies the system by avoiding the need for a separate I/O bus

2) What are the functions of I/O module?

• Control and timing
• Processor communication
• Device communication
• Data buffering
• Error detection
3) What are the different I/O techniques?
• Programmed I/O
• Interrupt-driven I/O
• Direct Memory Access (DMA)

4) What is programmed I/O?

Programmed input/output (PIO) is a method of transferring data between a

computer's central processing unit (CPU) and a peripheral device, such as a
storage device

5) What is interrupt driven I/O?

• Interrupt-driven I/O is a technique where the I/O device signals the processor
via an interrupt when it is ready for data transfer, rather than the processor
continuously polling the device.
• This allows the processor to perform other tasks while waiting for the I/O device
to be ready, improving efficiency by reducing idle time

6) Define Vectored Interrupt.

 A vectored interrupt is a type of interrupt where the interrupting device sends a
unique code, called an interrupt vector, to the processor.

7) What is Interrupt Latency?

Interrupt latency is the delay between the time an interrupt request is generated by
a device and the moment the processor begins executing the interrupt service
routine (ISR) to handle that interrupt.

8) Interpret the difference between an Interrupt Service

Routine and a Subroutine?

9) What is Exception?
An exception is an event that disrupts the normal flow of program execution, typically
caused by errors or special conditions, triggering a transfer of control to an exception
handling routine.

Long answer Questions :-

1) Differentiate isolated IO and memory mapped I/O?
2) What is the need of I/O interface module? Explain.
• Data Format Conversion: It converts data between different formats used by the
CPU and I/O devices, ensuring compatibility.
• Signal Conditioning: The interface manages electrical characteristics of signals
(e.g., voltage levels) to match the requirements of both the CPU and peripheral
devices.
• Control and Timing Management: It generates control signals and timing for data
transfers, coordinating communication between the CPU and I/O devices.
• Buffering: The interface provides temporary storage (buffers) to handle differences
in data transfer rates between the CPU and I/O devices, preventing data loss.
• Error Detection and Handling: It includes mechanisms to detect and handle errors
during data transmission, enhancing system reliability and performance.

3) Write about Vectored interrupts and interrupt Nesting.

4) What is priority interrupt? Explain the Daisy Chaining priority
with neat diagram
Priority interrupt: It is a method used in interrupt handling where multiple devices can
send interrupt requests, and the CPU services them based on their assigned priority levels.
Higher priority interrupts can preempt lower priority ones, ensuring critical tasks are
handled promptly.

Daisy Chaining Priority

In daisy chaining, devices are connected in a series, and the interrupt request line is
shared. When an interrupt occurs, the CPU polls the devices in order of their connection.

• D1 has the highest priority; if it raises an interrupt, it gets serviced first.

• If D1 does not need servicing, the interrupt request is passed to D2.
• This continues until a device that requires service is found.

5) Explain how to access I/O devices in a system

• Address Assignment: Each I/O device is assigned a unique address within the
system’s address space, enabling identification during access.
• Control Signals: The CPU sends control signals to specify the type of operation
(read or write) for the intended I/O device.
• Data Transfer Mechanism: Depending on the system architecture, data transfer
can occur via programmed I/O, interrupt-driven I/O, or Direct Memory Access
(DMA).
• Polling or Interrupts: The CPU can either poll the device status to check readiness
or rely on interrupts to respond when the device is ready for data transfer.
• Memory-Mapped I/O or Isolated I/O: The system can use either memory-mapped
I/O, where I/O devices share the memory address space, or isolated I/O, where a
separate address space is used.
• Buffering: Data may be buffered in temporary storage to accommodate differences
in processing speed between the CPU and the I/O device.
• Error Handling: The system should include mechanisms to detect and handle
errors that may occur during I/O operations to ensure reliability and correctness.