by Stephen A.

Edwards

Retrocomputing on an FPGA
Reconstructing an 80’s-Era Home Computer with Programmable Logic
The author reconstructs a computer of his childhood, an Apple II+.

As a Christmas present to myself in MOS Technology (it sold for $25 when
an Intel 8080 sold for $179). The 6502
2007, I implemented an 1980s-era Apple
II+ in VHDL to run on an Altera DE2 had an eight-bit data bus and a 64K
FPGA board. The point, aside from address space. In the Apple II+, the 6502
entertainment, was to illustrate the power ran at slightly above 1 MHz. Aside from
(or rather, low power) of modern FPGAs. the ROMs and DRAMs, the rest of the
Put another way, what made Steve Jobs circuitry consisted of discrete LS TTL
his first million could be a class project chips (Photo 2).
for the embedded systems class I teach at While the first Apple IIs shipped with
Columbia University. 4K of DRAM, this quickly grew to a
More seriously, this project standard of 48K. DRAMs, at this time,
demonstrates how legacy digital were cutting-edge technology. While they
electronics can be preserved and required periodic refresh and three power
integrated with modern systems. While I supplies, their six-times higher density
didn’t have an Apple II+ playing an made them worthwhile.
important role in a system, many Along with with an integrated
embedded systems last far longer than keyboard, a rudimentary (one-bit) sound
their technology. The space shuttle port, and a game port that could sense
immediately comes to mind; PDP-8s can buttons and potentiometers (e.g., in a
be found running some signs for San joystick), the main feature of an
Francisco’s BART system. Apple II+ was its integrated video
display. It generated composite
What is an Apple II+?
(baseband) NTSC video that was usually
The Apple II+ (Photo 1) was one of the sent through an RF modulator to appear
first really successful personal computers. on TV channel 3 or 4.
Designed by Steve Wozniak (“Woz”) and The Apple II+ had three video modes:
introduced in 1977 [1, 2, 4], it really took a 40 × 24 uppercase-only Photo 2: The Apple II+ Motherboard. Ex-
off in 1978 when the 140K Disk II black-and-white text display, a 40 × 48 pansion slots and analog video circuity
5.25-inch floppy drive was introduced, 16-color low-resolution display, and a dominate the top; the 6502 is above the
followed by VisiCalc, the first 140 × 280 6-color high-resolution six large ROM chips. The white rectan-
spreadsheet. display. The Apple II+ can almost be gle encloses 48K of DRAM. The charac-
Fairly simple even by the standards of thought of as a video controller that ter ROM is at the bottom; the rest is TTL.
the day, the Apple II was built around the happens to have a microprocessor
inexpensive 8-bit 6502 processor from connected to it. Woz started with a
14.31818 MHz master clock—exactly
four times the 3.579545 MHz colorburst
frequency used in NTSC video—and
derived everything from it.
The CPU and video alternate accesses
to memory at 2 MHz. Another Woz trick:
the video addresses are such that
refreshing the video also suffices to
refresh the DRAMs, so no additional
refresh cycles are needed.
Figure 1 shows the block diagram of
my reconstruction. The 6502 processor
on the left generates addresses and output
Photo 1: An Apple II+ data. The address is fed to the ROMs, an Figure 1: Block Diagram
Figure 2: Woz’s clock generator circuit. A 14.31818 MHz crystal drives a 4-bit shift register and a quad flip-flop to generate DRAM
timing signals and the processor clocks, which in turn feed a bank of horizontal and vertical video counters.

address range decoder, the peripheral patent [5], which describes it and his trick ’153 driving it, which selects between
slots, and to a mux that selects between of using digital signals to generate color PRE PHI 0 and a combination of Q3 and
processor and video system addresses for NTSC video. PHI0 depending on the state of AX.
the main memory. Woz derived the CPU clock from the The third sequential process models
The original Apple II+ used a tri-state 14M clock by dividing by roughly the four 4-bit binary counters. In the
data bus, but FPGA cores do not support fourteen. “Roughly” because every original circuit, these were clocked by the
such complex electrical structures sixty-fifth CPU cycle (one per horizontal output of a NAND gate. Such a practice
(although they do provide tri-state I/O scan line) is stretched by two 14M clock is dangerous because the output of the
pins), so my reconstruction breaks the periods to preserve the phase of the 3.58 gate might glitch and cause unpredictable
data bus into multiple segments. Most MHz colorburst frequency. Thus, there behavior, so instead I chose to clock these
notably, I added a large mux (right side of are 65 * 14 + 2 = 912 pixel periods per counters at 14 MHz and instead carefully
Figure 1) that selects the source of data line, or exactly 228 cycles of the control when they count.
fed to the 6502 core, such as main 3.58 MHz colorburst per line. Figure 3 shows a timing diagram for
memory or the ROMS. While it would be possible to write a the clock generator illustrating how it
The Clock Generator model for each TTL part in VHDL and behaves at the end of a line. The
assemble them according to the COLOR DELAY N signal causes the
Figure 2 shows the Apple’s clock
schematic, I prefer to try to write the shift register to delay RAS N et al. two
generator circuit. A crystal oscillator
VHDL according to Woz’s intentions for extra 14M cycles, which also causes
drives the clocks on a ’195 quad shift
the original circuit. This is especially true PHI0 to be stretched. HCOUNT changes
register and a ’175 quad flip-flop. These
for combinational “glue” logic, which on the rising edge of LDPS N, just as in
generate clocks for the the DRAM (RAS’
was often implemented in nonintuitive the original circuit.
and CAS’) along with the “1 MHz”
ways to save parts. The values taken on by the horizontal
processor clocks PHI0 and PHI1. A gated
Listing 1 shows my VHDL code for the counter are a little unusual: the counter is
version of PHI0 feeds a bank of ’161s:
clock generator. It assumes the 14 MHz allowed to wrap around from 7F to 00,
four-bit binary counters configured to act
clock is provided externally and consists but is then set to 40 to start the line.
as horizontal and vertical counters
of three main sequential processes. The These 65 PHI0 periods turn into about
(H0–H5, VA–VC, and V0–V5) from
first models the ’195 shift register, which 15.70 kHz, close to the NTSC horizontal
which the video addresses are generated.
either shifts or loads dependings on its frequency of 15.734 kHz.
This clever circuit does a lot with few
own Q3 output. The second process
parts. It is at the center of Woz’s
models the ’175 quad flip-flop and the
61us 62us 63us 64us 65us
Time
CLK_14M
RAS_N
AX
cas_n
Q3

CLK_7M
COLOR_REF
PRE_PHI0
PHI0

LDPS_N
HPE_N
HCOUNT[6:0] 7E 7F 00 40 41
VCOUNT[8:0] 0FA 0FB
COLOR_DELAY_N

Figure 3: Behavior of the clock generator at the end of a line

-- To generate the once-a-line hiccup: D1 pin 6

The CPU and Memory COLOR_DELAY_N <=
not (not COLOR_REF and (not AX and not CAS_N) and PHI0 and not H(6));
Like Woz, I didn’t create a 6502
-- The DRAM signal generator
processor from scratch. Instead, I used a C2_74S195: process (CLK_14M)
6502 core written by Peter Wendrich for begin
if rising_edge(CLK_14M) then
his FPGA-based Commodore 64. The if Q3 = ’1’ then -- shift
main challenge here was making sure it (Q3, CAS_N, AX, RAS_N) <=
unsigned’(CAS_N, AX, RAS_N, ’0’);
was clocked properly given the odd way else -- load
the Apple II+ generates its occasionally (Q3, CAS_N, AX, RAS_N) <=
unsigned’(RAS_N, AX, COLOR_DELAY_N, AX);
stretched processor clock. end if;
Semiconductor memory has changed a end if;
end process;
lot since 1977. The Apple II+
used 24 4116 16-kilobit DRAM chips -- The main clock signal generator
B1_74S175 : process (CLK_14M)
with 150 ns access times to provide 48 begin
kilobytes of memory. Today, it is difficult if rising_edge(CLK_14M) then
COLOR_REF <= CLK_7M xor COLOR_REF;
to find memory chips this small. CLK_7M <= not CLK_7M;
While it would have been nice to place PHI0 <= PRE_PHI0;
if AX = ’1’ then
all of the Apple’s memory on the FPGA I PRE_PHI0 <= not (Q3 xor PHI0); -- B1 pin 10
was using, it (an Altera Cyclone II 2C35) end if;
end if;
has about 59K of on-chip RAM, which is end process;
just a little too small to fit 48K of RAM
LDPS_N <= not (PHI0 and not AX and not CAS_N);
plus 12K of ROMs. I chose instead to use LD194 <= not (PHI0 and not AX and not CAS_N and not CLK_7M);
off-chip SRAM (the DE2 has 512K) for
-- Four four-bit presettable binary counters
the 48K of main memory and store the -- Seven-bit horizontal counter counts 0, 40, 41, ..., 7F (65 states)
ROMs on-chip. Storing the ROMs in -- Nine-bit vertical counter counts $FA .. $1FF (262 states)
D11D12D13D14_74LS161 : process (CLK_14M)
FPGA memory is more convenient begin
because their contents are initialized if rising_edge(CLK_14M) then
-- True the cycle before the rising edge of LDPS_N: emulates
when the FPGA is programmed. -- the effects of using LDPS_N as the clock for the video counters
Asynchronous SRAM is much easier if (PHI0 and not AX and ((Q3 and RAS_N) or
(not Q3 and COLOR_DELAY_N))) = ’1’ then
to interface than DRAM. The only real if H(6) = ’0’ then H <= "1000000";
issue is generating an approriately timed else
H <= H + 1;
write enable signal and making sure the if H = "1111111" then
tri-state data pins are only driven when V <= V + 1;
if V = "111111111" then V <= "011111010"; end if;
the processor is writing to the RAM. end if;
The Video Generator end if;
end if;
The Apple II+ has three main video end if;

modes: a 40×24 uppercase-only text end process;

display, a 40×48 16-color “lores”
graphics mode, and a 280×192 6-color
Listing 1: VHDL for the timing generator
“hires” graphics mode. The graphics So to display an NTSC-rate image on a
modes also have a mixed mode in which VGA monitor, it is enough to display
the bottom four lines of text are displayed each NTSC line twice, which is
instead. convenient because it only requires
The memory layout for all three modes buffering a line instead of a whole frame.
is similar and non-linear. To Rather than redesign Woz’s carefully
accommodate 40-character text lines crafted video circuitry, I chose to place a
using only a single four-bit binary adder VGA line doubling circuit after his (a) (b)
and wasting little memory, Woz divided one-bit video output that both doubles the
the screen into three horizontal stripes, horizontal frequency and interprets color
each 64 scan lines high (equivalently, information.
eight character rows). Memory for each My circuit consists of a dual-ported
display mode is divided into 128-byte memory that stores two lines of the
segments that hold three 40-byte lines 14 MHz 1-bit video signal. At any time,
(i.e., the last eight bytes in each segment the circuit is filling in one line and (c) (d)
are not displayed). The first line in each displaying the other; the roles of the two
segment appears in the top stripe, the lines swap once every NTSC line. Figure 4: A hires graphics fragment inter-
second in the middle stripe, and the third The Color Decoder preted as (a) monochrome, (b) output from
in the bottom. The result is that bits 3 to 6 Interpreting colors is the bigger challenge the KEGS software emulator for the Ap-
of the video address are a funny sum of in converting the Apple II+ output to ple IIgs, (c) under a four-bit window al-
horizontal and vertical counter bits. color VGA signals. Unlike VGA, which gorithm, and (d) under the six-bit window
All three modes fetch one byte from conveys separate red, green, and blue algorithm used in my reconstruction.
video memory every PHI0 cycle. In text signals, composite (color) NTSC video
mode, the data is fed to the top six consists of three signals modulated
address bits of the character ROM and the four square wave signals that differ only
together. To a high-bandwidth luminance
output of the ROM is loaded into a ’166 in their phase. Thus, interpreting groups
(brightness only) signal (about 3 MHz)
eight-bit parallel-to-serial shift register. of four bits as one of sixteen colors
called Y, NTSC adds two
In lores mode, the byte is loaded into a produces a reasonable display, especially
lower-bandwidth color signals (“I” and
pair of four-bit recycling shift registers for solid regions.
“Q”) that are quadrature modulated at
and clocked out repeatedly. In hires Unfortunately, this four-bit-at-a-time
3.579545 MHz. A color television
mode, the byte is loaded into an eight-bit approach produces more color fringing
demodulates and combines linear ratios
shift register and clocked out. around the edges of white objects than a
of these signals to recover red, green, and
The VGA Line Doubler television would because of the
blue intensities.
bandwidth limits on I and Q, as shown in
The Apple II+ generates a composite The Apple II+ uses a trick to generate
Figure 4(c). My solution was to look at
color NTSC signal that was usually sent the modulated signal: it produces a digital
one bit to the left and right of the four-bit
through an RF modulator and displayed signal that switches at
window and generate color only when
on a standard television set. Since 14.31818 MHz—exactly four times the
these extra bits follow the same pattern as
computers have not used composite color colorburst frequency. Figure 4(a) depicts
the middle four. (Figure 4(d))
monitors since the early 1980s, one of my a small patch of this digital video output
Figure 5 shows an abstract view of my
goals was to generate an analog color interpreted as black and white pixels. The
color generator. At the top is a six-bit
VGA signal (now also obsolete) suitable sixteen different period-four waveforms
shift register that amounts to a sliding
for a standard computer LCD monitor. (i.e., whose fundamentals are at the
window into the video signal. Each bit
This presented two problems. The first 3.58 MHz colorburst frequency) each
consumes 90 degrees of phase; the circuit
is one of rate: the Apple II+ generates produce a different color (two produce
mostly considers the middle four bits.
composite color non-interlaced NTSC gray). All 0’s is black and all 1’s is white
The main color circuitry comprises a
video: 60 frames a second, 262 lines per since neither has any high-frequency
“permute” block that rotates the four
frame. This leads to a horizontal refresh information; the television interprets
(constant) basis colors depending on
rate of about 15.70 kHz. them as purely luminance. Other patterns
which of the four phases a pixel can be in
The VGA standard, which has been produce different levels of Y, I, and Q,
relative to the colorburst frequency. Then
around since 1987, is an analog RGB and thus different colors.
each of the four basis colors are ANDed
component format associated with a NTSC demodulation and YIQ-to-RGB
with the four middle bits of the sliding
variety of refresh rates, but the most colorspace conversion is a linear process,
window filter and added together to form
relevant here is essentially NTSC times albeit a time-varying one because
a 24-bit RGB value.
two: a 31 kHz horizontal sweep rate with quadrature modulation uses phase to
At the top right of Figure 5 are three
a 60 Hz frame rate. By design, this is two distinguish two signals. So the digital
gates that guess when we are in the
VGA lines for every NTSC line. video signal the Apple II+ produces can
middle of a solid color region. When
be though of as a linear combination of
 activating the stepper motor phases in
sequence. And although the hardware did
provide a facility for clock recovery and
framing, the software was presented with
just a raw stream of encoded bytes from
the disk.
Instead of the FM scheme used by the
Shugart controller, which placed a clock
pulse between every data pulse, the
Disk II used a group code recording
scheme that allowed up to two
consecutive 0’s before a 1 was mandatory,
making it possible to store six bits instead
of four in the space of eight transitions.
This improved formatted capacity to
140K per diskettee over the 90K possible
with FM encoding, but it fell to the
software to decode this data.
My Disk II emulator consists of an SPI
controller responsible for initializing and
reading data from the SD card, a bus
device that interprets and responds to the
6502 like the Disk II controller, and a
Figure 5: Abstract View of the Color Generator dual-ported RAM that holds a single
unformatted track’s worth of data. At
bits 0 and 4 in the filter are equal, and My goal was to make it possible for my 300 rpm at 4 µ s per bit, this is 50,000 bits
bits 1 and 5 are also equal, the “color reconstruction to boot images of 5.25” or 6250 bytes. However, the standard file
select” signal is true and the solid color floppy disks. Years ago I converted my format for Apple II raw disk images
value generated as described above is own collection of physical disks to such (“.nib”) uses 6656 bytes (26 × 256) per
selected as the color for this pixel. images; many more can be found on the track, so I chose to use that.
Otherwise, my circuit colors the pixel web. Thus, my goal was to make the The SA400 had a single read/write
black, gray, or white depending on how software think it was talking to a floppy head whose position over the floppy was
many bits are set in the middle two drive instead of attempting to reconstruct controlled by a stepper motor. My Disk II
positions in the shift register. This the drive and its controller exactly. controller observes how the software
approximates the effect of the lower I and The DE2 board has a SD/MMC card activates the four phases of the stepper
Q bandwidth: when the signal suddenly interface, which is just a connector with a motor and responds to each track change
changes from dark to light, the luminance few pins connected directly to the FPGA by reading a track’s worth of data into the
changes more quickly; the color and some pull-up resistors. This plus the track buffer. Once in the buffer, the
information changes slower. quickly falling prices of SD flash memory controller simply cycles through the track
It took some experimentation for me to cards made it the natural choice. data, emulating the movement of the head
arrive at this approximation. To evaluate My emulation circuit consists of two over the track.
the algorithms, I wrote a simple C parts: a module that emulates the The stepper motor has four phases, and
program that converted a memory dump behavior of the Disk II controller, which every two phases corresponds to a distinct
of a hires image into a PPM file, which I interprets CPU access to the relevant I/O track (of which there are 35), but because
then evaluated. Figure 4(d) is the output I addresses, and a SPI module that fetches the software is free to turn on two (or
finally implemented. blocks of data from an SD card based on more) phases simultaneously, my
The Disk II Emulator commands from the first module. controller models both when the head is
SD/MMC flash memory cards can be at a particular phase and when it is
Introduced about a year after the Apple II
operated in a variety of modes. The between two adjacent phases. It
itself, the Disk II 5.25” floppy disk drive
simplest is SPI, a simple, constantly monitors the state of the four
was another remarkably svelte piece of
well-documented, four-wire synchronous phases and updates the head position
hardware [2, 3]. The system consisted of
serial protocol. Furthermore, the wiring based on its current position. When it
a digital controller board connected to the
on the DE2 was clearly set up to operate observes a track change, it signals the SPI
peripheral bus, an analog board in the
SD cards in such a mode. controller to fetch the new track and
drive itself that handled things like
The Disk II presented an extremely transfer it into the track buffer.
controlling the stepper motor and
low-level interface to software. Head I added a rudimentary user interface
conditioning the read signal, and a bare
positioning was performed by directly for selecting different disk images: ten
Shugart SA400 drive mechanism.
switches supply the image number in Sound I brought out the CPU’s PC to four of
binary, which I displayed in hex on two of The Apple II+’s sound system is the seven-segment displays on the DE2
the seven-segment LEDs. On the SD simultaneously humorous and amazing: a and the drive’s current track on another
card, the images are laid out one after the speaker connected to a Darlington two. While the PC is usually changing so
other, i.e., not in a file system. To create transistor driven by a flip-flop configured fast it becomes a blur, patterns do often
such a collection, I wrote a script that to toggle when a particular I/O address is emerge. For example, the PC remains
finds all the .dsk files in a directory, accessed. The amazing part is that highly focused when the computer is
converts each to the “nibblized” format, programmers managed to drive such a waiting at the prompt. Similarly, I have
and adds it to an image file. All 500 of the trivial circuit to generate four-voice found a lot of software, including the
5.25′′ floppies I owned fit into 112 MB, synthesized sound and even speech. operating system when it is moving the
which now resides comfortably on a $5 Emulating the audio address decoding drive head, calls the monitor’s “delay”
SD card. How times have changed. and flip-flop was trivial; doing something routine to slow things down.
The PS/2 Keyboard Interface useful with the resulting signal was more Comparing Implementations
The Apple II plus had an integrated of a challenge. This project demonstrates how little
keyboard consisting of an array of The DE2 board includes a Wolfson power modern hardware consumes and
discrete keyswitches scanned by a MW8731 CODEC, a CD-quality stereo how much more efficient it can be than
General Instruments AY-5-3600 keyboard audio chip capable of driving an audio software. I compared the power
encoder that produced a seven-bit ASCII amplifier, complete overkill for Apple II+ consumed by an actual Apple II+ with
code. When a key was pressed, it would audio, but already there on the board. that consumed by my reconstruction as
latch the code and send a pulse that Using it presented two challenges: well as a software emulator running on
indicated a new key was pressed. The generating the appropriate set of signals ten-year-old x86-based Linux box. I used
Apple II would latch the pulse as bit 7 of to feed its serial interface and initializing an inexpensive “Kill A Watt” power
the keyboard I/O location and clear it its registers through an I2 C bus. meter, which only claims 0.2% accuracy,
when another I/O location was accessed, I implemented one module that but this was enough to demonstrate what
providing a simple handshake. generates the various square waves for the was going on.
Instead of directly connecting a codec’s clocks (a bit clock and a word or The results were dramatic. My real
keyswitch array to the FPGA, I decided to channel clock) and shifts out sixteen bits Apple II+ nominally consumed 22 watts,
employ one of the many PS/2-compatible of amplitude data. The main trick here which rose to 31 watts when the disk was
keyboards littering my office. This was was choosing the proper divider values rotating; my FPGA reconstruction only
especially attractive since the DE2 board and sending out each bit at the right time. consumed 5 watts, even with all its extra
board already had a PS/2 connector. The I2 C bus controller was more tricky. unused peripherals. The Dell
The PS/2 keyboard interface is a While I only needed to support a small Optiplex GXa (running a now-modest
simple but idiosyncratic synchronous part of the bus protocol, it still required 233 MHz Pentium II) consumed 62 watts
serial protocol that sends and receives three state machines: one to handle the when running the emulation software.
data a byte at a time. The usual message low-level details of clock and data bit
Project Files
is “make,” which indicates a particular generation, one to transmit single packets,
and one to prepare the proper sequence of Included with all the VHDL files are
key has been pressed. Other messages
packets to initialize the Wolfson chip’s project files for Altera’s Quartus
include “break” followed by a code for a
registers. software, a utility program for converting
key that has been released. Unfortunately,
the more common 140K .dsk files to the
the scan codes are not ASCII (perhaps The Top Level
.nib files my reconstruction uses.
reflecting the wiring of an early My reconstruction actually has two For copyright reasons, I did not include
keyboard) and use “extended codes” for “top-level” modules. The “apple2” a copy of the Apple ROMs. They are easy
keys such as the arrows, since they were module contains the timing generator, to obtain from an existing computer or
not on the original keyboard. video generator, processor, ROMs, from the Internet. I included the script I
My solution uses the free PS/2 address decoder, and various minor used to convert the binary files into
controller distributed by ALSE, which peripheral devices, i.e., all the original VHDL files that hold the same data.
speaks the low-level protocol and parts of the Apple II+. A second module But the project will function as it
performs the serial-to-parallel conversion, is the actual top level, consisting of the stands: I wrote a “fake BIOS” that clears
and a simple state machine that looks at “apple2” module along with the VGA the screen, displays some messages, then
the returned messages and interprets them line doubler, the PS/2 keyboard interface, cycles through a simple pair of graphics
as ASCII. The code is sloppy but works. Disk II emulator, audio components, a demos. I included the 6502 assembly
Because all of this was never part of the PLL that divides the DE2’s 50 MHz clock source, which I compiled with the xa65
Apple II, I was not concerned with being down to about 28 MHz (i.e., not exactly cross-assembler. My “BIOS” is not able
faithful to the original design, or even the right frequency, but close enough), to boot any Apple disks, however.
elegant. and connections for switches and LEDs
on the DE2 board.
A Slippery Slope
Like most projects, this one could
continue without end. Many important
features are still missing. Many Apple II
games used a joystick, but I have not
emulated it. The DE2 board has a USB
host controller, so in theory I could use a
standard USB joystick to it, but even a
USB controller chip still demands a
processor control it.
The disk emulation presents the most
opportunities for improvement. For
example, it is read-only, which is enough
for running plenty of software, but there
are plenty of reasons to want to write to a
disk. Also, my emulator uses an SD card
but does not support a filesystem. It
would be much easier to manage disk
images if they could be named and stored
in a standard hierarchical filesystem (e.g.,
FAT32). It might be possible to do this
with the 6502 processor, but a separate
processor for managing this might also be
in order. Along the same lines, my
emulator could also support the more
standard 140K disk images if it included
logic to perform the encoding used by
Apple DOS; most software emulators do
this.
There are myriad peripheral cards that
could also be emulated. The 16K
memory expansion card would be a first
step, but it would also be nice to have
others that provided serial ports, printers,
and improved sound.
Perhaps next Christmas I’ll have time.
References
[1] Winston Gayler. The Apple II Circuit
Description. Howard W. Sams &
Co., 1983.
[2] Jim Sather. Understanding the Apple
II. Quality Software, Reseda, CA,
1983.

[3] Don Worth and Pieter Lechner.

Beneath Apple DOS. Quality
Software, Reseda, CA, 1981.

[4] Stephen Wozniak. System

description: The Apple-II. Byte
Magazine, 2(5):34–43, May 1977.

[5] Stephen G. Wozniak. Microcomputer

for use with video display. US Patent
4,136,359, January 1979.