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B.M.S.College of Engineering, Bangalore-19: The Min Term Corresponding To Decimal Number 15 Is

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0% found this document useful (0 votes)
5 views

B.M.S.College of Engineering, Bangalore-19: The Min Term Corresponding To Decimal Number 15 Is

Uploaded by

manyam.ml23
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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B.M.S.

COLLEGE OF ENGINEERING,BANGALORE-19
(Autonomous Institute, Affiliated to VTU)
DEPARTMENT OF MEDICAL ELECTRONICS ENGINEERING
CONTINUOUS INTERNAL EVALUATION TEST -I
Course Code: 23ES3PCDEC Course Title: DIGITAL ELECTRONICS CIRCUITS
Maximum Marks: 40 Date: 4/1/2024
Semester: III

Faculty Handling the Course: Dr. Suma M.S. Time: 12noon to 1.15p.m
Instructions: Part Aand Part Bare compulsory. Internal choice is provided in Part C.

PART-A

Marks CO PO PSO
Q.No Question
-

2 1
'A' XNOR 1= ;A.not( A) =
1 1 1
lb The min term corresponding to decimal number 15 is
If one of the inputs of a 2-input EX OR gate is connected to 1, then 1 1 1 1
lc
it can be used as

1d In a four variable K map, all the cells logically adjacent to cell 1 1


14 are

PART-B

Q. No. Question Marks Co PO PSO


2 1
Convert the following Boolean function into minterm canonical form
2a
f(x,y,z) =x'(y'+z)+z'
5 2 1

2b
Simplify the given function using K-Map
f(a,b,c,d) Em(1,2,4,11,13,14,15)+d(0,5,7,8,10)
5 3 3
Design a combinational circuit whose output is equal to 1 if
2c the input variables have more 1'sthan 0's.The output is 0 otherwise.
Assumethe three variables asa,b,c.

PART- C
Q. No. Question MarksCO PO PSO
Simplify the following Boolean function using Quine McCluskey 10 2 2 1

method.
F(A,B,C,D) =Em(0,2,6,7,8,9,10) +d (3,5,15)
OR
3
Using Karnaugh maps, determine all the minimal sum and minimal
products for the incomplete Boolean function f where,
f(w,x,y,z)= Lm(0,1,3,7,8,12) +de(5,10,13,14)

10 3 1
Design a logic circuit with 3 inputs X,Y,Z which produce a '1' only
when two adjacent input variables are 1's .X and Z are also to be
4 treated as adjacent. Implement using universal logie.
OR
Realize a fulladder with inputs as a,b,c as per the design protocol.

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