Op Amp/Comparator

HIGHLIGHTS
This section of the manual contains the following major topics:

1.0 Introduction ....................................................................................................................... 2

2.0 Comparator Registers....................................................................................................... 5
3.0 Comparator Operation .................................................................................................... 17
4.0 Comparator Configuration............................................................................................... 18
5.0 Comparator Interrupts ..................................................................................................... 22
6.0 Op Amp Configuration .................................................................................................... 24
7.0 Comparator Voltage Reference Generator ..................................................................... 26
8.0 Related Application Notes............................................................................................... 32
9.0 Revision History .............................................................................................................. 33

© 2013 Microchip Technology Inc. DS70000357E-page 1

dsPIC33E/PIC24E Family Reference Manual

Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33E/PIC24E devices.
Please consult the note at the beginning of the “Comparator” or
“Op Amp/Comparator” chapter in the specific device data sheet to check
whether this document supports the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com

1.0 INTRODUCTION
The dsPIC33E/PIC24E devices have multiple built-in comparators, some of which can also be
configured as op amps, with their output being brought to an external pin for gain/filtering
connections.
As illustrated in Figure 1-1 and Figure 1-3, individual comparator and op amp options are
specified by the module’s Special Function Register (SFR) control bits. These options allow
users to:
• Select the edge for trigger and interrupt generation
• Configure the comparator voltage reference
• Configure the band gap
• Configure output blanking and masking
• Configure as a comparator or op amp
Note 1: This document references both the op amp/comparator and the dedicated
comparator modules for the dsPIC33E/PIC24E family of devices. Refer to the
“Comparator” or “Op Amp/Comparator” chapter in the specific device data
sheet for the availability of these features.
2: Throughout this document, when the comparator is referenced, it applies to both
the dedicated comparator module, as well as the op amp/comparator module when
configured as a comparator.
The op amp/comparator and comparator operating modes are configured through the CMxCON
register. Some of the options include Op Amp or Comparator mode, polarity selection of the
comparator and inverting/non-inverting comparator polarity, as well as input selection options.
An option is also available to use the internal reference voltage that is generated by a resistor
ladder network, which is configured by the Comparator Voltage Reference Control (CVRCON)
register (see Register 2-7 and Register 2-8).

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 Op Amp/Comparator

Figure 1-1: Dedicated Comparator Module Block Diagram

Comparator 1, 2, 3, 5
CREF (CMxCON<4>)
(x = 1, 2, 3, 5)
CxIN1+ 0

CVREFIN 1 VIN+
+ Blanking Digital
CMPx Function Filter
VIN- –
(see Figure 4-1) (see Figure 4-2)
CxOUT
CxIN1- 00
Output Data/Control
CxIN2- 01

CxIN3- 10

CxIN4- 11

CCH<1:0> (CMxCON<1:0>)

Comparator Voltage
Reference
CVREF

VREF+ VREF- AVDD AVSS

Figure 1-2: Dedicated Comparator Module Block Diagram for Devices with Band Gap Reference Circuit

CREF Comparator 1, 2, 3
(x = 1, 2, 3)
CxIN1+ 0

CVREFIN 1 VIN+
+ Blanking Digital
CMPx Function Filter
VIN- (see Figure 4-1) (see Figure 4-2)
CxIN2- 00 – CxOUT
Output Data/Control
CxIN1- 01

CxIN3- 10

11

CCH<1:0>

Comparator Voltage 1.2V 00

Reference
CVREF 0.6V 01
INTREF
0.2V 10

VREF+ 11
VREF+ VREF- AVDD AVSS
BGSEL<1:0>

Note: Refer to the “Comparator” or “Op Amp/Comparator” chapter in the specific device data sheet for the
available comparators.

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Figure 1-3: Op Amp/Comparator Module Block Diagram

Op Amp/Comparator 1, 2, 3, 5
CCH<1:0> (CMxCON<1:0>) (x = 1, 2, 3, 5)

CxIN1- 00
CxIN2- 01
CxIN3- 10
Op Amp/Comparator
CXIN4- 11 VIN-
– Blanking Digital CxOUT
CMPx Function Filter
VIN+ Trigger
CxIN1+ 0 (see Figure 4-1) (see Figure 4-2)
+ Output

CVREFIN 1 OPMODE (CMxCON<10>)

–
Op Amp x OAxOUT
+
OAx
(to ADC)
CREF (CMxCON<4>)

CCH<1:0> (CMxCON<1:0>) Comparator 4

OA1/AN3 01

OA2/AN0 10

OA3/AN6 11

C4IN1- 00
VIN-
– C4OUT
Blanking Digital
CMP4 Function Filter
VIN+ (see Figure 4-1) (see Figure 4-2) Trigger
C4IN1+ 0 + Output

CVREFIN 1

CREF (CMxCON<4>)

Note: Refer to the “Comparator” or “Op Amp/Comparator” chapter in the specific device data sheet for the
available comparators.

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 Op Amp/Comparator

2.0 COMPARATOR REGISTERS

The op amp/comparator module uses the following eight registers:
• CMSTAT: Comparator Status Register
This register enables control over the operation of all comparators when the device enters
Idle mode. In addition, it provides the status of all comparator results, as well as all of the
comparator outputs and event bits, which are replicated as read-only bits in the CMSTAT
register.
• CMxCON: Op Amp/Comparator x Control Register
This register allows the application program to enable, configure and interact with the
individual comparators/op amps (on some devices).
• CMxMSKSRC: Comparator x Mask Source Select Control Register
This register allows the application program to select sources for the inputs to the blanking
function.
• CMxMSKCON: Comparator x Mask Gating Control Register
This register allows the application program to specify the blank function logic.
• CMxFLTR: Comparator x Filter Control Register
This register enables comparator filter configuration.
• CVRCON: Comparator Voltage Reference Control Register(4)
This register allows the application program to enable, configure and interact with the
comparator internal voltage reference generator (for more information, see Section 7.0
“Comparator Voltage Reference Generator”).
• CVR1CON: Comparator Voltage Reference Control Register 1(4)
This register allows the application program to enable, configure and interact with the
comparator internal voltage reference generator (for more information, see Section 7.0
“Comparator Voltage Reference Generator”).
• CVR2CON: Comparator Voltage Reference Control Register 2(4)
This register allows the application program to enable, configure and interact with the
comparator internal voltage reference generator (for more information, see Section 7.0
“Comparator Voltage Reference Generator”).

Note 1: The CVR1CON and CVR2CON registers are present on devices with two DACs.
If a device has only one DAC, then only the CVRCON register is present.

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Register 2-1: CMSTAT: Comparator Status Register

R/W-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

(1) (1)
PSIDL — — C5EVT C4EVT C3EVT C2EVT C1EVT
bit 15 bit 8

U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

(1) (1)
— — — C5OUT C4OUT C3OUT C2OUT C1OUT
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 PSIDL: Comparator Stop in Idle Mode bit

1 = Discontinues operation of all comparators when device enters Idle mode
0 = Continues operation of all comparators in Idle mode
bit 14-13 Unimplemented: Read as ‘0’
bit 12 C5EVT: Comparator 5 Event Status bit(1)
1 = Comparator event occurred
0 = Comparator event did not occur
bit 11 C4EVT: Comparator 4 Event Status bit(1)
1 = Comparator event occurred
0 = Comparator event did not occur
bit 10 C3EVT: Comparator 3 Event Status bit
1 = Comparator event occurred
0 = Comparator event did not occur
bit 9 C2EVT: Comparator 2 Event Status bit
1 = Comparator event occurred
0 = Comparator event did not occur
bit 8 C1EVT: Comparator 1 Event Status bit
1 = Comparator event occurred
0 = Comparator event did not occur
bit 7-5 Unimplemented: Read as ‘0’
bit 4 C5OUT: Comparator 5 Output Status bit(1)
When CPOL = 0:
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-
bit 3 C4OUT: Comparator 4 Output Status bit(1)
When CPOL = 0:
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-

Note 1: These bits are not available on all devices. Refer to the “Comparator” or “Op Amp/Comparator”
chapter in the specific device data sheet for availability.

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Register 2-1: CMSTAT: Comparator Status Register (Continued)

bit 2 C3OUT: Comparator 3 Output Status bit

When CPOL = 0:
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-
bit 1 C2OUT: Comparator 2 Output Status bit
When CPOL = 0:
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-
bit 0 C1OUT: Comparator 1 Output Status bit
When CPOL = 0:
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-

Note 1: These bits are not available on all devices. Refer to the “Comparator” or “Op Amp/Comparator”
chapter in the specific device data sheet for availability.

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Register 2-2: CMxCON: Op Amp/Comparator x Control Register

R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0

(1)
CON COE CPOL — — OPMODE CEVT COUT
bit 15 bit 8

R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0

(2)
EVPOL<1:0> — CREF — — CCH<1:0>(2)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CON: Comparator Enable bit

1 = Comparator is enabled
0 = Comparator is disabled
bit 14 COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
bit 13 CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 12-11 Unimplemented: Read as ‘0’
bit 10 OPMODE: Op Amp Enable bit(1)
1 = Op amp is enabled
0 = Op amp is disabled
bit 9 CEVT: Comparator Event bit
1 = Comparator event according to the EVPOL<1:0> settings occurred; disables future triggers and
interrupts until the bit is cleared
0 = Comparator event did not occur
bit 8 COUT: Comparator Output bit
When CPOL = 0 (non-inverted polarity):
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1 (inverted polarity):
1 = VIN+ < VIN-
0 = VIN+ > VIN-

Note 1: This bit not available on all devices. Refer to the “Comparator” or “Op Amp/Comparator” chapter in the
specific device data sheet for availability.
2: Inputs that are selected and not available will be tied to VSS.
3: This input is not available when OPMODE (CMxCON<10>) = 1.

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 Op Amp/Comparator

Register 2-2: CMxCON: Op Amp/Comparator x Control Register (Continued)

bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits

11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt is generated only on high-to-low transition of the polarity selected
comparator output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
Low-to-high transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
High-to-low transition of the comparator output.
01 = Trigger/event/interrupt is generated only on low-to-high transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
High-to-low transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
Low-to-high transition of the comparator output.
00 = Trigger/event/interrupt generation is disabled
bit 5 Unimplemented: Read as ‘0’
bit 4 CREF: Comparator Reference Select bit (VIN+ input)(2)
1 = VIN+ input connects to internal CVREFIN voltage(3)
0 = VIN+ input connects to CxIN1+ pin
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 CCH<1:0>: Op Amp/Comparator Channel Select bits(2)
These bits select the CxIN1, CxIN2 and CxIN3 inputs. Refer to the “Comparator” or “Op Amp/
Comparator” chapter in the specific device data sheet for the available selections.

Note 1: This bit not available on all devices. Refer to the “Comparator” or “Op Amp/Comparator” chapter in the
specific device data sheet for availability.
2: Inputs that are selected and not available will be tied to VSS.
3: This input is not available when OPMODE (CMxCON<10>) = 1.

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Register 2-3: CMxMSKSRC: Comparator x Mask Source Select Control Register

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 RW-0

— — — — SELSRCC<3:0>
bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SELSRCB<3:0> SELSRCA<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’

bit 11-8 SELSRCC<3:0>: Mask C Input Select bits
These bits select the FLTx, PTGx and PWMx inputs as mask sources. Refer to the “Comparator” or
“Op Amp/Comparator” chapter in the specific device data sheet for available selections.
bit 7-4 SELSRCB<3:0>: Mask B Input Select bits
These bits select the FLTx, PTGx and PWMx inputs as mask sources. Refer to the “Comparator” or
“Op Amp/Comparator” chapter in the specific device data sheet for available selections.
bit 3-0 SELSRCA<3:0>: Mask A Input Select bits
These bits select the FLTx, PTGx and PWMx inputs as mask sources. Refer to the “Comparator” or
“Op Amp/Comparator” chapter in the specific device data sheet for available selections.

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 Op Amp/Comparator

Register 2-4: CMxMSKCON: Comparator x Mask Gating Control Register

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN
bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 HLMS: High or Low-Level Masking Select bit

1 = The masking (blanking) function will prevent any asserted (‘0’) comparator signal from propagating
0 = The masking (blanking) function will prevent any asserted (‘1’) comparator signal from propagating
bit 14 Unimplemented: Read as ‘0’
bit 13 OCEN: OR Gate C Input Enable bit
1 = MCI is connected to the OR gate
0 = MCI is not connected to the OR gate
bit 12 OCNEN: OR Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to the OR gate
0 = Inverted MCI is not connected to the OR gate
bit 11 OBEN: OR Gate B Input Enable bit
1 = MBI is connected to the OR gate
0 = MBI is not connected to the OR gate
bit 10 OBNEN: OR Gate B Input Inverted Enable bit
1 = Inverted MBI is connected to the OR gate
0 = Inverted MBI is not connected to the OR gate
bit 9 OAEN: OR Gate A Input Enable bit
1 = MAI is connected to the OR gate
0 = MAI is not connected to the OR gate
bit 8 OANEN: OR Gate A Input Inverted Enable bit
1 = Inverted MAI is connected to the OR gate
0 = Inverted MAI is not connected to the OR gate
bit 7 NAGS: AND Gate Output Inverted Enable bit
1 = Inverted ANDI is connected to the OR gate
0 = Inverted ANDI is not connected to the OR gate
bit 6 PAGS: AND Gate Output Enable bit
1 = ANDI is connected to the OR gate
0 = ANDI is not connected to the OR gate
bit 5 ACEN: AND Gate C Input Enable bit
1 = MCI is connected to the AND gate
0 = MCI is not connected to the AND gate
bit 4 ACNEN: AND Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to the AND gate
0 = Inverted MCI is not connected to the AND gate
bit 3 ABEN: AND Gate B Input Enable bit
1 = MBI is connected to the AND gate
0 = MBI is not connected to the AND gate

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Register 2-4: CMxMSKCON: Comparator x Mask Gating Control Register (Continued)

bit 2 ABNEN: AND Gate B Input Inverted Enable bit

1 = Inverted MBI is connected to the AND gate
0 = Inverted MBI is not connected to the AND gate
bit 1 AAEN: AND Gate A Input Enable bit
1 = MAI is connected to the AND gate
0 = MAI is not connected to the AND gate
bit 0 AANEN: AND Gate A Input Inverted Enable bit
1 = Inverted MAI is connected to the AND gate
0 = Inverted MAI is not connected to the AND gate

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Register 2-5: CMxFLTR: Comparator x Filter Control Register

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— CFSEL<2:0> CFLTREN CFDIV<2:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 CFSEL<2:0>: Comparator Filter Input Clock Select bits
111 = T5CLK(1)
110 = T4CLK(1)
101 = T3CLK(1)
100 = T2CLK(1)
011 = SYNCO2(2,4)
010 = SYNCO1(2)
001 = FOSC(3)
000 = FP(3)
bit 3 CFLTREN: Comparator Filter Enable bit
1 = Digital filter is enabled
0 = Digital filter is disabled
bit 2-0 CFDIV<2:0>: Comparator Filter Clock Divide Select bits
111 = Clock Divide 1:128
110 = Clock Divide 1:64
101 = Clock Divide 1:32
100 = Clock Divide 1:16
011 = Clock Divide 1:8
010 = Clock Divide 1:4
001 = Clock Divide 1:2
000 = Clock Divide 1:1

Note 1: For more information, refer to the “Timer” chapter in the specific device data sheet or the
“dsPIC33E/PIC24E Family Reference Manual”, “Timers” (DS70362).
2: For more information, refer to the “High-Speed PWM” chapter in the specific device data sheet or the
“dsPIC33E/PIC24E Family Reference Manual”, “High-Speed PWM” (DS70645).
3: For more information, refer to the “Oscillator” chapter in the specific device data sheet or the
“dsPIC33E/PIC24E Family Reference Manual”, “Oscillator” (DS70580).
4: This bit setting is not available on all devices. Refer to the “Comparator” or “Op Amp/Comparator”
chapter in the specific device data sheet for availability.

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Register 2-6: CVRCON: Comparator Voltage Reference Control Register(4)

U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

(1)
— CVR2OE — — — VREFSEL BGSEL<1:0>(1)
bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(2) (3)
CVREN CVROE CVRR CVRSS CVR<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14 CVR2OE: Comparator Voltage Reference 2 Output Enable bit(1)
1 = (AVDD – AVSS)/2 is connected to the CVREF2O pin
0 = No voltage references are connected to the CVREF2O pin
bit 13-11 Unimplemented: Read as ‘0’
bit 10 VREFSEL: Voltage Reference Select bit
1 = CVREFIN is VREF+
0 = CVREFIN is generated by the resistor network
bit 9-8 BGSEL<1:0>: Band Gap Reference Source Select bits(1)
11 = Reference source for inverting input is VREF+
10 = Reference source for inverting input is 0.2V (nominal)
01 = Reference source for inverting input is 0.6V (nominal)
00 = Reference source for inverting input is 1.2V (nominal)
bit 7 CVREN: Comparator Voltage Reference Enable bit
1 = Comparator voltage reference circuit is powered on
0 = Comparator voltage reference circuit is powered down
bit 6 CVROE: Comparator Voltage Reference Output Enable bit(2)
1 = Voltage level (CVREFIN) is output on the CVREF pin
0 = Voltage level (CVREFIN) is disconnected from the CVREF pin
bit 5 CVRR: Comparator Voltage Reference Range Selection bit
1 = 0 to 0.67 CVRSRC, with CVRSRC/24 step-size
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step-size
bit 4 CVRSS: Comparator Voltage Reference Source Selection bit(3)
1 = Comparator voltage reference source, CVRSRC = (VREF+) – (VREF-) or CVRSRC = (VREF+) – (AVSS)
0 = Comparator voltage reference source, CVRSRC = AVDD – AVSS
bit 3-0 CVR<3:0> Comparator Voltage Reference Value Selection 0  CVR<3:0>  15 bits
When CVRR = 1:
CVREFIN = (CVR<3:0>/24) • (CVRSRC)
When CVRR = 0:
CVREFIN = 1/4 • (CVRSRC) + (CVR<3:0>/32) • (CVRSRC)

Note 1: These bits are not available on all devices. Refer to the “Comparator” or “Op Amp/Comparator”
chapter in the specific device data sheet for availability.
2: This bit overrides the TRIS bit setting.
3: Refer to the “Comparator” or “Op Amp/Comparator” chapter in the specific device data sheet for
available bit selections.
4: This register is available in devices with a single DAC.

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 Op Amp/Comparator

Register 2-7: CVR1CON: Comparator Voltage Reference Control Register 1(4)

U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0

(1) (1)
— — — — CVRR1 VREFSEL —
bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(2) (1) (3)
CVREN CVR1OE CVRR0 CVRSS CVR<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’

bit 11,5 CVRR<1:0>: Comparator Voltage Reference Range Selection bits(1)
11 = 0.00 CVRSRC to 0.94, with CVRSRC/16 step-size
10 = 0.33 CVRSRC to 0.96, with CVRSRC/24 step-size
01 = 0.00 CVRSRC to 0.67, with CVRSRC/24 step-size
00 = 0.25 CVRSRC to 0.75, with CVRSRC/32 step-size
bit 10 VREFSEL: Voltage Reference Select bit(1)
1 = CVREFIN is VREF+
0 = CVREFIN is generated by the resistor network
bit 9-8 Unimplemented: Read as ‘0’
bit 7 CVREN: Comparator Voltage Reference Enable bit
1 = Comparator voltage reference circuit is powered on
0 = Comparator voltage reference circuit is powered down
bit 6 CVR1OE: Comparator Voltage Reference Output Enable bit(2)
1 = Voltage level (CVREFIN) is output on the CVREF10 pin
0 = Voltage level (CVREFIN) is disconnected from the CVREF10 pin
bit 4 CVRSS: Comparator Voltage Reference Source Selection bit(3)
1 = Comparator voltage reference source, CVRSRC = (VREF+) – (AVSS)
0 = Comparator voltage reference source, CVRSRC = AVDD – AVSS
bit 3-0 CVR<3:0> Comparator Voltage Reference Value Selection 0  CVR<3:0>  15 bits
When CVRR<1:0> = 11:
CVREF = (CVR<3:0>/16) • (CVRSRC)
When CVRR<1:0> = 10:
CVREF = 1/3 • (CVRSRC) + (CVR<3:0>/24) • (CVRSRC)
When CVRR<1:0> = 01:
CVREF = (CVR<3:0>/24) • (CVRSRC)
When CVRR = 00:
CVREF = 1/4 • (CVRSRC) + (CVR<3:0>/32) • (CVRSRC)

Note 1: These bits are not available on all devices. Refer to the “Comparator” or “Op Amp/Comparator”
chapter in the specific device data sheet for availability.
2: This bit overrides the TRISx bit setting.
3: Refer to the “Comparator” or “Op Amp/Comparator” chapter in the specific device data sheet for available
bit selections.
4: This register is available in devices with two DACs.

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Register 2-8: CVR2CON: Comparator Voltage Reference Control Register 2(4)

U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0

(1) (1)
— — — — CVRR1 VREFSEL —
bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(2) (1) (3)
CVREN CVR2OE CVRR0 CVRSS CVR<3:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’

bit 11,5 CVRR<1:0>: Comparator Voltage Reference Range Selection bits(1)
11 = 0.00 CVRSRC to 0.94, with CVRSRC/16 step-size
10 = 0.33 CVRSRC to 0.96, with CVRSRC/24 step-size
01 = 0.00 CVRSRC to 0.67, with CVRSRC/24 step-size
00 = 0.25 CVRSRC to 0.75, with CVRSRC/32 step-size
bit 10 VREFSEL: Voltage Reference Select bit(1)
1 = Reference source for inverting input is from CVR2
0 = Reference source for inverting input is from CVR1
bit 9-8 Unimplemented: Read as ‘0’
bit 7 CVREN: Comparator Voltage Reference Enable bit
1 = Comparator voltage reference circuit is powered on
0 = Comparator voltage reference circuit is powered down
bit 6 CVR2OE: Comparator Voltage Reference Output Enable bit(2)
1 = Voltage level (CVREFIN) is output on the CVREF20 pin
0 = Voltage level (CVREFIN) is disconnected from the CVREF20 pin
bit 4 CVRSS: Comparator Voltage Reference Source Selection bit(3)
1 = Comparator voltage reference source, CVRSRC = (VREF+) – (AVSS)
0 = Comparator voltage reference source, CVRSRC = AVDD – AVSS
bit 3-0 CVR<3:0> Comparator Voltage Reference Value Selection 0  CVR<3:0>  15 bits
When CVRR<1:0> = 11:
CVREF = (CVR<3:0>/16) • (CVRSRC)
When CVRR<1:0> = 10:
CVREF = 1/3 • (CVRSRC) + (CVR<3:0>/24) • (CVRSRC)
When CVRR = 01:
CVREF = (CVR<3:0>/24) • (CVRSRC)
When CVRR = 00:
CVREF = 1/4 • (CVRSRC) + (CVR<3:0>/32) • (CVRSRC)

Note 1: These bits are not available on all devices. Refer to the “Comparator” or “Op Amp/Comparator”
chapter in the specific device data sheet for availability.
2: This bit overrides the TRISx bit setting.
3: Refer to the “Comparator” or “Op Amp/Comparator” chapter in the specific device data sheet for available
bit selections.
4: This register is available in devices with two DACs.

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 Op Amp/Comparator

3.0 COMPARATOR OPERATION

The operation of a typical comparator and the relationship between the analog input levels and
the digital output are illustrated in Figure 3-1. Depending on the comparator operating mode, the
monitored analog signal is compared to either an external or internal voltage reference. Each of
the comparators can be configured to use the same or different reference sources. For example,
one comparator can use an external reference while the others can use the internal reference.
For more information on comparator operation, see Section 7.0 “Comparator Voltage
Reference Generator”.
In Figure 3-1, the external reference, VIN-, is a fixed external voltage. The analog signal present
at VIN+ is compared to the reference signal at VIN- and the digital output of the comparator is
created by the difference between the two signals. When VIN+ is less than VIN-, the output of the
comparator is a digital low level. When VIN+ is greater than VIN-, the output of the comparator is
a digital high level. The shaded areas of the output represent the area of uncertainty due to input
offsets and response time. The polarity of the comparator output can be inverted, so that it is a
digital low level when VIN+ is greater than VIN-.

Figure 3-1: Comparator Operation

VIN+ +
Output
VIN- –

Input Offset

VIN-

VIN+

Output

Input offset represents the range of voltage levels within which the comparator trip point can
occur. The output can switch at any point in this offset range. Response time is the minimum time
required for the comparator to recognize a change in input levels.

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4.0 COMPARATOR CONFIGURATION

Each of the comparators in the comparator or op amp/comparator modules is configured
independently by various control bits in the following registers:
• CMSTAT: Comparator Status Register (Register 2-1)
• CMxCON: Op Amp/Comparator x Control Register (Register 2-2)
• CMxMSKSRC: Comparator x Mask Source Select Control Register (Register 2-3)
• CMxMSKCON: Comparator x Mask Gating Control Register (Register 2-4)
• CMxFLTR: Comparator x Filter Control Register (Register 2-5)
• CVR1CON: Comparator Voltage Reference Control Register 1 (Register 2-7)
• CVR2CON: Comparator Voltage Reference Control Register 2 (Register 2-8)

4.1 Comparator Enable/Disable

The comparator under control may be enabled or disabled using the corresponding CON bit
(CMxCON<15>). When the comparator is disabled, the corresponding trigger and interrupt
generation is disabled when CON = 0.
It is recommended to first configure the CMxCON register with all bits to the desired value and
then set the CON bit (CMxCON<15>).

4.2 Comparator Output Blanking Function

In many power control and motor control applications, there are periods of time in which the
inputs to the analog comparator are known to be invalid. The blanking (masking) function
enables the user to ignore the comparator output during predefined periods of time. In this
document, the terms, ‘masking’ and ‘blanking’, are used interchangeably.
Figure 4-1 illustrates a block diagram of the comparator blanking circuitry. A blanking circuit is
associated with each comparator.
Each comparator’s blanking function has three user-selectable inputs:
• MAI (Mask A Input)
• MBI (Mask B Input)
• MCI (Mask C Input)
The MAI, MBI and MCI signal sources are selected through the SELSRCA<3:0>,
SELSRCB<3:0> and SELSRCC<3:0> bits in the CMxMSKSRC register.
The MAI, MBI and the MCI signals are fed into an AND-OR function block, which enables the
user to construct a blanking (masking) signal from these inputs. The blanking (masking) function
is disabled following a system Reset.
The HLMS bit in the CMxMSKCON register configures the masking logic to operate properly,
depending on the default (deasserted) state of the comparators.
If the comparator is configured for ‘positive logic’, so that a ‘0’ represents a deasserted state and
the comparator output is a ‘1’ when it is asserted, the HLMS bit (CMxMSKCON<15>) should be
set to ‘0’ so that the blanking function (assuming the blanking function is active) will prevent the
‘1’ signal of the comparator from propagating through the module.
If the comparator is configured for ‘negative logic’, so that a ‘1’ represents a deasserted state and
the comparator output is a ‘0’ when it is asserted, the HLMS bit should be set to a ‘1’ so that the
blanking function (assuming blanking function is active) will prevent the ‘0’ signal of the
comparator from propagating through the module.

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 Op Amp/Comparator

Figure 4-1: User-Programmable Blanking Function Diagram

SELSRCA<3:0>
(CMxMSKSRC<3:0>)

Comparator Output To Digital

MUX A
MAI Blanking Filter
Blanking
Signals “AND-OR” Function Logic
MAI

MBI ANDI
AND
SELSRCB<3:0> MCI
(CMxMSKSRC<7:4)

MAI HLMS
(CMxMSKCON<15)
MUX B

MBI MBI MASK

Blanking OR
Signals
MCI

SELSRCC<3:0>
(CMxMSKSRC<11:8)
CMxMSKCON
MUX C

MCI
Blanking
Signals

4.3 Digital Output Filter

In many motor and power control applications, the comparator input signals can be corrupted by
the large electromagnetic fields generated by the associated external switching power
transistors. Corruption of the analog input signals to the comparator can cause unwanted
comparator output transitions. The programmable digital output filter can minimize the effects of
input signal corruption.
The digital filter requires three consecutive input samples to be similar before the output of the
filter can change state. Assuming the current state is ‘0’, a string of inputs, such as
‘001010110111’ will only yield an output state of ‘1’, at the end of the example sequence, after
the three consecutive ‘1’s. Similarly, a sequence of three consecutive ‘0’s is required before the
output will change to a zero state.
Because of the requirement of three similar consecutive states for the filter, the chosen digital
filter clock period must be one-third or less than the maximum desired comparator response time.
The digital filter is enabled by setting the CFLTREN bit (CMxFLTR<3>). The CFDIV<2:0> bits
(CMxFLTR<2:0>) select the clock divider ratio for the clock signal input to the digital filter block.
The CFSEL<2:0> bits (CMxFLTR<6:4>) select the desired clock source for the digital filter. The
digital filter is disabled (bypassed) following a system Reset.

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Figure 4-2: Digital Filter Interconnect Block Diagram

TxCLK 1xx
SYNCOx 01x
FP 000
FOSC 001
CFDIV<2:0>

CFSEL<2:0> (CMxFLTR<6:4>) CFLTREN (CMxFLTR<3>)

From Blanking Logic Digital Filter 1

CXOUT
0

4.4 Comparator Polarity Selection

To provide maximum flexibility, the output of the comparator may be inverted using the CPOL bit
(CMxCON<13>). This is functionally identical to reversing the inverting and non-inverting inputs
of the comparator for a particular mode.
The CPOL bit should be changed only when the comparator is disabled (CON = 0). Internal logic
will prevent the generation of any corresponding triggers or interrupts when CON = 0. This logic
allows both the CON and CPOL bits to be set with a single register write.

4.5 Event Polarity Selection

In addition to a programmable comparator output polarity, the op amp/comparator module also
allows software selection for trigger/interrupt edge polarity through the EVPOL<1:0> bits in the
corresponding CMxCON register. This feature allows independent control of the comparator
output, as seen on any external pins, and the trigger/interrupt generation.
Note: The corresponding comparator must be enabled (CON = 1) for the specific
trigger/interrupt generation to be enabled.

4.6 Comparator Reference Input Selection

The input to the non-inverting input of the comparator, also known as the reference input, can be
selected by the value of the CREF bit (CMxCON<4>). For more information on the CREF bit, see
Register 2-2.

4.7 Comparator Channel Selection

The input to the inverting input of the comparator, also known as the channel input, can be
selected by the CCH<1:0> bits (CMxCON<1:0>). For more information on the CCHx bits, see
Register 2-2.
Note: Not all inputs are available for both the op amp or comparator modules. Refer to the
“Comparator” or “Op Amp/Comparator” chapter in the specific device data sheet
for the available inputs.

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 Op Amp/Comparator

4.8 Comparator Event Status Bit

The Comparator Event Status (CEVT) bit (CMxCON<9>) reflects whether or not the comparator
has gone through the preconfigured event. After the bit is set, all future triggers and interrupts
from the corresponding comparator will be blocked until the user-assigned application clears the
CEVT bit. Clearing the CEVT bit begins rearming the trigger. Once the CEVT bit is cleared, it
takes an extra CPU cycle for the comparator triggers to be fully rearmed.

4.9 Status Register

To provide an overview of all comparator results, the Comparator Output bit, COUT
(CMxCON<8>), and Comparator Event bit, CEVT (CMxCON<9>), are replicated as status bits in
the CMSTAT register.
These bits are read-only and can be altered only by manipulating the corresponding CMxCON
register or the comparator input signals.

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5.0 COMPARATOR INTERRUPTS

The Comparator Interrupt Flag (CMPIF) bit (IFS1<2>) is set when the synchronized output value
of any of the comparators changes, with respect to the last read value. The CxEVT bits in the
CMSTAT register can be read by the user application to detect an event.
User-assigned software can read the CEVT and COUT bits (CMxCON<9> and CMxCON<8>) to
determine the change that occurred. Because it is possible to write a ‘1’ to this register, a
simulated interrupt can be software initiated. Both the CMPIF and CEVT bits must be reset by
clearing them in software. These bits can be cleared in the Interrupt Service Routine (ISR). For
more information, refer to the “dsPIC33E/PIC24E Family Reference Manual”, “Interrupts”
(DS70600).
Note 1: The comparison required for generating interrupts is based on the current compar-
ator state and the last read value of the comparator outputs. Reading the COUT bit
in the CMxCON register will update the values used for the interrupt generation.
2: When configured as an op amp (OPMODE = 1), the comparator interrupts are
disabled.

5.1 Interrupt Operation During Sleep Mode

If a comparator is enabled and the dsPIC33E/PIC24E device is placed in Sleep mode, the
comparator remains active. If the comparator interrupt is enabled in the interrupt module, it
remains functional. Under these conditions, a comparator interrupt event will wake up the device
from Sleep mode.
Each operational comparator consumes additional current. To minimize power consumption in
Sleep mode, turn off the comparators before entering Sleep mode by disabling the CON bit
(CMxCON<15>). If the device wakes up from Sleep mode, the contents of the CMxCON register
are not affected. For more information on Sleep mode, refer to the “dsPIC33E/PIC24E Family
Reference Manual”, “Watchdog Timer and Power-Saving Modes” (DS70615).

5.2 Interrupt Operation During Idle Mode

The comparator remains active in Idle mode. Comparator interrupt operation during Idle mode is
controlled by the Comparator Idle Mode (PSIDL) bit (CMSTAT<15>). If PSIDL = 0, normal
interrupt operation continues. If PSIDL = 1, the comparator continues to operate, but it does not
generate interrupts.
For more information on Idle mode, refer to the “dsPIC33E/PIC24E Family Reference Manual”,
“Watchdog Timer and Power-Saving Modes” (DS70615).

5.3 Effects of a Reset State

A device Reset forces the CMxCON register to its Reset state, causing the comparators to be
turned off (CON = 0). However, the input pins multiplexed with analog input sources are
configured as analog inputs by default on a device Reset. The I/O configuration for these pins is
determined by the setting of the ANSELx register. Therefore, device current is minimized when
analog inputs are present at Reset time.

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 Op Amp/Comparator

5.4 Analog Input Connection Considerations

A simplified circuit for an analog input is illustrated in Figure 5-1. A maximum source impedance
of 10 k is recommended for the analog sources. Any external component connected to an
analog input pin, such as a capacitor or a Zener diode, should have little leakage current.

Figure 5-1: Comparator Analog Input Model

RS < 10k RIC

Comparator
Input
CxIN
CPIN ILEAKAGE
VA 5 pF 500 nA

VSS

Legend:
CPIN = Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage

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6.0 OP AMP CONFIGURATION

Devices with the op amp/comparator module can be configured as op amps by setting the
OPMODE (CMxCON<10>) bit. When set, this bit enables the output of the op amp on the
OAxOUT pin for the external gain/filtering components to be added in the feedback path to either
of the op amp inputs.
With the proper configuration of the ADC module, the op amps can be configured such that the
ADC can directly sample the output of the op amp without the need to route the op amp output
to a separate analog input pin. Refer to the “dsPIC33E/PIC24E Family Reference Manual”,
“Analog-to-Digital Converter (ADC)” (DS70621) for more information on configuring the ADC.
Figure 6-1 describes this configuration, which is referred to as Configuration A.

Figure 6-1: Op Amp Configuration A

RFEEDBACK

R1
CxIN1-
VIN –
CMPx OAxOUT
CxIN1+ (VOAXOUT)
+
VADC

OAx
(to ADC)
ADC

As shown in Figure 6-2, there is a second possible configuration for the op amps, which is
referred to as Configuration B. In this configuration, the op amp is not connected internally to the
ADC. Instead, the op amp output is routed to a separate analog input pin (ANx). On certain
device families, this configuration provides an added benefit of increasing the performance of the
op amps. Refer to the “Comparator” or “Op Amp/Comparator” chapter in the specific device
data sheet for performance information.

Figure 6-2: Op Amp Configuration B

RFEEDBACK

R1
CxIN1-
VIN –
OAxOUT
CMPx
CxIN1+ (VOAXOUT)
+

ANx
ADC

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 Op Amp/Comparator

Figure 6-3 illustrates an example of a typical 3-phase motor control application taking advantage
of the op amps. In this example, the op amps sample the current through the shunt resistors, with
the output of the op amps connected directly to the ADC module, representing Configuration A
as previously described in Figure 6-1.

Figure 6-3: Op Amp Application Usage Diagram

VBUS

PWM PWM PWM

Driver Driver Driver

To Motor To Motor To Motor

PHASE_1_HIGH
PWM PWM PWM
Driver Driver Driver

PHASE_2_HIGH
PHASE_1_LOW

PHASE_2_LOW
R

BUS_HIGH C1IN1-
Op Amp 1 OPMODE
PHASE_1_LOW

C1IN1+
OA1OUT
PHASE_1_HIGH
BUS_LOW
VDD/2 OA1 (to ADC)
R

C2IN1-
Op Amp 2 OPMODE
PHASE_2_LOW

C2IN1+
OA2OUT
PHASE_2_HIGH

VDD/2 OA2 (to ADC)

R

C3IN1-
Op Amp 3 OPMODE
BUS_LOW

C3IN1+
OA3OUT
BUS_HIGH

VDD/2 OA3 (to ADC)

R

Comparator 4

To
PWM
Fault

CVREFIN

Note 1: Modules inside the dotted boxes are op amp/comparator modules.

2: Other components are shown to depict the usage of op amp/comparator modules in an application.

© 2013 Microchip Technology Inc. DS70000357E-page 25

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7.0 COMPARATOR VOLTAGE REFERENCE GENERATOR

The internal comparator voltage reference is derived from a 16-tap resistor ladder network that
provides a selectable voltage level, as illustrated in Figure 7-1. This resistor network generates
the internal voltage reference for the analog comparators. Figure 7-1 shows the block diagram
for the op amp/comparator voltage reference for devices with a single 16-tap resister ladder
network.
This voltage generator network is managed by the Comparator Voltage Reference Control
(CVRxCON) register (see Register 2-7 and Register 2-8) through these control bits:
• CVREN – Comparator Voltage Reference Enable bit (CVRxCON<7>)
This control bit enables the voltage reference circuit.
• CVRxOE – Comparator Voltage Reference Output Enable bit (CVRxCON<6>)
This control bit enables the reference voltage to be placed on the CVREF pin. When enabled,
this bit overrides the corresponding TRISx bit setting.
• VREFSEL – Voltage Reference Select bit (CVR1CON<10>)
This control bit specifies whether the reference source is external (VREF+) or it is obtained
from the 4-bit DAC output.
• VREFSEL – Voltage Reference Select bit (CVR2CON<10>)
This control bit specifies whether the internal voltage reference(4-bit DAC output) is from
CVR1 or CVR2.
• CVRSS – Comparator Voltage Reference Source Selection bit (CVRxCON<4>)
This control bit specifies that the source (CVRSS) for the voltage reference circuit is either
the device voltage supply (AVDD and AVSS) or an external reference (VREF+ and VREF-).
• CVRR<1:0> – Comparator Voltage Reference Range Selection bits (CVRxCON<11,5>)(1)
These control bits select one of the two voltage ranges covered by the 16-tap resistor ladder
network:
- 0 CVRSRC to 0.94 CVRSRC
- 0.33 CVRSRC to 0.96 CVRSRC
- 0 CVRSRC to 0.67 CVRSRC
- 0.25 CVRSRC to 0.75 CVRSRC
The range selected also determines the voltage increments available from the resistor
ladder taps (see Section 7.1 “Configuring the Comparator Voltage Reference”).
• CVR<3:0> – Comparator Voltage Reference Value Selection bits (CVRxCON<3:0>)(2)
These bits designate the resistor ladder tap position.
Table 7-1 lists the voltage at each tap for both ranges with CVRSRC = 3.3V.

Note 1: These bits are not available on all devices. Refer to the “Comparator” or
“Op Amp/Comparator” chapter in the specific device data sheet for availability.
2: Comparator Voltage Reference Value Selection bits may vary in different
devices depending on the DAC resolution. Refer to the “Comparator” or
“Op Amp/Comparator” chapter in the specific device data sheet for availability.

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 Op Amp/Comparator

Figure 7-1: Op Amp/Comparator Voltage Reference Block Diagram for Devices with Two DACs

CVRSS = 1 VREFSEL
VREF+ (CVR1CON<4>) CVRSRC (CVR1CON<10>)
CVR1CON<3:0>
AVDD
CVRSS = 0

CVR3
CVR2
CVR1
CVR0
(CVR1CON<4>) 8R 1
CVREFIN
CVREN
(CVR1CON<7>) R 0

CVRR0 R
(CVR1CON<5>)
R

16-to-1 MUX
16 Steps
CVREF10

R CVR1OE
(CVR1CON<6>)
R
VREFSEL (CVR2CON<10>)
R

0
CVRR1 8R

1
AVSS

CVRSS = 1
VREF+ (CVR2CON<4>) CVRSRC
CVR2CON<3:0>
AVDD
CVR3
CVR2
CVR1
CVR0

CVRSS = 0
(CVR2CON<4>) 8R

CVREN
(CVR2CON<4>) R

R
CVRR0
(CVR2CON<5>) R
16-to-1 MUX

R
16 Steps CVREF20

R CVR2OE
(CVR2CON<6>)
R
R

CVRR1 8R
(CVR2CON<11>)

AVSS

Note: Refer to the “Comparator” or “Op Amp/Comparator” chapter in the specific device data sheet for the
available voltage reference functionality.

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Figure 7-2: Op Amp/Comparator Voltage Reference Block Diagram for Devices with a Single DAC

CVRSS = 1 VREFSEL
VREF+ CVRSRC (CVRCON<10>)
CVRCON<3:0>
AVDD
CVRSS = 0

CVR3
CVR2
CVR1
CVR0
8R 1
CVREFIN
CVREN 0
R

16-to-1 MUX
R
16 Steps CVREF

R CVROE
(CVR1CON<6>)
R
R

CVRR 8R
AVDD
R
AVSS
CVREF20
R
AVSS CVR2OE
(CVRCON<14>)

Note: Refer to the “Comparator” or “Op Amp/Comparator” chapter in the specific device data sheet for the
available voltage reference functionality.

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 Op Amp/Comparator

Table 7-1: Typical Voltage Reference with CVRSRC = 3.3V

Voltage Reference
CVR<3:0>(2) CVRR0 = 0 CVRR0 = 0 CVRR0 = 1 CVRR0 = 1
CVRR1 = 0(1) CVRR1 = 1(1) CVRR1 = 0(1) CVRR1 = 1(1)
0000 0.825 0 1.099989 0
0001 0.928125 0.137511 1.2375 0.20625
0010 1.03125 0.274989 1.375011 0.4125
0011 1.134375 0.4125 1.512489 0.61875
0100 1.2375 0.550011 1.65 0.825
0101 1.340625 0.687489 1.787511 1.03125
0110 1.44375 0.825 1.924989 1.2375
0111 1.546875 0.962511 2.0625 1.44375
1000 1.65 1.099989 2.200011 1.65
1001 1.753125 1.2375 2.337489 1.85625
1010 1.85625 1.375011 2.475 2.0625
1011 1.959375 1.512489 2.612511 2.26875
1100 2.0625 1.65 2.749989 2.475
1101 2.165625 1.787511 2.8875 2.68125
1110 2.26875 1.924989 3.025011 2.8875
1111 2.371875 2.0625 3.162489 3.09375
Note 1: CVRR<1:0> bits are not available on all devices. Refer to the “Comparator” or
“Op Amp/Comparator” chapter in the specific device data sheet for availability.
2: Comparator Voltage Reference Value Selection bits, CVR<3:0>, may vary in differ-
ent devices depending on the DAC resolution. Refer to the “Comparator” or
“Op Amp/Comparator” chapter in the specific device data sheet for availability.

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7.1 Configuring the Comparator Voltage Reference

The voltage range selected by the CVRR<1:0> bits (CVRxCON<11,5>) determines the size of
the steps selected by the CVR<3:0> bits (CVRCON<3:0>). The equations used to calculate the
comparator voltage reference are as follows:
If CVRR<1:0> = 11:
CVREF = (CVR<3:0>/16) • (CVRSRC)
If CVRR<1:0> = 10:
CVREF = 1/3 • (CVRSRC) + (CVR<3:0>/24) • (CVRSRC)
If CVRR<1:0> = 01:
CVREF = (CVR<3:0>/24) • (CVRSRC)
If CVRR<1:0> = 00:
CVREF = 1/4 • (CVRSRC) + (CVR<3:0>/32) • (CVRSRC)
Devices with a single Comparator Voltage Reference Range Selection bit, CVRR
(CVRCON<5>), the equations used to calculate the comparator voltage reference are as follows:
If CVRR = 1:
Voltage Reference = (CVR<3:0>/24) • (CVRSRC)
If CVRR = 0:
Voltage Reference = (CVRSRC/4) + (CVR<3:0>/32) • (CVRSRC)
Devices with no Comparator Voltage Reference Range Selection bit, the equation used to
calculate the comparator voltage reference is as follows:
Voltage Reference = (CVR<3:0>/16) • (CVRSRC)

7.2 Voltage Reference Accuracy/Error

The full voltage reference range cannot be realized because the transistors on the top and
bottom of the resistor ladder network (Figure 7-1) keep the voltage reference from approaching
the reference source rails. The voltage reference is derived from the reference source; therefore,
the voltage reference output changes with fluctuations in the reference source. For reference
voltage accuracy, refer to the “Electrical Characteristics” chapter of the specific device data
sheet.

7.3 Operation During Sleep Mode

When the device wakes up from Sleep mode, through an interrupt or a Watchdog Timer time-out,
the contents of the CVRxCON register are not affected. To minimize current consumption in
Sleep mode, the voltage reference should be disabled.

7.4 Effects of a Reset

A device Reset has the following effects:
• Disables the voltage reference by clearing the CVREN bit (CVRxCON<7>)
• Disconnects the reference from the CVREF pin by clearing the CVRXOE bit (CVRxCON<6>)
• Selects the high-voltage range by clearing the CVRRx bit (CVRxCON<11,5>)
• Clears the CVRX value bits (CVRxCON<3:0>)

DS70000357E-page 30 © 2013 Microchip Technology Inc.

 Op Amp/Comparator

7.5 Connection Considerations

The voltage reference generator operates independently of the comparator. The output of the
reference generator is connected to the CVREF pin if the CVROE bit (CVRCON<6>) is set.
Enabling the voltage reference output onto the I/O when it is configured as a digital input will
increase current consumption. Configuring the port associated with CVREF as a digital output,
with CVRSS enabled, will also increase current consumption.
The CVREF output pin can be used as a simple Digital-to-Analog output with limited drive
capability. Due to this limited current drive capability, a buffer may be needed on the voltage
reference output for external connections to CVREF. Figure 7-3 illustrates a buffering technique
example. Refer to the “Comparator” or “Op Amp/Comparator” chapter in the specific device
data sheet for the current drive capability.

Figure 7-3: Comparator Voltage Reference Output Buffer Example

dsPIC33E/PIC24E

External Buffer
CVREF R(1)
Generator + Voltage Reference
Voltage CVREF – Output
Reference
Output
Impedance

Note 1: R is dependent upon the Comparator Voltage Reference Control bits, CVRR<1:0>
(CVRxCON<11,5>), and CVR<3:0> value bits (CVRxCON<3:0>).

© 2013 Microchip Technology Inc. DS70000357E-page 31

dsPIC33E/PIC24E Family Reference Manual

8.0 RELATED APPLICATION NOTES

This section lists application notes that are related to this section of the manual. These
application notes may not be written specifically for the dsPIC33E/PIC24E device family, but the
concepts are pertinent, and could be used with modification and possible limitations. The current
application notes related to the Op Amp/Comparator module are:

Title Application Note #

Make a Delta-Sigma Converter Using a Microcontroller’s Analog Comparator Module AN700
A Comparator Based Slope ADC AN863

Note: Visit the Microchip Web site (www.microchip.com) for additional application notes
and code examples for the dsPIC33E/PIC24E family of devices.

DS70000357E-page 32 © 2013 Microchip Technology Inc.

 Op Amp/Comparator

9.0 REVISION HISTORY

Revision A (November 2008)
This is the initial released version of this document.

Revision B (April 2010)

This version of the document includes the following updates:
• Replaced Figure 26-1: Comparator I/O Operating Modes
• Updated Register 26-2: CMxCON: Comparator x Control Register:
- Changed the default POR values for the COE, COUT and EVPOL<1:0> bits
- Updated the selection encoding tables for the CREF and CCH<1:0> bits
- Updated the CREF = 1 definition
- Updated the CCH<1:0> = 11 definition
• Updated Register 26-3: CMxMSKSRC: Comparator x Mask Source Select Control Register:
- Renamed the SELSRC_A, SELSRC_B and SELSRC_C bits to SELSRCA, SELSRCB
and SELSRCC
- Changed the bit value definitions for SELSRCA, SELSCRB and SELSRCC
• Updated Register 26-4: CMxMSKCON: Comparator x Mask Gating Control Register:
- Removed the word, ‘inverted’, from the OCEN, OBEN, ACEN and ABEN bit definitions
• Added Note 1, Note 2 and Note 3, and updated the CFSEL<2:0> bits definition in
Register 26-5: CMxFLTR: Comparator x Filter Control Register
• Updated the bit value definitions for the VREFSEL and BGSEL<1:0> bits in
Register 26-6: CVRCON: Comparator Voltage Reference Control Register

Revision C (July 2011)

This version of the document includes the following updates:
• Document has been updated to include both op amp and comparator features. Updates
include:
- Updated Section 26.1 “Introduction” to include the description for the
op amp/comparator module
- Updated Figure 26-1
- Added Figure 26-2 for op amp/comparator I/O operating modes
- Updated bit 4 and bits<1-0> in Register 26-2 to include settings applicable for the
comparator, as well as the op amp module
- Added paragraphs about op amp/comparator features in
Section 26.3 “Comparator Operation”
- Added “It is recommended to first configure the CMxCON register with all bits to the
desired value, and then set the CON bit (CMxCON<15>).”, which provides information
on how the comparator module can be operated as an op amp
- Added Section 26.6 “Op Amp Configuration”
• Added Figure 26-5
• Updated Register 26-1
• Minor updates in Register 26-3 through Register 26-6
• Updated the comparator register map (see Table 26-2)
• Minor updates to formatting and text have been incorporated throughout the document

© 2013 Microchip Technology Inc. DS70000357E-page 33

dsPIC33E/PIC24E Family Reference Manual

Revision D (December 2011)

This version of the document includes the following updates:
• Updated Section 26.1 “Introduction”
• Updated the following figures:
- Figure 26-1
- Figure 26-2
- Figure 26-4
- Figure 26-5
- Figure 26-9
- Figure 26-12
• Removed Figure 26-6
• Updated all registers (see Register 26-1 through Register 26-6)
• Removed the last two paragraphs in Section 26.3 “Comparator Operation”
• Removed Section 26.4.2 “Comparator as an Op Amp”
• Removed Section 26.4.9 “Low-Power Selection”
• Removed Figure 26-7: Comparator Configuration for Op Amp/Comparator Module and
Figure 27-8: Op Amp Configuration for Op Amp/Comparator Module
• Updated Section 26.4 “Comparator Configuration”
• Added Op Amp Configuration A and Op Amp Configuration B diagrams (see Figure 26-7
and Figure 26-8)
• Relocated Section 26.6 “Comparator Interrupts” to Section 26.5 “Comparator Interrupts”
• Removed the Op Amp/Comparator Register Map (Table 26-2)

Revision E (June 2013)

Major changes in this version (including Section number being removed from the title):
• CVR1CON and CVR2CON Registers (Register 2-7 and Register 2-8) are included
• Table 7-1 is updated
• Figure 7-1 is changed
Other minor changes:
• A few notes have been added
• Minor updates to formatting and text have been incorporated throughout the document

DS70000357E-page 34 © 2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
Incorporated in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of
devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries.
the buyer’s risk, and the buyer agrees to defend, indemnify and
Analog-for-the-Digital Age, Application Maestro, BodyCom,
hold harmless Microchip from any and all damages, claims,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
suits, or expenses resulting from such use. No licenses are
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
conveyed, implicitly or otherwise, under any Microchip
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
intellectual property rights.
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2013, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-240-9

QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures

== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2013 Microchip Technology Inc. DS70000357E-page 35

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DS70000357E-page 36  2013 Microchip Technology Inc.