Computer Organization
Computer Organization
Computer Organization
School ANAND SCHOOL OF ENGINEERING & TECHNOLOGY
Batch 2024-26
Program MCA
Branch CSE
Academics Year 2024-25
Semester FIRST SEMESTER
Course Code MCC-104
Course Title Computer Organization
Credits 3
Contact Hours (L- 3-0-0
T-P)
Course Status Core
Course Objectives
1 Understand computer hardware components and architecture.
2 Learn instruction set architecture and assembly language.
3 Explore CPU design, memory hierarchy, and input-output.
4 Gain knowledge of parallelism, pipelining, and performance evaluation.
Acquire practical skills relevant to computer networks and distributed
5
systems.
Apply theoretical understanding to real-world scenarios through projects and
6
exercises.
Bloom’s
Course Outcomes
Knowledge
(After completion of Course students will be able to learn)
Level ( KL)
Understand the basic structure and operation of a digital
CO1 K1
computer system.
Analysis of the design of ALU and understanding fixed-
CO2 K2
point and floating-point arithmetic operations
Know the concepts of control unit techniques
CO3 K3
and the concept of Pipelining.
Understand the hierarchical memory system K3
CO4
and its mechanisms
Understand cache memories and virtual memory K3
CO5
concepts
Analyze I/O devices and standard I/O interfaces K4
CO6
performance of interrupt in CPU.
Course Description
Computer Architecture and Organization is a foundational course that explores the design and
structure of computer systems. Students will learn about the fundamental principles and
components that enable the execution of programs and the functioning of modern computers. This
course covers topics such as instruction set architecture, memory systems, processor organization,
input/output systems, and system performance evaluation
SYLLABUS
Introduction Co Proposed
Unit 1
Mapping Lectures
Functional units of digital system and their CO1 08
A
interconnections
B Buses, bus architecture, types of buses and CO1
bus arbitration. Register, bus and memory
transfer..
Processor organization, general registers CO1
C organization, stack organization and
addressing modes.
Unit 2 Arithmetic and Logic Unit
Look ahead carries adders. CO2
Multiplication: Signed operand 08
A
multiplication, Booths algorithm and
array multiplier
Division and logic operations. CO2
B Floating point arithmetic operation,
Arithmetic & logic unit design
C IEEE Standard for Floating Point Numbers CO2
Unit 3 Control System Unit 08
Instruction types, formats, instruction cycles CO3
and sub cycles (fetch and execute etc), micro
A
operations, execution of a complete
instruction.
Program Control, Reduced CO3
B
Instruction Set Computer, Pipelining.
Hardwire and micro programmed control: CO3
C micro program sequencing, concept of
horizontal and vertical micro programming.
Unit 4 System Memory 08
Basic concept and hierarchy, CO4
semiconductor RAM memories, 2D &
A
2 1/2D memory organization. ROM
memories.
Cache memories: concept and CO4
design issues & performance,
B
address mapping and replacement
Auxiliary memories.
Magnetic disk, magnetic tape and optical CO4
C disks Virtual memory: concept
implementation.
Unit 5 Input / Output Devices 08
Peripheral devices, I/O interface, I/O CO5
A ports, Interrupts: interrupt hardware,
types of interrupts and exceptions.
Modes of Data Transfer: CO6
Programmed I/O, interrupt initiated
B
I/O and Direct Memory Access., I/O
channels and processors
Serial Communication: Synchronous CO5
C & asynchronous communication,
standard communication interfaces
Mode of Theory
examination
Weightage CA MTE ETE Total CA MTE Total
Distribution
% 25% 25 % 50% 100% 50% 50% 100 %
25 25 50 100 Marks 25 25 50
Marks Marks
Course Mapping
COS PO1 PO2 PO3 PO PO5 PO6 PO7 PO8 PO9 PO10 PO1 PO1 PSO1 PSO2 PSO 3
4 1 2
CO1 3 3 2 1 2 2 3 2 2 2 1 1 1 1 3
CO2 2 3 3 3 1 1 3 2 2 2 1 2 2 2 3
CO3 3 3 2 1 1 2 3 2 2 1 1 1 1 1 3
CO4 3 2 2 2 1 1 3 2 2 2 2 1 1 1 3
CO5 3 3 1 1 1 2 3 2 2 2 2 1 1 1 3
CO6 3 3 2 1 1 2 3 2 2 1 1 2 2 2 3