10/19/24, 7:34 PM DFT, Scan and ATPG – VLSI Tutorials

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DFT, Scan and ATPG

The chip manufacturing process is prone to defects and the defects are commonly
referred as faults. A fault is testable if there exists a well-specified procedure to
expose it in the actual silicon. To make the task of detecting as many faults as
possible in a design, we need to add additional logic; Design for testability (DFT)
refers to those design techniques that make the task of testing feasible. In this
article we will be discussing about the most common DFT technique for logic test,
called Scan and ATPG. Before going into Scan and ATPG basics, let us first
understand the concept of fault model.

Fault Models

Fault models abstract the behavior of manufacturing defects so that test vectors
can be generated to detect them.

• Functional Defects : Stuck-at Fault Model

• Current defects : Pseudo Stuck-at Fault Model (IDDQ)
• Speed defects: At-speed Fault Model, Path Delay Fault Model

However in this article we will be discussing about two most common fault
models: stuck-at and at-speed fault models.

1. Stuck-at Faults

This is the most common fault model used in industry. It models manufacturing
defects which occurs when a circuit node is shorted to VDD (stuck-at-1 fault) or
GND (stuck-at-0 fault) permanently. The fault can be at the input or output of a
gate. Thus a simple 2-input AND gate has six possible stuck-at faults.

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In the circuit shown in Figure 1, suppose we have a stuck-at-0 fault at the output
of an AND gate. Note one important thing, there are three input ports in the
circuit, thus we can have a combination of eight different inputs or patterns {000,
001, 010, 011, 100, 101, 110, 111}; out of the eight patterns, only two patterns {011,
111} will be able to detect this fault because with rest of the patterns the expected
output will be same as the actual circuit output in the presence of this s-a-0 fault.
This is a small circuit so we can easily find the pattern that can detect this fault,
but what about much bigger circuits? Well we don’t have to worry about it as the
CAD tools (ATPG tools) will do that for us. The ATPG tools will try to generate the
stuck-at fault patterns required to test all the possible fault locations using
complex algorithms, but if it is unable to find patterns for few faults, then it will
classify those faults as untestable.

Figure 1: stuck-at-0 fault in a circuit

2. At-speed Faults

It models the manufacturing defects that behave as gross delays on gate input-
output ports. So each port is tested for logic 0-to-1 transition delay (slow-to-rise
fault) or logic 1-to-0 transition delay (slow-to-fall fault). Like stuck-at faults,
the at-speed fault can be at the input or output of a gate, thus a simple 2-input
AND gate has six possible at-speed faults.

In the circuit shown in Figure 2, suppose we have a slow-to-fall fault at the

output of an AND gate. As shown, a slower 1-to-0 transition at the output of AND
gate can affect the value captured by the Flop 2 at its capture edge. It is important
to note that only with an initial state ‘1’ in Flop 1 and 010 at the input, we will be
able to detect this fault. And like stuck-at fault pattern generation, the ATPG tools
will try to generate the at-speed fault patterns required to test all the possible
fault locations.

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10/19/24, 7:34 PM DFT, Scan and ATPG – VLSI Tutorials

Figure 2: slow-to-fall fault in a circuit

Scan and ATPG

Scan is the internal modification of the design’s circuitry to increase its test-
ability. ATPG stands for Automatic Test Pattern Generation; as the name
suggests, this is basically the generation of test patterns. In other words, we can
say that Scan makes the process of pattern generation easier for detection of the
faults we discussed earlier.

Figure 3: A typical sequential circuit (before scan insertion)

To test a fault we need to initialize the flops to the required values as we had
shown while discussing about stuck-at faults and at-speed faults. In a bigger
sequential circuit (without scan), it is difficult to control the flop’s value through
primary inputs and observe the captured response in primary outputs. To solve
this issue we do ‘Scan Insertion’ during synthesis.

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The goal of ‘Scan Insertion’ is to make a difficult-to-test sequential circuit

behave (during testing process) like an easier-to-test combinational circuit.
Achieving this goal involves two steps –

1. Converting Regular Flop to Scan Flop

All the flops in the design are converted into scan flops (as shown in Figure 4),
except –
• The ones that are excluded by user. These are called non-scan flops.
• The ones that have DFT DRC violation(s).

Figure 4: Regular flop vs Scan flop

2. Stitching the Scan Flops to form Scan Chains

The scan flops are stitched to form scan chain(s) (as shown in Figure 5). The
number of scan chains depends upon various user inputs like –
• Length of scan chain
• Clock domain mixing
• Power domain mixing
• Voltage domain mixing

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Figure 5: A typical sequential circuit compatible for Scan and ATPG (after scan insertion)

To initialize any flop to a value (refer the Figure 5), we simply make the SE = 1,
such that SI to Q path is activated and we shift in the required values serially
through a top level primary input called Scan-Input. Once the required values are
loaded to the flops, we capture the values from combinational circuit by making
SE = 0. And to observe the captured response we make the SE = 1 and serially shift
out the captured data through a primary output called Scan-Output. Thus in a
way, we can say the scan flop’s output (Q) act as pseudo primary output of the
design and the scan flop’s input (D) act as pseudo primary inputs to the design,
thereby making it a pseudo combination circuit.

Once the patterns are generated, the expected response of the circuit for each
pattern is obtained in pre-silicon. The expected responses along with the patterns
are then stored in the memory of Automatic Test Equipment (ATE). In post-
silicon, the manufactured chip is tested using the ATE, which loads the pattern
and compares it with the expected response for pass or fail status.

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Figure 6: A schematic showing how testing works

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