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Verilog HDL - Different Types of Modelling - CODE STALL

DDCO

Uploaded by

haanisuh23
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© © All Rights Reserved
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13/11/2023, 16:52 Verilog HDL: Different types of Modelling – CODE STALL

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Verilog HDL: Different types of Modelling


This post will give you an idea of different types of modelling styles in Verilog HDL or any HDL if it
matters.

When we think of any digital circuit, either it is a combinational or a sequential circuit, we have three
aspects in our mind. They are:-

1. Circuit diagram or schematic,


2. Logical Expression,
3. and Truth table.

So, when comes to Verilog HDL or any HDL, there are three aspects of Modelling:

1. Structural or Gate-level modelling,


2. Dataflow modelling,
3. Behavioral modelling.

These three modelling aspects in Verilog HDL relate to those three aspects of a digital circuit
respectively. Let’s glide into the next section…

Structural/Gate-level Modelling:

The Circuit diagram of a digital circuit shows the logic gates present in it. Likewise in Structural
modelling, we model a circuit by using Primitive gates, and predefined modules.

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13/11/2023, 16:52 Verilog HDL: Different types of Modelling – CODE STALL

When we design a Verilog code entirely using Primitive Logic Gates, it is called “Gate Level
Modelling“. This is Lowest level abstraction, and it is hard to understand the intent of the code by the
human, but is easy and guaranteed for machine compiling and logical synthesis.

If we create smaller modules using Logic gates, and then we use those small modules to create a big
circuit, it is called “Structural Modelling“. We connect Gates and modules using wires here.

Get detailed explanation and information of Structural Modelling in the post here: Verilog HDL:
Structural Modelling (Part-1)

Dataflow Modelling:

Dataflow modelling is completely done by the logical expression of the digital circuit. We have logical
and arithmetic operators in Verilog, which we can use to create logical expressions of the digital
circuit.

This is a medium level abstraction. This type of modelling along with structural modelling is Highly
Recommended in ASIC design.

Behavioral Modelling:

The behavioural modelling completely depends on the truth table or behaviour of the circuit. In this
modelling, we can design hardware without even knowing the components present in it, because it
doesn’t care.

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If we know the behaviour of the circuit, we can design it. This is the highest level abstraction. This
modelling is recommended for FPGA prototyping and other Reconfigurable devices.

We will discuss each type of modelling in detail in upcoming posts…Stay Tuned.

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13/11/2023, 16:52 Verilog HDL: Different types of Modelling – CODE STALL

Content Created: 07/07/2017


Content Updated: 3/08/2017

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Published by KK

 View all posts by KK

 July 7, 2017
Verilog

behavioral, dataflow, Structural, Verilog

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