DIGITAL LOGIC DESIGN

VHDL Coding for FPGAs

Unit 1
✓ DESIGN FLOW
✓ DATA TYPES
✓ LOGIC GATES IN VHDL
✓ TESTBENCH GENERATION
✓ XILINX: I/O ASSIGNMENT
✓ USE OF std_logic_vector
Daniel Llamocca
 ✓ DESIGN FLOW
▪ Design Entry: The circuit is specified using a Hardware
Description Language (e.g., VHDL, Verilog).
▪ Functional Simulation: Also called behavioral
simulation. Here, we will only verify the logical operation
of the circuit. Stimuli is provided to the logic circuit, so we
can verify the outputs behave as we expect.
▪ Physical Mapping: The inputs/outputs of our digital
circuit are mapped to specific pins of the FPGA.
▪ Timing Simulation: It simulates the circuit considering
its timing behavior (delays between inputs and outputs)
▪ Implementation: A configuration file (‘bitstream’ file) is
generated and then downloaded onto the FPGA
configuration memory.

Daniel Llamocca
✓ DESIGN FLOW (Vivado Software)
▪ Synthesis: In this step, the VHDL code is examined for
syntax errors and warnings. While your code should be free
of syntax errors, watch out for warnings and critical
warnings. After this, we do behavioral simulation.
▪ Simulate Behavioral Model: We need to write a VHDL
file called ‘testbench’ where we specify the stimuli to the
logic circuit.
▪ Implement Design (Translate + Map + Place & Route)
▪ Generate Programming File: Here, a configuration file or
bitstream (.bit) is generated. This file will configure the
FPGA so that the logic circuit is implemented on it.
▪ Configure Target Device (Programming): The bitstream
file is written onto the FPGA configuration memory so that a
digital circuit is materialized. At this stage, we can verify
whether the hardware is actually working.
Daniel Llamocca
✓ LOGIC DATA TYPES
▪ Type: This is how data (digital signals or even abstract constructs like
variables) is specified in VHDL. Though different standards are available, a
common one is the IEEE std_logic_1164, that allows for these basic types:
▪ std_logic, std_logic_vector, std_logic_2d
▪ The std_logic type defines nine (9) possible states for a 1-bit signal:
▪ ‘U’ : Uninitialized
▪ ‘X’ : Forced Unknown
▪ ‘0’ : Zero
▪ ‘1’ : One
▪ ‘Z’ : High impedance
▪ ‘W’ : Weak unknown
▪ ‘L’ : Weak Zero
▪ ‘H’ : Weak One
▪ ‘-’ : Don’t care
▪ Other data types:
▪ array (group of signals, or group of groups)
▪ integer, user-defined
Daniel Llamocca
✓ LOGIC DATA TYPES:
▪ A digital circuit includes internal signals and external signals (also
called I/Os). In VHDL, I/O specification is called ‘mode’.
▪ Mode: Physical characteristics of inputs/outputs of a logic
circuit. The following modes are available in VHDL:
✓ IN : Input port of a circuit

✓ OUT : Output port of a circuit.

VHDL syntax: in VHDL, it is not possible to feedback an
output port to the input of the circuit.

✓ INOUT : Bidirectional port (it can be an input or output at

different times). It is very useful when implementing
bidirectional buses.

✓ BUFFER : Output port. In VHDL, if we define an output signal

as BUFFER, the signal can be fed back as an input of the
circuit. However, vendor support is inconsistent.
Daniel Llamocca
✓ LOGIC GATES IN VHDL
▪ VHDL allows for the specification of Boolean functions
based on the following gates: AND, OR, NOT, XOR,
NAND, and NOR.

▪ EXAMPLE: Write the VHDL code to implement the

following circuit whose output is ‘F’:

C
x
B
F

A y
• Note: In VHDL, A B C are inputs (IN), F is an output
(OUT), and x and y are internal signals (signal).
Daniel Llamocca
✓ LOGIC GATES IN VHDL
▪ EXAMPLE: VHDL code: example.vhd
library ieee;
use ieee.std_logic_1164.all;
I/Os are specified here
entity example is
port ( A, B, C: in std_logic; A
F: out std_logic); B logic F
circuit
end example; C

architecture struct of example is

signal x,y: std_logic;
begin
x <= C nor B; Internal Description
of the logic circuit
y <= A and not(B); is specified here

F <= not(x xor y);

end struct;

Daniel Llamocca
✓ TESTBENCH GENERATION
▪ EXAMPLE: library ieee;
use ieee.std_logic_1164.all;
tb_example.vhd entity tb_example is
end tb_example;
architecture behavior of tb_example is
component example

the outputs
We retrieve
Unit
We provide

port ( A,B,C: in std_logic;

stimuli

Under F: out std_logic);

Test end component;
(UUT) -- Inputs
signal A: std_logic := '0'; -- default value
signal B: std_logic := '0'; -- default value
signal C: std_logic := '0'; -- default value
A -- Outputs
B UUT F signal f: std_logic;
'example' begin
C
uut: example port map (A=>A,B=>B,C=>C,F=>F);
Specified in stim_proc: process -- Stimulus process
testbench begin
Simulator Output
wait for 100 ns -- reset state
-- Stimuli:
A <='0';B <='0';C <='0'; wait for 20 ns;
A <='1';B <='0';C <='1'; wait for 20 ns;
wait;
end process;
end;
Daniel Llamocca
✓ XILINX ISE: I/O ASSIGNMENT
(obsolete)
UCF file: We need to map the I/Os of our logic circuit to physical
FPGA pins. In a board (e.g., Nexys-4), these FPGA pins are
connected to specific components: LEDs, switches, buttons, etc.
▪ EXAMPLE: The inputs A, B, C are assigned to switches.
The output F is assigned to an LED (ON if F is ‘1’). The
Nexys-4 Artix-7 FPGA Board is used.
▪ ISE 14.7: I/O standard must be specified for every pin
▪ UCF file: example.ucf
# Inputs
NET "A" LOC="U9" | IOSTANDARD="LVCMOS33"; #SW0 FPGA pins: R7 U8 U9 T8

NET "B" LOC="U8" | IOSTANDARD="LVCMOS33"; #SW1

NEXYS 4
NET "C" LOC="R7" | IOSTANDARD="LVCMOS33"; #SW2 schematic names: SW2 SW1 SW0 LED0
ON (1)

# Outputs OFF(0)

NET "F" LOC="T8" | IOSTANDARD="LVCMOS33"; #LED0 I/O VHDL names: A B C F

➢ example.zip: example.vhd, tb_example.vhd, example.ucf

Daniel Llamocca
✓ VIVADO: I/O ASSIGNMENT
XDC file: Here, we map the I/Os of our circuit to physical FPGA
pins. In a board (e.g. Nexys-4), many FPGA pins are wired to
specific components (LEDs, switches, buttons, etc.).
▪ Example: Nexys-4 Artix-7 FPGA Board:
To connect the inputs a, b, c to SW2 SW1 SW0 and the output f to
LED0, we assign a, b, c, f to the corresponding FPGA pins (this
mapping information is provided by the board’s manufacturer).
▪ Vivado: The I/O standard and pin name must be specified for
every I/O port. Pin names are case-sensitive and must match
the port names as specified in the VHDL entity.
# Inputs▪ XDC file: example.xdc
set_property PACKAGE_PIN U9 [get_ports {a}]
set_property IOSTANDARD LVCMOS33 [get_ports {a}] FPGA pins: R7 U8 U9 T8
set_property PACKAGE_PIN U8 [get_ports {b}]
set_property IOSTANDARD LVCMOS33 [get_ports {b}] NEXYS 4
schematic names: SW2 SW1 SW0 LED0
set_property PACKAGE_PIN R7 [get_ports {c}] ON (1)
set_property IOSTANDARD LVCMOS33 [get_ports {c}]
OFF(0)
# Outputs
a b c f
set_property PACKAGE_PIN T8 [get_ports {f}] I/O VHDL names:

set_property IOSTANDARD LVCMOS33 [get_ports {f}]

➢ example.zip: example.vhd, tb_example.vhd, example.xdc
Daniel Llamocca
✓ EXAMPLE: Light Control
▪ There are three available switches. We want LED1 ON
when only one of the switches is in the ON position. And
we want LED0 ON only when the three switches are in the
ON position.
SW2 SW1 SW0 LED1 LED0 SW2 SW1 SW0
ON (1)
0 0 0 0 1 OFF (0)
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
LED1 LED0
1 0 0 1 1
1 0 1 0 1
1 1 0 0 1
1 1 1 0 0

𝐿𝐸𝐷1 = 𝑆𝑊2 𝑆𝑊1𝑆𝑊0 + 𝑆𝑊2𝑆𝑊1𝑆𝑊0 + 𝑆𝑊2𝑆𝑊1 𝑆𝑊0

→ 𝐿𝐸𝐷1 = 𝑆𝑊2 𝑆𝑊1 𝑆𝑊0 + 𝑆𝑊2𝑆𝑊1 𝑆𝑊0

𝐿𝐸𝐷0 = 𝑆𝑊2 + 𝑆𝑊1 + 𝑆𝑊0

➢ light_ctrl.zip: light_ctrl.vhd, tb_light_ctrl.vhd,

light_ctrl.ucf
Daniel Llamocca
✓ USE of std_logic_vector
▪ This type defines an array of bits.
▪ Here, we use the std_logic_vector type for an input signal.
library ieee;
use ieee.std_logic_1164.all;

entity test is
port ( A: in std_logic_vector (3 downto 0);
-- A: |A3|A2|A1|A0|
y: out std_logic); A = A3A2A1A0
end test; A(3)
A(2)
y
architecture struct of test is A(1)
A(0)
begin
-- The circuit represents an AND gate
-- with 4 inputs: A(3), A(2), A(1), A(0)
y <= A(3) and A(2) and A(1) and A(0);

end struct;
Daniel Llamocca
✓ USE of std_logic_vector
▪ Here, we use this type in a testbench for ‘test’.
library ieee;
use ieee.std_logic_1164.all;
entity tb_test is
* The values for a signal of end tb_test;
type std_logic_vector
architecture behavior of tb_test is
can be specified in different component test
ways (see this testbench). port ( A: in std_logic_vector(3 downto 0);
F: out std_logic);
end component;
* A <=“0010”: It is -- Inputs
equivalent to: signal A: std_logic_vector(3 downto 0):= "0000";
-- Outputs
A(3)<=‘0’; A(2)<=‘0’; signal f: std_logic;
A(1)<=‘1’; A(0)<=‘0’; begin
uut: test port map (A=>A,F=>F);
stim_proc: process -- Stimulus process
begin
100 ns 120 ns 140 ns wait for 100 ns -- reset state
A 0000 0010 1111 1101
-- Stimuli:
A <= "0010"; wait for 20 ns;
F A <= x"F"; wait for 20 ns; -- A <="1111"
A <= "11"&"01"; wait for 20 ns; -- A <="1101"
wait;
end process;
Daniel Llamocca end;
✓ USE of std_logic_vector
▪ In the example, we use the std_logic_vector type for an output signal.

library ieee;
use ieee.std_logic_1164.all;

entity tst is
port ( A,B: in std_logic;
F: out std_logic_vector (3 downto 0);
-- F: |F3|F2|F1|F0
end tst;
A B F = F3F2F1F0
architecture struct of tst is F(3)

begin F(2)

F(0) <= A and B; F(1) <= A xor B;

F(1)
F(2) <= A or B; F(3) <= not(A);
F(0)
end struct;

Daniel Llamocca
✓ EXAMPLE: Security Combination
▪ A lock is opened only when a certain combination of
switches exist: Switches: 01101011
▪ The lock will be represented by 8 LEDs. Open Lock  All
LEDS ON.
SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0
ON (1)

OFF (0)
LED7

LED6

LED5

LED4

LED3

LED2

LED1

LED0
➢ sec_comb.zip: sec_comb.vhd, tb_sec_comb.vhd,
sec_comb.ucf
Daniel Llamocca