74AC191 Up/Down Counter with Preset and Ripple Clock

November 1988
Revised November 1999

74AC191
Up/Down Counter with Preset and Ripple Clock
General Description Features
The AC191 is a reversible modulo 16 binary counter. It fea- ■ ICC reduced by 50%
tures synchronous counting and asynchronous presetting. ■ High speed—133 MHz typical count frequency
The preset feature allows the AC191 to be used in pro-
grammable dividers. The Count Enable input, the Terminal ■ Synchronous counting
Count output and the Ripple Clock output make possible a ■ Asynchronous parallel load
variety of methods of implementing multistage counters. In ■ Cascadable
the counting modes, state changes are initiated by the ris- ■ Outputs source/sink 24 mA
ing edge of the clock.

Ordering Code:
Order Number Package Number Package Description
74AC191SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC191SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC191MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC191PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols
Connection Diagram

IEEE/IEC

Pin Descriptions
Pin Names Description
CE Count Enable Input
CP Clock Pulse Input
P0–P3 Parallel Data Inputs
PL Asynchronous Parallel Load Input
U /D Up/Down Count Control Input
Q0–Q3 Flip-Flop Outputs
RC Ripple Clock Output
TC Terminal Count Output

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74AC191
RC Truth Table
Inputs Outputs

PL CE TC CP RC
(Note 1) H = HIGH Voltage Level
L = LOW Voltage Level
H
H
L
H
H
X X H

X = Immaterial
= LOW-to-HIGH Transition
= Clock Pulse
Note 1: TC is generated internally
H X L X H
L X X X H

Functional Description
The AC191 is a synchronous up/down counter. The AC191 ripple through to the last stage before the clock goes HIGH.
is organized as a 4-bit binary counter. It contains four edge- There is no such restriction on the HIGH state duration of
triggered flip-flops with internal gating and steering logic to the clock, since the RC output of any device goes HIGH
provide individual preset, count-up and count-down opera- shortly after its CP input goes HIGH.
tions. The configuration shown in Figure 3 avoids ripple delays
Each circuit has an asynchronous parallel load capability and their associated restrictions. The CE input for a given
permitting the counter to be preset to any desired number. stage is formed by combining the TC signals from all the
When the Parallel Load (PL) input is LOW, information preceding stages. Note that in order to inhibit counting an
present on the Parallel Load inputs (P0–P3) is loaded into enable signal must be included in each carry gate. The
the counter and appears on the Q outputs. This operation simple inhibit scheme of Figure 1 and Figure 2 doesn't
overrides the counting functions, as indicated in the Mode apply, because the TC output of a given stage is not
Select Table. affected by its own CE.
A HIGH signal on the CE input inhibits counting. When CE
is LOW, internal state changes are initiated synchronously Mode Select Table
by the LOW-to-HIGH transition of the clock input. The
direction of counting is determined by the U/D input signal, Inputs Mode
as indicated in the Mode Select Table. CE and U/D can be


changed with the clock in either state, provided only that PL CE U/D CP
the recommended setup and hold times are observed.


H L L Count Up
Two types of outputs are provided as overflow/underflow
indicators. The terminal count (TC) output is normally H L H Count Down
LOW. It goes HIGH when the circuits reach zero in the L X X X Preset (Asyn.)
count down mode or 15 in the count up mode. The TC out-
put will then remain HIGH until a state change occurs, H H X X No Change (Hold)
whether by counting or presetting or until U/D is changed.
The TC output should not be used as a clock signal State Diagram
because it is subject to decoding spikes.
The TC signal is also used internally to enable the Ripple
Clock (RC) output. The RC output is normally HIGH. When
CE is LOW and TC is HIGH, RC output will go LOW when
the clock next goes LOW and will stay LOW until the clock
goes HIGH again. This feature simplifies the design of mul-
tistage counters, as indicated in Figure 1 and Figure 2. In
Figure 1, each RC output is used as the clock input for the
next higher stage. This configuration is particularly advan-
tageous when the clock source has a limited drive capabil-
ity, since it drives only the first stage. To prevent counting in
all stages it is only necessary to inhibit the first stage, since
a HIGH signal on CE inhibits the RC output pulse, as indi-
cated in the RC Truth Table. A disadvantage of this config-
uration, in some applications, is the timing skew between
state changes in the first and last stages. This represents
the cumulative delay of the clock as it ripples through the
preceding stages.
A method of causing state changes to occur simulta-
neously in all stages is shown in Figure 2. All clock inputs
are driven in parallel and the RC outputs propagate the
carry/borrow signals in ripple fashion. In this configuration
the LOW state duration of the clock must be long enough to
allow the negative-going edge of the carry/borrow signal to

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 74AC191
Functional Description (continued)

FIGURE 1. N-Stage Counter Using Ripple Clock

FIGURE 2. Synchronous N-Stage Counter Using Ripple Carry/Borrow

FIGURE 3. Synchronous N-Stage Counter with Parallel Gated Carry/Borrow

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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74AC191
Absolute Maximum Ratings(Note 2) Recommended Operating
Supply Voltage (VCC ) −0.5V to +7.0V Conditions
DC Input Diode Current (IIK) Supply Voltage (VCC) 2.0V to 6.0V
VI = −0.5V −20 mA Input Voltage (VI) 0V to VCC
VI = VCC + 0.5V +20 mA Output Voltage (VO) 0V to VCC
DC Input Voltage (VI) −0.5V to VCC + 0.5V Operating Temperature (TA) −40°C to +85°C
DC Output Diode Current (IOK) Minimum Input Edge Rate (∆V/∆t)
VO = −0.5V −20 mA VIN from 30% to 70% of VCC
VO = VCC + 0.5V +20 mA VCC @ 3.3V 4.5V, 5.5V 125 mV/ns
DC Output Voltage (VO) −0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO) ±50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND) ±50 mA Note 2: Absolute maximum ratings are those values beyond which dam-
age to the device may occur. The databook specifications should be met,
Storage Temperature (TSTG) −65°C to +150°C
without exception, to ensure that the system design is reliable over its
Junction Temperature (TJ) power supply, temperature, output/input loading variables. Fairchild does
not recommend operation of FACT circuits outside databook specifica-
PDIP 140°C tions.

DC Electrical Characteristics
VCC TA = +25°C TA = −40°C to +85°C
Symbol Parameter Units Conditions
(V) Typ Guaranteed Limits
VIH Minimum HIGH Level 3.0 1.5 2.1 2.1 VOUT = 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V
5.5 2.75 3.85 3.85
VIL Maximum LOW Level 3.0 1.5 0.9 0.9 VOUT = 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V
5.5 2.75 1.65 1.65
VOH Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V IOUT = −50 µA
5.5 5.49 5.4 5.4
3.0 2.56 2.46 VIN = VIL or VIH
4.5 3.86 3.76 V IOH −12 mA
5.5 4.86 4.76 IOH = −24 mA
IOH.= −24 mA (Note 3)
VOL Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V IOUT = 50 µA
5.5 0.001 0.1 0.1
3.0 0.36 0.44 VIN = VIL or VIH
4.5 0.36 0.44 V IOL = 12 mA
5.5 0.36 0.44 IOL = 24 mA
IOL = 24 mA (Note 3)
IIN Maximum Input
5.5 ±0.1 ±1.0 µA VI = VCC, GND
(Note 5) Leakage Current
IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max
IOHD Output Current (Note 4) 5.5 −75 mA VOHD = 3.85V Min
ICC Maximum Quiescent VIN = VCC
5.5 4.0 40.0 µA
(Note 5) Supply Current or GND
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.

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 74AC191
AC Electrical Characteristics
VCC CL = 50 pF TA = −40°C to +85°C

Symbol Parameter (V) TA = +25°C CL = 50 pF Units

(Note 6) Min Typ Max Min Max

fMAX Maximum Count 3.3 70 105 65
MHz
Frequency 5.0 90 133 85
tPLH Propagation Delay 3.3 2.0 8.5 15.0 1.5 16.0
ns
CP to Qn 5.0 1.5 6.0 11.0 1.5 12.0
tPHL Propagation Delay 3.3 2.5 8.5 14.5 2.0 16.0
ns
CP to Qn 5.0 1.5 6.0 10.5 1.5 11.5
tPLH Propagation Delay 3.3 3.5 10.5 18.0 2.5 20.0
ns
CP to TC 5.0 2.5 7.5 12.0 1.5 14.0
tPHL Propagation Delay 3.3 4.0 10.5 17.5 3.0 19.0
ns
CP to TC 5.0 2.5 7.5 12.5 2.0 13.5
tPLH Propagation Delay 3.3 2.5 7.5 12.0 2.0 13.5
ns
CP to RC 5.0 2.0 5.5 9.5 1.0 10.5
tPHL Propagation Delay 3.3 2.5 7.0 11.5 2.0 12.5
ns
CP to RC 5.0 1.5 5.0 8.5 1.0 9.5
tPLH Propagation Delay 3.3 2.5 7.0 12.0 1.5 13.5
ns
CE to RC 5.0 1.5 5.0 8.5 1.0 9.5
tPHL Propagation Delay 3.3 2.0 6.5 11.0 1.5 12.5
ns
CE to RC 5.0 1.5 5.0 8.0 1.0 9.0
tPLH Propagation Delay 3.3 2.5 6.5 12.5 2.0 14.5
ns
U /D to RC 5.0 1.5 5.0 9.0 1.0 10.0
tPHL Propagation Delay 3.3 2.5 7.0 12.0 2.0 13.5
ns
U /D to RC 5.0 1.5 5.0 8.5 1.0 10.0
tPLH Propagation Delay 3.3 2.0 7.0 11.5 1.5 13.5
ns
U /D to TC 5.0 1.5 5.0 8.5 1.0 9.5
tPHL Propagation Delay 3.3 2.0 6.5 11.0 1.5 12.5
ns
U /D to TC 5.0 1.5 5.0 8.5 1.0 9.5
tPLH Propagation Delay 3.3 2.5 8.0 13.5 2.0 15.5
ns
Pn to Qn 5.0 2.0 5.5 9.5 1.0 10.5
tPHL Propagation Delay 3.3 2.5 7.5 13.0 1.5 14.5
ns
Pn to Qn 5.0 1.5 5.5 9.5 1.0 10.5
tPLH Propagation Delay 3.3 3.5 9.5 14.5 2.5 17.5
ns
PL to Qn 5.0 2.0 5.5 9.5 1.0 10.5
tPHL Propagation Delay 3.3 3.0 8.0 13.5 2.0 15.5
ns
PL to Qn 5.0 2.0 6.0 10.0 1.5 11.0
Note 6: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V

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74AC191
AC Operating Requirements
VCC TA = +25°C TA = −40°C to +85°C

Symbol Parameter (V) C L = 50 pF CL = 50 pF Units

(Note 7) Typ Guaranteed Minimum
tS Setup Time, HIGH or LOW 3.3 1.0 3.0 3.0
ns
Pn to PL 5.0 0.5 2.0 2.5
tH Hold Time, HIGH or LOW 3.3 −1.5 0.5 1.0
ns
Pn to PL 5.0 −0.5 1.0 1.0
tS Setup Time, LOW 3.3 3.0 6.0 7.0
ns
CE to CP 5.0 1.5 4.0 4.5
tH Hold Time, LOW 3.3 −4.0 −0.5 −0.5
ns
CE to CP 5.0 −2.5 0 0
tS Setup Time, HIGH or LOW 3.3 4.0 8.0 9.0
ns
U/D to CP 5.0 2.5 5.5 6.5
tH Hold Time, HIGH or LOW 3.3 −5.0 0 0
ns
U/D to CP 5.0 −3.0 0.5 0.5

tW PL Pulse Width, LOW 3.3 2.0 3.5 4.0

ns
5.0 1.0 1.0 1.0
tW CP Pulse Width, LOW 3.3 2.0 3.5 4.0
ns
5.0 2.0 3.0 4.0
trec Recovery Time 3.3 −0.5 0 0
ns
PL to CP 5.0 −1.0 0 0
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V

Capacitance
Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF V CC = OPEN

CPD Power Dissipation Capacitance 75.0 pF V CC = 5.0V

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 74AC191
Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Package Number M16A

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74AC191
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D

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 74AC191
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16

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74AC191 Up/Down Counter with Preset and Ripple Clock
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E

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Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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