This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2904205, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 1

Enhanced Multilevel Modular Converter with

Reduced Number of Cells and Harmonic Content
D. Vozikis, Student Member, G. Adams, Member, P. Rault, O. Despouys, D. Holliday, S. Finney

Abstract—This paper presents an alternative implementation Several derivatives of modular multilevel converters that
of a modular multilevel converter (MMC) that generates a large employ unipolar, asymmetric and symmetric bipolar cells have
number of voltage levels per phase with high resolution voltage been presented [8]–[19]. It has been shown that the use of
steps from a reduced number of cells per arm. The presented
MMC employs a half-bridge chain-link of medium-voltage cells unipolar cells such as half-bridge or three-level flying capacitor
and a full-bridge chain-link of low-voltage cells in each of its cells leads to MMC topologies that cannot retain control
arms. The total blocking voltage of the full-bridge chain-link is when the DC link voltages fall below the respective critical
equivalent to half that of the medium-voltage half-bridge cell. voltage, and which are unable to block DC faults [10], [11].
The use of half and full-bridge cells with two distinct rated Asymmetric bipolar cells lead to MMCs that can remain under
voltages in each arm permits full exploitation of the full-bridge
cells to generate high resolution multilevel voltage waveforms full control when operating with positive DC link voltages
with fine stepped transitions between major voltage steps of from zero to rated DC voltage, even when the DC voltage
the medium-voltage half-bridge cells. In this manner, errors falls below the critical value [10]–[18]. They therefore offer
in the synthesis of the common-mode voltages of the three DC fault blocking and active control of DC fault currents. The
phase legs due to switching of the cell capacitors in and out mixed cell modular multilevel converter (MC-MMC) is an ex-
the power path are reduced. The nested multilevel operation
of the proposed MMC results in a number of voltage levels ample of an MMC that employs asymmetric bipolar cells [10],
which is related to the product, rather than the sum, of the [11], [13], [20], [21]. Moreover, the use of symmetrical bipolar
numbers of half and full-bridge cells. Detailed comparisons with cells such as the full-bridge or five-level cross connected cells
existing MMC implementations show that the proposed MMC lead to MMCs that can operate with bipolar (positive and
implementation offers the best design trade-offs (superior AC negative) DC voltage, including zero voltage, and can reverse
and DC waveforms with reduced control and power circuit
complexity). The validity of the proposed MMC implementation the DC or active power by change of DC current or voltage
is confirmed using simulations and experimentally. polarities.
Besides the realization of MMCs employing either symmet-
Index Terms—HVDC, MMC, converter topology, hybrid con-
verter rical or asymmetrical cells, further performance optimization
is possible by mixing different types of the cells, resulting in
hybrid multilevel converters. Most of the hybrid converters
I. I NTRODUCTION developed in the last decade were motivated by the trade-
An efficient transmission technology is required for the offs between DC fault ride-through, efficiency and footprint.
reinforcement of weak AC networks and continuous increase Amongst the many hybrid converter topologies proposed in
in the growth of renewable energy production, especially from the open literature in recent years, the MC-MMC is the
remote offshore wind farms [1]. Existing multilevel voltage most attractive topology as it retains many of the attributes
source converter based HVDC transmission systems have of the conventional MMC such as modularity and simple
received universal acceptance from the power industry [2], methods for bypassing faulted cells, while permitting delivery
[3], because they satisfy the requirements of high efficiency of customized features such as bespoke control range for a
and high power quality on both AC and DC sides, while given level of semiconductor losses [20].
providing internal fault management which is critical for In the broader context, MMCs and hybrid converters that
ensuring continuous operation during cell failure [4], [5]. employ asymmetrical and symmetrical bipolar cells, or a
Two main competing realizations of the modular multilevel mixture of different cells, achieve DC fault blocking and
converter (MMC) exist. The first approach utilizes a large greater control flexibility at the expense of higher semicon-
number of cells per arm, where the blocking capability of ductor losses compared to converters with unipolar cells.
each cell is small and is defined by the rating of a single Additionally, other types of hybrid multilevel converters exist
switching device (i.e. 1.6-3kV) [6]. The second approach (such as the alternate arm converter and the hybrid cascaded
adopts a reduced number of cells per arm, with each cell two-level converter), that use symmetrical bipolar cells (e.g.
rated for high DC operating voltage, ranging between 16- full-bridge cells) and incorporate director switches that operate
20kV [7]. The latter approach requires the adoption of series- at extremely low-frequency to achieve DC fault blocking
connected semiconductor devices. Reducing the number of capability at reduced footprint and semiconductor losses [22],
MMC cells is attractive since it reduces both the size and [23]. However, the aforementioned hybrid converters lack
complexity of the converter. However, AC and DC power the power quality of an MMC and require filters, thereby
quality are compromised when compared to converters with making the claim of total converter station footprint reduction
a high number of cells per arm. debatable.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2904205, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 2

This paper presents a novel MMC that utilizes both half- 1.2 1.6
Vcm
bridge (HB) and full-bridge (FB) chain-links in its arms. The 1 1.2

HB chain-link is rated for full DC-link voltage and, with 0.8 0.8
each HB cell being rated for medium voltage and therefore

p.u.
p.u.
0.6 0.4
Iarml Iarmu
requiring series-connected devices, is used to synthesize an 0.4
Varmu Varml
0
approximation to the fundamental sinusoidal output voltage −0.4
0.2
with large (major) voltage steps. The FB chain-link, with total
0 −0.8
blocking voltage equivalent to half that of an HB cell, is used 0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
T ime [s] T ime [s]
to generate additional voltage levels with small (minor) voltage
steps to smooth the transitions between the large voltage steps (a) (b)
generated by the HB cells so that the MMC provides high- 1.2
Vcm
1.6

quality sinusoidal output. In this way, the proposed MMC 1 1.2

has the potential to eliminate both AC and DC side filters 0.8 0.8

despite having a reduced number of cells. The proposed MMC

p.u.
p.u.
0.6 0.4
Iarml Iarmu
also exhibits a new, unique multiplication feature where the 0.4
Varmu Varml
0
number of voltage levels per arm is approximately equal to the 0.2 −0.4
product of the numbers of HB and FB cells, whilst the output
0 −0.8
0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
voltage step amplitude is equal to that of the FB cell voltage. T ime [s] T ime [s]
These characteristics contribute to significant improvement in
the quality of the AC and DC side waveforms generated by (c) (d)
the proposed MMC. Fig. 1. MMC (P : 1000MW, VDC : 640kV, Larm : 0.05p.u.) common-mode
The paper is organized as follows: Section II explains voltage, arm voltages and currents (a)-(b) 40 cells, (c)-(d) 400 cells.
the main motivation for the proposed MMC. Section III
describes the theoretical principles that underpin the operation
the use of large switching voltages increases the magnitudes
and modulation of the proposed MMC. Section IV presents
of the high-frequency currents and voltages to be injected
illustrative simulation and experimental results to corroborate
into the DC side. Relatively large arm inductors are therefore
the theoretical discussions presented in Section III. Section V
required to suppress the high-frequency components of the
discusses the scalability of the proposed MMC, and Section
circulating currents. Thus, an increased number of levels with
VI presents the conclusions, where the main findings of this
smaller switching voltages improves the power quality of the
research are summarized.
AC and DC side waveforms, as well as the arm waveforms,
and eliminates or minimizes passive filtering requirements.
II. M OTIVATION It should be stressed that DC fault blocking is not one
The MMC synthesizes AC voltage by inserting and by- of the motivations of the proposed topology, especially as
passing cells in the upper and lower arms such that the the maximum negative voltage its FB chain-link produces
blocking voltage of the inserted cells in both arms is slightly is negligible and insufficient to facilitate DC fault blocking.
larger or smaller than the imposed DC link voltage [24]. Instead the proposed topology is an enhancement that applies
In MMC with large numbers of cells per arm, where each to half or full-bridge MMCs that employ medium-voltage
cell is rated for a small voltage ranging from 1.6-2.5kV, the cells, predominantly to improve the quality of the AC and
nearest voltage level modulation (NLM) scheme synthesizes DC side waveforms. However, only improvement of the half-
high quality AC and DC side waveforms. In contrast, in MMC bridge MMC is pursued in this paper due to space limitations.
with relatively small numbers of cells per arm, where the rated
voltage per cell ranges from 15-20kV, pulse width modulation III. P ROPOSED TOPOLOGY
(PWM) is widely used to facilitate accurate synthesis of the In this section, the proposed topology is described in
output AC and DC voltages. The use of series-connected the context of cell placement design, fundamental operation,
switching devices in the high-voltage cells of an MMC with a modulation strategies and power losses.
reduced number of cells, e.g. 40 for a 640kV HVDC converter,
introduces significant errors to the output AC and common- A. Converter design
mode voltages of the three MMC legs, and high-frequency
Fig. 2 shows one phase leg of the proposed Enhanced MMC
components in the arm currents as shown in Fig. 1(a) and (b).
(EMMC) topology. Each arm of the EMMC consists of two
To satisfy the harmonic requirements specified by the Grid
types of chain-link: the half-bridge (HB) chain-link and the
Code, an AC filter is required to reject the high-frequency
full-bridge (FB) chain-link. The total blocking voltage of the
PWM harmonics [25]. A DC filter is required to remove
FB chain-link is equivalent to half the rated voltage of an HB
the voltage mismatch that may cause ripple resulting from
cell. If suffixes hb and f b signify the variables and parameters
transitions between the different voltages, as depicted in Fig. 1.
relating to the HB and FB chain-links respectively, the HB and
Under fast-acting current interruption, i.e. DC circuit breakers
FB cell voltages are described as:
with operating times in the range 2-5ms, over-sizing of the arm
inductors is unnecessary [26]. Increased voltage error due to VDC
Vcell−hb = (1)
Nhb

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2904205, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 3

1.25 0.625
VchainHB
1 0.5 VchainHB
Ccell−f b Varm Vcell−hb

V oltage [p.u.]

V oltage [p.u.]
0.375
0.75
Vcell−f b
Upper HB 0.25
VDC 0.5 Varm
Ccell−hb Chainlink
VchainF B 0.125
0.25
Upper FB VDC 0
Chainlink o
2·NM 0.125 Vcell−hb Vcell−f b
MC
0 −0.125
Ccell−f b −0.125 VchainF B
Larm
−0.25 −0.25
Ccell−hb 0 0.005 0.01 0.015 0.02 0 0.0025 0.005
T ime [s] T ime [s]
Larm
(a) (b)
Lower HB
Chainlink VDC

Fig. 3. EMMC internal synthesized voltages: (a) Generated voltage wave-

Lower FB VDC
Ccell−hb Chainlink
o
2·NM MC forms, (b) Detailed view of voltage waveforms
Ccell−f b

Vcell−hb
cell ( 2NVhbDC
Nf b = 2Nf b ). The positive and negative peaks
of Vchainf b in each arm are limited to ± 12 Vcell−hb , which
Fig. 2. Phase representation of EMMC topology. suggests that the minimum blocking voltage of the FB chain-
link is 21 Vcell−hb . Based on Fig. 3, the illustrative EMMC
consisting of 4 HB and 2 FB cells can generate 17 discrete
where Vcell−hb is the voltage across an HB cell, Nhb is the voltage levels in each arm. The number of arm voltage levels
number of cells in the HB chain-link, and VDC is the pole-to- generated can be expressed generically as in (5).
pole DC voltage. The HB cell capacitance may be expressed in terms of the
Vcell−hb arm equivalent capacitance Carm−tot as:
Vcell−f b = (2)
2Nf b Ccell−hb = Carm−tot · Nhb (6)
where Vcell−f b is the voltage across an FB cell and Nf b is the where Ccell−hb is the cell capacitance for the HB chain-link.
number of cells in the FB chain-link of each arm. Each arm Similarly the cell capacitance Ccell−f b for the FB cell is
will have a total number of cells N , defined in (3). expressed in terms of HB cell capacitance Ccell−hb and the
N = Nhb + Nf b (3) number of FB cells Nf b as:

The conventional MMC with Nhb cells per arm generates Nf b

Ccell−f b = Ccell−hb ·
(7)
Nhb + 1 voltage levels per arm, while the EMMC generates 2
2Nhb · Nf b + 1 voltage levels per arm. This multiplication The total capacitance of the FB chain-link is equal to half
effect enables the EMMC to generate an increased number of the total HB cell capacitance. This is achieved by increasing
voltage levels when compared to the conventional MMC with the FB cell capacitance as described in (7). In industry,
an equivalent number of cells, as shown in (4) and (5). cell capacitor sizing is based on stored energy criteria and
o
considers volume and capacitor voltage ripple. Values in the
NM MC = N + 1 (4) range 30-40kJ/MW are commonly considered [7], and (6) and
where NM o (7) guarantee that the cell capacitor voltage ripple will not
M C represents the number voltage levels per arm
of the conventional MMC. exceed ±10% which is a commonly used design value in
conventional MMC.
o
NEM M C = 2Nhb · Nf b + 1 (5) It should be noted that the FB cells of the EMMC are not
Fig. 3 depicts the ideal synthesis of the total arm voltage intended to facilitate DC fault blocking or reduced DC link
and voltages of the HB and FB chain-links, assuming an operation. The proposed concept of incorporating FB chain-
illustrative EMMC with 4 HB cells and 2 FB cells per arm, links with minor voltage steps could be extended to other
with all voltages being normalized to DC voltage VDC . Fig. MMC variants, such as the mixed-cell and FB-MMC.
3(a) shows that the HB chain-link of each EMMC arm synthe-
sizes a stepped approximation of the sinusoidal fundamental B. Operating principle
voltage Vchainhb with a major voltage step equal to 0.25p.u. The EMMC uses the HB chain-link rated at full pole-to-pole
(Vcell−hb = 14 VDC = VNDC hb
), whilst the FB chain-link of each DC voltage to synthesize the fundamental voltage with major
arm synthesizes a bipolar voltage Vchainf b with positive and voltage steps, VNDC , as shown in Fig. 4(a). The FB chain-link,
negative peaks of ±0.125p.u. (± 21 · 41 VDC = ± 81 VDC = hb
with combined blocking voltage equivalent to half that of an
VDC
± 2N hb
= 12 Vcell−hb ) and minor a voltage step of 0.125 2 p.u. HB cell, acts as an active power filter (APF) and generates
Vcell−hb
1 1
( 2 · 8 VDC = 16 1
VDC = ± 2N VDC
fb
· Nhb = 2Nf b ). Observe a multilevel waveform with minor voltage steps, 2NVhbDC ·Nf b .
that the total arm voltage Varm is the algebraic sum of the Thus, the FB chain-link facilitates smooth transition between
voltages Vchainhb and Vchainf b , synthesized by the HB and FB the major voltage levels through intermediate voltage levels
chain-links respectively. The minor voltage step seen in Varm separated by minor voltage steps. Since the HB chain-link
is derived directly from the voltage produced by a single FB synthesizes the fundamental component of the arm voltage,

2168-6777 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2904205, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 4

the continuous modulating signal mhb is used to estimate the C. Converter analysis
number of HB cells to be inserted and bypassed in each arm on In the following analysis of the proposed EMMC, subscript
a discrete basis, as shown in Fig. 4(a). Equally, the FB chain- j defines the phase index (i.e. j = a, b, c) and k defines the
link is required to inject voltage harmonics into each arm, thus upper and lower position of the arm (i.e. k = u for the upper
the modulating signal of the FB chain-link is extracted as an arm and k = l for the lower arm). The FB and HB cell
error between the target fundamental voltage and its switched capacitor currents can be described in terms of arm currents
equivalent, as shown in Fig. 4(b). Thus, the modulating signals and their switching functions (Scell ) as:
for the HB and FB chain-links are:
Nhb  
mhb ∼
X
= Scell−hbNhb ,j,k (12)
mhb = M · cos(ωt + δ) (8)
i=1
mhbN LM = round(mhb · Nhb ) (9) Nf b  
∼
X
mf b = mhb · Nhb − mhb (10) mf b = Scell−f bNf b ,j,k (13)
i=1
mf bN LM = round(mf b · Nf b ) (11)
icell−hbNhb ,j,k = Scell−hbNhb ,j,k · ij,k (14)
where M represents modulation index amplitude.
Equations (8)-(11) show that the FB and HB cell modulation icell−f bNf b ,j,k = Scell−f bNf b ,j,k · ij,k (15)
indexes are created from the same reference. Fig. 4 shows that Each arm voltage varmj,k is formed by the summation of
the HB chain link of each arm generates a staircase voltage individual cell voltages vcell−hbNhb ,j,k (t) and vcell−f bNhb ,j,k (t)
with Nhb + 1 levels, with a pre-defined major voltage step, as described in (16) to (19):
defined in (1), between two consecutive voltage levels. In
contrast, the FB chain link of each arm generates a bipolar Z  
1
voltage consisting of 2Nf b + 1 levels, with a step voltage of vcell−hbNhb ,j,k (t) = · icell−hbNhb ,j,k (t) dt (16)
Vcell−f b defined in (2). The FB cells are switched to produce Ccell−hb
positive and negative output voltage steps around an artificial Z  
zero voltage level that is synchronized with the edges of 1
vcell−f bNf b ,j,k (t) = · icell−f bNf b ,j,k (t) dt (17)
mhbN LM . Fig. 4(c) shows the ideal modulating signals of the Ccell−f b
HB and FB chain-links normalized for the synthesis of the
minor voltage levels between two successive major voltage Nhb 
X 
levels. varmj,k = scell−hbNhb ,j,k · vcell−hbNhb ,j,k
Conventional capacitor voltage balancing techniques, such y=1
as the sorting, tolerance band and cell reference modulation Nf b   (18)
X
methods [27], [28], can be applied to both chain-links of the + scell−f bNf b ,j,k · vcell−f bNf b ,j,k
EMMC. y=1
or
5 3
mf bN LM varmj,k = VchainHBj,k + VchainF Bj,k (19)
4 2

3 1
The instantaneous common-mode voltage the MMC phase
mhb
legs present at its DC terminals can be expressed in terms
Nhb

Nf b

2 mhbN LM 0

1 −1
of the instantaneous upper and lower arm voltages (varmj,u ,
0 −2
varmj,l ) as:
mf b
−1
0 0.005 0.01 0.015 0.02
−3
0 0.005 0.01 0.015 0.02 Vcm = varmj,u + varmj,l = VDC ± dV (20)
T ime [s] T ime [s]

(a) (b)
where dV represents the DC voltage drops across the internal
resistance of the arm reactors and switching devices of the
Nhbn
upper and lower arms. Synthesis of the AC voltage, as well
mhbN LM as the AC, common-mode and circulating currents, is similar
Nf b
Nhb
2
to that in the conventional MMC [24]. Fundamentally, the
mhb
Nhbn−1 Nhb necessary condition for cell capacitor voltage balancing is that
Nhb
2 the energy exchange between the cell capacitors of the HB and
FB chain-links, and both chain-links with the AC side, must
mf bN LM be zero as described in (21) and (22).
Nhbn−2

(c)
Z T 
EHBj,k = mhb · iarmj,k (t) dt = 0 (21)
Fig. 4. Modulation signals: (a) HB chain-link, (b) FB chain-link, (c) Detailed 0
illustration of modulation signals. Z T  
EF Bj,k = mf b · iarmj,k (t) dt = 0 (22)
0

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2904205, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 5

It should be noted that incorporation of the very limited Start

number of FB cells into each arm of the proposed EMMC may

Required number
affect the magnitudes of the low-order characteristic harmonics of cells Non
and the high-frequency harmonics of the circulating currents.
The DC offset of the modulating signal mf b of the FB chain-
No Yes
link is manipulated in order to ensure that the FB chain-link Vcmin < Vc < Vmax Iarm < 0
exchanges zero net energy or active power with the FB chain-
link and AC side. Modulation index mf b is adjusted according Yes No

to the FB cell energy as described in (23). Compiling

cell capacitor
list Vc < Vcmax Yes Vc > Vcmin
Nf b C 2
1 X cell−f b · vcell−f bN ,j,k
fb
Wf bj,k = (23)
Nf b i=1
2 Calculating firing
pulses
No No
Turn off cell and Turn off cell and
Fig. 5 shows the overall controller structure of the pro- assign it last on assign it first on
End the list the list
posed EMMC. The horizontal and vertical energy balance
controllers, and the outer and inner current controllers, define
the modulation index for the HB chain-link. The vertical Fig. 6. Flowchart of the tolerance band cell voltage balancing algorithm
(arm balancing) controller is responsible for ensuring that the
DC voltages across the upper and lower arms of all three
phases are equal (zero differential voltage or energy). The losses.
horizontal (average capacitor voltage or energy) controller is If HB cells are used in place of FB cells, the NLM
responsible for ensuring that the three phase legs have the algorithm must be modified accordingly, i.e. replacement of
same DC voltage to prevent DC circulating currents between the round function in (9) and (11). Additionally, twice as
the phase legs. The FB chain-link energy controller ensures many HB cells will be required, leading to increased cell
that the energy stored in the upper and lower arm FB chain- capacitance without any additional benefit. Also instead of
links is balanced. This is achieved by injecting a small DC the previously described DC offset manipulation, distributed
component into the modulation index of the FB chain-links. capacitor voltage balancing [29] in the FB cells could be used
Also, the circulating current suppression controller modifies to prevent departure of the cell voltage from its nominal value.
the FB chain-link modulation index in order to reduce the The cell capacitor voltages of the HB and FB chain-link in
switching instances of the HB cells, and hence switching each arm of the EMMC are balanced using two independent
tolerance band capacitor voltage balancing methods [27],
illustrated in Fig. 6.
FB chainlink energy controller
Wf∗bj,k V dc
Nhb

Wf bj,k
PI
D. Modulation schemes
Circulating Current Suppression controller Table I lists a number of hybrid modulation techniques
ij,u PR controller which are applicable for controlling the EMMC HB and FB
0.5 Larm Kpr chain-links. The first scheme is well-suited to the low number
HPF
ij,l
(5Hz)
0 of HB and FB cells. Application of PWM to the HB chain-
Kir
BPF
link with major voltage steps permits accurate synthesis of
(2ω)
the fundamental voltage over the full modulation index linear
Energy controller
Wj∗ Pac
3
Vdc
2
range. FB cell balancing is therefore readily achievable over
mf b
Wsum,j i∗dif f,j
PI PI
Eq.(9)to(10) the full modulation range as the FB chain-links will not be
0
forced to produce fundamental voltage (or exchange non-zero
vd θ Vdc
Wdif f,j
Power to
active power). This scheme is not however preferred due to
PI current
the increased complexity of the implementation, difficulty in
Outer controller Inner controller synchronizing two high-frequency modulations, and switching
mhb
P∗
vd loss concerns. By incorporating selective harmonic elimination
P PI i∗d vq∗ vmd
PI (SHE), the second scheme in Table I offers similar attributes
Vdc PI
ωL to the first scheme for low numbers of HB and FB cells,
Vdc∗ id dq

iq abc
including operation over the full modulation index range. Its
ωL

i∗q vq∗
extension to MMC with large numbers of HB cells is, however,
vmq θ
Q PI PI problematic with regard to calculation of switching angles and
Q∗ vq implementation, particularly at high modulation indexes where
Grid synchronization
vj,ac
abc
vd several angles will be indistinguishable. The third scheme in
ij,ac vq
vj,ac dq
id
iq
Table I inherently has all the features of the second scheme
P LL θ
when it is applied to MMC with large numbers of HB cells.
Fig. 5. EMMC control structure When it is applied to MMC with reduced numbers of HB cells,
its inability to accurately synthesize the required fundamental

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2904205, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 6

voltage during operation at low modulation indexes increases 100 6.6

the risk of voltage imbalance in the FB cells, as the FB chain-

Semiconductor loss increase [%]

6.4
link will be required to contribute fundamental voltage. The

Losses [M W ]
10 6.2
fourth scheme is well suited to MMC with large numbers of
HB and FB cells. Thus, it is able to operate over the full 6
modulation index and power factor range. 1
5.8

0 50 100 150 200 5.6

TABLE I

os
T

T
Number of HB cells

M
IG

IG

IG

−
MODULATION SCHEMES

i−

i−

i−

iC
S
S

1
0

40

+
40

+
C

40
40
C

C
C
M

M
M
M
M

M
M
HB FB

E
E
Scheme
Chain-link Chain-link (a) (b)
1 PWM PWM
Fig. 7. Semiconductor loss estimation: (a) Semiconductor loss increase
2 SHE PWM versus the number of HB cells, (b) Semiconductor loss comparison between
conventional MMC and EMMC with Si-IGBTs and SiC-MOSFETs.
3 NLM PWM
4 NLM NLM
and diode threshold voltages, on-state resistance, turn-on and
turn-off energy, and diode recovery energy.
E. Converter power losses Fig. 7(b) and Table II show that the EMMC has marginally
higher conduction loss compared to the conventional MMC
The increased semiconductor losses in the EMMC when with 40 and 400 cells per arm, when all MMCs being
compared to the conventional MMC are highly dependent compared employ the same silicon IGBTs. Amongst the
on the proportional relationship between the HB cell voltage silicon IGBT MMCs, the 400-cell MMC exhibits the lowest
and the DC link voltage. When NLM is applied to an HB switching loss, followed by the proposed EMMC, while the
chain-link which is subjected to high voltage and switching conventional 40-cell MMC exhibits the highest switching loss.
frequency ranging from 150-300Hz, the switching loss is As a result, the overall semiconductor loss of the EMMC is
expected to be slightly lower than that which could be achieved slightly lower than that of the conventional 40-cell MMC,
with PWM. However, due to FB cell operation, the additional with the conventional 400-cell MMC exhibiting the lowest
conduction losses are equivalent to those of one HB cell and, overall semiconductor loss. Additionally, the results in Fig.
as a result, the FB losses will be a small proportion of the 7(b) and Table II show further reduction in semiconductor
total arm losses, as show in (24). The total switching losses loss of the EMMC is possible by adopting wide-band-gap
may be reduced as the HB cells switch less frequently, while switching devices such as silicon carbide MOSFETs.
FB cells switch at lower voltage. Additionally, as the voltage Based on the basic design presented, the EMMC increases
requirement of FB cells is low more efficient semiconductors, semiconductor count by 2.5%, which can be offset by other
such as SiC MOSFETs which have lower conduction and design considerations such as cell redundancy.
switching losses when compared to similarly rated IGBTs,
may be employed. TABLE II
Nhb + 1 S EMICONDUCTOR LOSS COMPARISON BETWEEN MMC AND EMMC
PEM M Ccond = · PM M Ccond (24)
Nhb
Conduction Switching Total
Fig. 7(a) shows the correlation between the number of Losses
[MW] [MW] [MW]
HB cells and the increase in total semiconductor losses, but M M C400Si−IGBT 4.75 1.14 5.89
does not consider the potential reduction in switching and M M C40Si−IGBT 4.75 1.75 6.50
passive filter losses. As the number of HB cells increases the EM M C40+1Si−IGBT 4.87 1.14 6.32
incremental semiconductor losses decrease. EM M C40+1SiC−M os 4.87 1.35 6.22
Fig. 7(b) and Table II present a semiconductor loss compar-
ison between the conventional MMC implementations (40-cell
MMC and 400-cell MMC) and the EMMC. Table II and Fig.
7(b) display semiconductor losses for the 400-cell HB-MMC IV. T OPOLOGY VALIDATION
that uses silicon IGBTs (M M C400Si−IGBT ), the 40-cell HB- This section presents simulation and experimental validation
MMC that uses silicon IGBTs (M M C40Si−IGBT ), the EMMC of the EMMC. Table III shows the simulation and experimental
with 40 HB cells and 5 FB cells, where both HB and FB test rig parameters used to substantiate the viability of the
cells employ silicon IGBTs (EM M C40+1Si−IGBT ), and the EMMC. In both simulation and experimental studies, the HB
EMMC with 40 HB cells and 5 FB cells, where the HB cells chain-link is controlled using NLM, whilst the FB chain-link
use Silicon IGBTs and the FB cells employ silicon carbide is controlled using high-frequency PWM with 2.5kHz level-
(SiC) MOSFETs (EM M C40+1SiC−M os ). The semiconductor shifted carriers (one carrier per FB cell). Both chains adopt
losses displayed are computed from a detailed power loss sorting based capacitor voltage balance. The sizing of the HB
model [25] which accounts for junction temperature, IGBT cell capacitance is derived from a scaled system with inertia

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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 7

of 40kJ/MVA (equivalent to 40ms). On a similar basis, the 400 60

upper
arm inductance is calculated to be 0.2p.u. lower 40
300
20

V oltage [V ]

V oltage [V ]
200 0
TABLE III
−20
C ONVERTER SPECIFICATION 100
−40

−60 upper lower

VDC [V] 300 0
−50 −80
0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
RLOAD [Ω] 17 T ime [s] T ime [s]
Nhb / Nf b 4/4 (a) (b)
fS [kHz] 2.5 50
350
Larm [mH] 5 lower
upper 45
Chb / Cf b / Cf [mF] 2.2 / 4.4 / 5 325

V oltage [V ]
V oltage [V ]
300 40

275 lower 35

A. Simulation study upper

250 30
Simulation results where one phase of the EMMC operates 0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
T ime [s] T ime [s]
under open-loop control with a modulation index of 0.85
and a resistive load of 17Ω are shown in Fig. 8. Fig. 8(a) (c) (d)
shows the low-frequency modulation of the HB chain-link 400 350

voltage waveform using NLM, while Fig. 8(b) shows the high- upper lower
300 325
frequency modulation of the FB chain-link using PWM as de-

V oltage [V ]
scribed earlier. Observe that the synthesized switched voltage, V oltage [V ] 200
300

which is a step approximation of a sinusoidal waveform by 100

275
the FB chain-link, occupies the full DC-link voltage range
0
of VDC , whilst the FB chain-link occupies a voltage range −50
0 0.005 0.01 0.015 0.02
250
0 0.005 0.01 0.015 0.02
equivalent to half that of an HB cell, and is a small fraction T ime [s] T ime [s]
of VDC according to (2). Fig. 8(a)-(d) indicate that the voltages (e) (f)
across the cell capacitors of the HB and FB chain-links, and
8
consequently the voltages across the switching devices of both 150
6
chain links, are tightly regulated around the desired steady- 100
4

Current [A]
state values. Fig. 8(e) shows the total upper and lower arm
V oltage [V ]

50 2

voltages, which are synthesized by HB chain-links comprising 0 0

−2
four HB cells each and providing large step voltage transitions, −50
−4
and FB chain-links which consist of four FB cells providing −100 −6

small step voltage transitions. Observe that the upper and −150
0 0.005 0.01 0.015 0.02
−8
0 0.005 0.01 0.015 0.02

lower arm voltages in Fig. 8(e) exhibit a substantial increase T ime [s] T ime [s]

in the number of voltage levels, amounting to 2Nhb ·Nf b +1 (g) (h)

as described earlier. Although this illustrative simulation uses
Fig. 8. EMMC simulation results: (a) HB chain-link voltage, (b) FB chain-
only four HB cells and four FB cells, the arm voltage of link voltage, (c) HB chain-link total capacitor voltage, (d) FB chain-link total
the EMMC accurately reflects the modulating signal of a capacitor voltage, (e) total arm voltage, (f) common-mode voltage, (g) output
conventional MMC with 32 cells per arm. Fig. 8(f) shows AC voltage, (h) output AC current.
that the common-mode voltage (or instantaneous sum of the
upper and lower arm voltages) that the EMMC presents at
and fed to Cypress Semiconductor 32-bit Arm R Cortex R -
its DC terminals exhibits some high-frequency content due
M3 PSoC R 5LP low-power micro-controller units MCU 1 and
to switching edge mismatch. Fig. 8(g) and (h) show that the
MCU 2. MCU 1 manages NLM and capacitor balancing of the
EMMC produces high-quality sinusoidal output phase voltage
upper and lower HB chain-links, whilst MCU 2 is dedicated to
and current waveforms even though it is feeding a purely
high-frequency level shifted PWM (fs =2.5kHz) and capacitor
resistive load.
voltage balancing of the upper and lower FB chain-links. This
approach ensures that the fundamental voltage components
B. Experimental study generated by the upper and lower chain-links are synchronized
This section presents experimental results for a prototype and completely complementary so as to avoid any potential
single phase of a EMMC, which is based on an existing four voltage mismatches between the arms which could be reflected
cell per arm conventional MMC test rig that was upgraded to in the AC and DC voltages. Moreover, the synchronization
the EMMC topology by the addition of FB chain links and of each arm HB and FB chain-link is achieved from the
the necessary control system, as shown in Fig. 9. A 50Hz si- reference, and does not need internal communication or clock-
nusoidal reference (modulating) signal is generated externally synchronization.

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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 8

400 60
upper lower 40
300
20

V oltage [V ]
V oltage [V ]
200 0

−20
100
−40
upper lower
−60
0
−50 −80
0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
T ime [s] T ime [s]

(a) (b)
(a) (b)
350 50

vcell−hb1..Nhb ,u lower
Upper HB
Chainlink Shb1..Nhb ,u 325 upper 45

V oltage [V ]
V oltage [V ]
vcell−f b1..Nf b ,u
Cf Upper FB
Chainlink Sf b1..Nf b ,u Shb1..Nhb ,u 300 40
vcell−hb1..Nhb ,u
MCU 1 Shb1..Nhb ,l
vcell−hb1..Nhb ,l 275 lower 35
Larm upper
RLOAD Iarmup,low
VDC Reference
Generator 250 30
0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02

Larm Sf b1..Nf b ,u T ime [s] T ime [s]

vcell−f b1..Nf b ,u
MCU 2 Sf b1..Nf b ,l
vcell−hb1..Nhb ,l vcell−f b1..Nf b ,l
(c) (d)
Lower HB
Cf Chainlink Shb1..Nhb ,l
400 350

Lower FB vcell−f b1..Nf b ,l

upper lower
Chainlink Sf b1..Nf b ,l 300 325

V oltage [V ]
V oltage [V ] 200
300
(c)
100
275
Fig. 9. Experimental configuration: (a) HB and FB chain-links, (b) converter
cell, (c) schematic diagram. 0
−50 250
0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
T ime [s] T ime [s]

As in the simulation, each HB and FB chain-link consists (e) (f)

of four cells, and the capacitances of the HB and FB cells are 8
150
2.2mF and 4.4mF respectively. Two capacitors (Cf =5mF) with 6
100
split mid-point are connected across the DC power supply, as 4

Current [A]
V oltage [V ]

50
shown in Fig. 9(c), to create a return path for the single- 2

0 0
phase arrangement. A 17Ω resistive load is connected to −2
−50
the converter AC side. The experimental tests replicate the −4
−100
simulation study to enable direct comparison of the results. −6

−150 −8
Fig. 10 shows that the experimental waveforms for the voltages 0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
T ime [s] T ime [s]
across the HB and FB chain-links of the upper and lower arms,
the HB and FB cell capacitor voltages, the upper and lower (g) (h)
total arm voltages, the common-mode voltage, and the output Fig. 10. EMMC experimental results: (a) HB chain-link voltage, (b) FB chain-
phase voltage and current correspond well with the simula- link voltage, (c) HB chain-link total capacitor voltage, (d) FB chain-link total
tion waveforms illustrated in Fig. 8. The low-energy high- capacitor voltage, (e) total arm voltage, (f) common-mode voltage, (g) output
AC voltage, (h) output AC current.
frequency voltage and current spikes in Fig. 10 (a), (b), (e),
(f) and (g) are due to small switching mismatches introduced
by factors such as dead-time, differences in the turn-on and models developed in the EMTP-RV simulation environment,
turn-off times, rapid reference tracking and electromagnetic and considers a number of configurations and comparisons
interference. The adverse impact of these factors is amplified with the conventional MMC. Details of the various MMC
in the experimental waveforms in Fig. 10 due to the relative configurations being compared are shown in Table IV. In
size of the minor voltage steps of the FB cells compared to these illustrative simulations, the conventional MMC with 40
that of the major voltage steps of the HB cells. In a full-scale medium-voltage cells uses PWM and that with 400 cells uses
system where the ratio of the minor to major voltage steps NLM, whilst the HB and FB chain-links of the EMMC use
will be of the order of 0.1 or less, these current spikes are NLM. Fig. 11 shows simulation waveforms of the conventional
expected to be attenuated by the arm inductors. MMC with 40 and 400 HB cells, and the EMMC with
Nhb =40 and Nf b =5. The plots for output phase voltages
V. D ETAILED QUANTITATIVE CONVERTER COMPARISONS and currents are illustrated in rows (a) and (b) of Fig. 11
To complement the simulation and experimental validation and show that all converters being compared produce high
presented in Section IV, this section demonstrates the scalabil- quality output voltages. However, the proposed EMMC with
ity of the EMMC to high-voltage applications, using full-scale 40 medium-voltage HB cells (each rated at 16kV) and 5 FB

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2904205, IEEE Journal
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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 9

40 HB cells 400 HB cells 40 HB and 5 FB cells

TABLE IV
300 HVDC SPECIFICATIONS
(a) UAC [kV ]

150

0
Nhb =40
−150 N o cells Nhb =40 Nhb =400
Nf b =5
−300
2500 HB chain-link
PWM NLM NLM
modulation
(b) IAC [A]

1250

0 FB chain-link
−1250 - - NLM
modulation
−2500
HB cell
600
16 1.6 16
voltage [kV]
(c) varm [kV ]

400
FB cell
200 - - 0.8
voltage [kV]
0
HB cell
1800 1.30 13.02 1.30
capacitance [mF]
(d) iarm [A]

900
FB cell
- - 6.51
0
capacitance [mF]
−900 P [MW] 1000
1900
VDC [kV] 640
(e) IDC [A]

1700
1500 Larm [p.u.] 0.05
1300
1100

670
which any AC-side equipment will be subjected. The DC link
(f) Vcm [kV ]

650
currents and common-mode voltages shown in Fig. 11 rows (e)
630 and (f) reveal significant injection of high-frequency harmonic
610
18
components into the DC side of the conventional MMC with
700
40 medium-voltage HB cells compared to the conventional
(g) Vctot−hb [kV ]

17
Vctot−f b [kV ]

500
MMC with 400 HB cells and the proposed EMMC (the DC
16
300 link voltage ripples of the conventional MMCs with 40 and
15
100 400 HB cells per arm, and the EMMC with 40 HB and 5 FB
0 14
0.005
time [s]
0.015 0.005
time [s]
0.015 0.005
time [s]
0.015 cells per arm, are 5.18%, 0.22% and 0.25% respectively). This
0 is because the large switching cell voltage of the conventional
MMC with 40 medium-voltage HB cells (V chb = 16kV) creates
(h) |UAC | [db]

−20

−40 larger errors in the instantaneous magnitudes of the common-

−60

−80
0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70
Harmonics [N o ] Harmonics [N o ] Harmonics [N o ] 10
600

Fig. 11. Waveform comparison between an HB-MMC with 40 (left column) 5

V oltage [kV ]

V oltage [kV ]

and 400 (middle column) cells, and an EMMC with 40 HB cells and 5 FB 400

cells (right column). 0

200
−5

cells (each rated at 1.6kV) produces an output phase voltage

0 −10
with identical quality (THD and dv/dt) to the MMC with 400 0 0.005
time[s]
0.015 0 0.0005
time[s]
0.001

HB cells (each rated at 1.6kV). In both cases this performance

(a) (b)
is superior to that of the conventional MMC with 40 HB
cells (THD of the output voltages of the conventional MMC 18 1.8

with 40 and 400 HB cells, and the proposed EMMC with

17 1.7
40 HB cells and 5 FB cells are 1.47%, 1.32% and 1.28%
V oltage [kV ]
V oltage [kV ]

respectively). The quality of the output phase currents of the 16 1.6

three converters (Fig. 11 row (b)) is practically similar as the
arm inductances are sufficiently large to filter out all the high- 15 1.5

frequency components associated with MMC switching from

14 1.4
the arm currents (Fig. 11 row (d)). The arm voltages of the 0 0.005 0.015 0 0.02 0.04 0.06
time[s] time[s]
three MMCs are displayed in Fig. 11 row (c) and confirm the
ability of the EMMC with fewer medium-voltage HB cells to (c) (d)
match the conventional MMC with a large number of low- Fig. 12. Internal voltages of EMMC: (a) 40 HB chain-link, (b) 4 FB chain-
voltage HB cells in terms of waveform quality and dv/dt to link, (c) HB capacitor voltages, (d) FB capacitor voltages.

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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 10

103 15 VI. C ONCLUSIONS

MMC MMC
EM M C EM M C
This paper proposes an enhanced MMC topology with a

DC voltage error %
significantly reduced number of cells per arm that generates
Number of levels

10

102
high-quality AC and DC side waveforms, and a high number
5 of output voltage levels to rival the performance of the conven-
tional MMC with hundreds of cells per arm. This is achieved
0
by incorporating low-voltage FB chain-links with blocking
101 102 103 101 102 103
Number of cells Number of cells voltage equal to half that of an HB cell. The theoretical
(a) (b) development, simulations and experimental results confirm
that the EMMC offers reduced AC harmonics and DC voltage
12 2
MMC MMC ripple with a low number of cells per arm when compared to
10 EM M C EM M C
conventional MMC. The main features of the EMMC are:
DC current Ripple %

1.5
AC voltage THD %

8
• Significant improvements in the power quality of the AC
6 1
and DC side waveforms without significant increase in
4
0.5
the power circuit and control complexity when compared
2 to the conventional MMC.
0
101 102 103
0
101 102 103
• In comparison with a conventional MMC with the same
Number of cells Number of cells
number of cells, the EMMC has similar volume but
(c) (d) eliminates the need for AC and DC side filters due to
Fig. 13. Scalability of EMMC compared to conventional MMC for various
significantly improved output power quality.
numbers of cells: (a) correlation between number of cells and number of levels • The proposed concept of the low-voltage FB chain-link
produced in each arm, (b) common-mode DC voltage error, (c) DC current can be integrated into existing, currently operational,
ripple, (d) AC phase voltage THD.
low cell count MMC-based HVDC links with minimum
modification, and can be implemented in FB-MMC and
mode voltage compared to an MMC with 400 HB cells (V chb = other hybrid topologies.
• Gains that are achieved in power quality outweigh the
1.6kV) and the proposed EMMC. In practice, the DC link
voltage ripple would be exacerbated in the MMC with 40 cells marginal increases in semiconductor losses and area due
due to the dead-times and the significant mismatch between to integration of the low-voltage FB chain-links. These
the turn-on and turn off timings of the series-connected IGBTs. losses may however be reduced by using state-of-the-art
Fig. 11 row (g) shows the total cell capacitor voltage for each semiconductors devices.
of the three converters, and highlights that the total HB cell
voltages are well regulated with identical ripple, whilst the VII. ACKNOWLEDGEMENT
total EMMC FB cell voltage is also well regulated and is The authors gratefully acknowledge the support of Réseau
only a small portion of the total HB cell voltage. Fig. 12 (a) de Transport d’Électricité (RTE) in conducting this research.
and (b) show that the voltage stresses in the HB and FB cell
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