1414 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO.

11, NOVEMBER 2002

A Low-Power Small-Area 7.28-ps-Jitter 1-GHz

DLL-Based Clock Generator
Chulwoo Kim, Member, IEEE, In-Chul Hwang, and Sung-Mo (Steve) Kang, Fellow, IEEE

Abstract—In this paper, a delay-locked loop (DLL)-based clock TABLE I

generator is presented. Although a DLL-based clock generator re- COMPARISONS OF PLL AND DLL
quires a clean reference signal, it has several inherent advantages
over conventional phase-locked-loop-based clock generators, i.e.,
no jitter accumulation, fast locking, stable loop operation, and easy
integration of the loop filter. We propose a phase detector with a
reset circuitry and a new frequency multiplier to overcome the lim-
ited locking range and frequency multiplication problems of the
conventional DLL-based system. Fabricated in a 0.35- m CMOS
process, our DLL-based clock generator occupies 0.07 mm2 of area
and consumes 42.9 mW of power. It operates in the frequency range
of 120 MHz–1.1 GHz and has a measured cycle-to-cycle jitter of
7.28 ps at 1 GHz. The die area, peak-to-peak, and rms jitter are
the smallest compared to those of reported high-frequency clock
multipliers.
Index Terms—Clock generator, delay-locked loops (DLLs),
tions service (PCS) applications has used an edge combiner for
frequency multiplication, limited locking range, low jitter, phase
detector (PD). frequency multiplication [9]. However, it requires an LC tank at
the output to enhance the load impedance at the resonant fre-
quency, which consumes a large chip area. Also, a low- in-
I. INTRODUCTION ductor for small close-in phase noise draws a large tail current to
achieve the required output swing. Another drawback is that the
M OST CLOCK generators in high-performance micro-
processors employ a phase-locked loop (PLL), which
includes a voltage-controlled oscillator (VCO) [1]–[6]. The
frequency multiplication ratio is fixed once the LC-tank compo-
nent values are chosen. In [10], a DLL-based frequency synthe-
PLL is a higher order system and is difficult to design. Its loop sizer used AND–OR gates for frequency multiplication. However,
bandwidth, which is critical for stable operation, can change it always multiplies the input frequency by nine times. Further-
due to process, voltage, and temperature (PVT) variations. In more, digital AND–OR gates are very sensitive to power supply
the PLL, the VCO output timing uncertainty accumulates over noise, which significantly affects the peak-to-peak jitter perfor-
multiple oscillation cycles and is limited by the time response mance. An analog-OR I/O buffer was used to generate a 1-GHz
of the PLL [7]. State-of-the-art microprocessors operate under off-chip clock signal with an external 50- pull-up resistor [8].
increasingly more noisy conditions and suffer from the delay However, this scheme is not suitable for an on-chip high-fre-
variations due to significant power supply/substrate noises. quency clock generator. The DLL-based system is also bound
These delay variations cannot be corrected instantaneously by by a limited locking range of DLL. In this paper, we propose a
the PLL [8]. Delay-locked loop (DLL)-based clock multipliers new DLL-based clock generator, which overcomes these two
have several inherent advantages over conventional PLL-based major problems of the DLL-based system. As the clock fre-
clock multipliers. The DLL is a first-order system and is always quency goes higher, electromagnetic emission (EME) becomes
stable and, thus, easier to design. Table I summarizes the a problem and can be reduced by lowering the peak current.
characteristics of the PLL and DLL. This paper is organized as follows. Section II describes a new
DLL-based clock generators have seldom been reported, al- frequency-multiplication methodology. In Section III, we ex-
though they have several advantages over PLL-based ones. The plain the concept of proposed phase detector (PD) with reset
main reason has been due to the difficulty of frequency mul- circuitry and its gain curve. Implementation and measurement
tiplication using a voltage-controlled delay line (VCDL). Re- results of the DLL-based clock generator are presented in Sec-
cently, a DLL-based local oscillator for personal communica- tions IV and V, respectively. Finally, conclusions are drawn in
Section VI.
Manuscript received March 20, 2002; revised June 15, 2002.
C. Kim was with the Microelectronics Division, IBM, Austin, TX 78758 II. FREQUENCY MULTIPLICATION
USA. He is now with the Department of Electronics and Computer Engineering,
Korea University, Seoul, Korea (e-mail: [email protected]). Fig. 1 shows two schematic diagrams for high-frequency
I.-C. Hwang is with the Samsung Electronics Corporation, Yongin, Korea. clock generators, i.e., PLL- and DLL-based ones. As shown
S.-M. Kang is with the Baskin School of Engineering, University of
California at Santa Cruz, Santa Cruz, CA 95064 USA. in Fig. 1(a), PLL-based clock generators employ a VCO and
Digital Object Identifier 10.1109/JSSC.2002.803936 two dividers. One of the dividers (Divide by ) multiplies the
0018-9200/02$17.00 © 2002 IEEE

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KIM et al.: LOW-POWER SMALL-AREA 7.28-ps-JITTER 1-GHz DLL-BASED CLOCK GENERATOR 1415

Fig. 3. Schematic of the frequency multiplier.

(a)

(b)
Fig. 1. Schematic diagram of: (a) PLL- and (b) DLL-based clock generators.

Fig. 4. Example of the frequency multiplication of two.

(a)

keeps the previous “ ” data value. At the rising edge of the

signal, both transistors and are turned on for a short
time duration of and transfer data between nodes and
. When is “ ,” node is discharged to “ ” through
transistors – . For “ ” , charges output node to
“ ”. After three inverter delay ( ), becomes “ ”
(b)
and node is charged to “ ” through , and node keeps
Fig. 2. Jitter accumulation of: (a) PLL- and (b) DLL-based clock generators. the previous “ ” data value. At the rising edge of the signal,
the data transfer from node to node can be explained in a
input reference signal and the other (Divide by 2) creates a 50% similar manner. After data transfer, node drives to dis-
duty cycle clock output. However, as shown in Fig. 2(a), if the charge output node to “ .” Thus, output clock signal tog-
power supply noise persists over several periods of the VCO gles at every rising edge of the “ ” signal. Fig. 4 illustrates an
clock, then jitter accumulation will cause each clock edge to example of frequency multiplication by two. represents a
deviate increasingly farther from the ideal edge. Also, VCO and virtual pulse period when both and transistors are turned
dividers operating at twice the output clock frequency consume on. Even though the duty cycle ratio of signals is not 50%,
large power and may cause a high-frequency electromagnetic the output clock signal toggles at even time space because each
interference (EMI) problem. DLL-based clock generators using virtual pulse is generated at every rising edge of the sig-
a VCDL have an inherent advantage. For an open-loop VCDL, nals.
the jitter accumulates only within a single delay line, as shown If the VCDL has delay cells, then the output clock fre-
in Fig. 2(b). With the use of a high- crystal oscillator, a quency can be expressed as
DLL-based clock generator can produce a clean clock signal.
The key circuit technique for our DLL-based clock generator (1)
is based on the new frequency multiplier.
A schematic diagram of our proposed frequency multiplier is where is the frequency of the input reference signal.
shown in Fig. 3. Regulated power supply is used for the fre- Multiplication factor ( integer) of the proposed fre-
quency multiplier. is also applied to the buffer transistors of quency multiplier can be chosen easily according to the number
the multiplier. input signals ( ) feed to the multiplier to of delay cells and can be either integer or noninteger (frac-
generate the frequency-multiplied output clock signal (clk). tional increment by 0.5), although the conventional DLL-based
signals are buffered VCDL outputs. The operation of the mul- clock multipliers [9], [10] can multiply an input frequency by
tiplier is as follows. When the signal is “ ,” node is only odd and nine times, respectively. Furthermore, the multi-
discharged to “ ” through NMOS transistor , and node plication factor can be programmable with MUXs, as shown in

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1416 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 11, NOVEMBER 2002

(a)

Fig. 5. Block diagram of a programmable clock generator.

(b)
Fig. 7. Example of: (a) correct locking and (b) false locking.

(a)

(b)

(a)

(c)
(b)
Fig. 6. (a) Conventional PD. (b) Gain curve of the PD. (c) Locking range of
the DLL. Fig. 8. (a) PD with reset circuitry. (b) Its gain curve.

III. PD WITH RESET CIRCUITRY

Fig. 5. The control block generates -bit MUX select signals
A PD generates UP/DN signals according to the phase dif-
(MUX-sel) to change the multiplication factor on the fly. The
ference between the reference signal and delay line’s final stage
MUX’s block consists of 2 : 1 MUXs and an MUX
output. A bang–bang-type PD can be used in the DLL, but its
in parallel. The outputs from 2 : 1 MUXs, -bit signals (where
nonlinearity causes jitter. A conventional PD, shown in Fig. 6(a),
) feed to the frequency multiplier. The last bit among
the MUXed signals (last-bit) by MUX feeds to the PD. has a higher linearity, and its gain curve is shown in Fig. 6(b). In
The multiplication factor change with a fine granularity helps a general, for correct locking, the delay of the delay line should
robust operation of the programmable clock generator. A wide be in the following locking range:
tuning range of the VCDL is necessary to cover all the multipli-
cation factors required. (2)

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KIM et al.: LOW-POWER SMALL-AREA 7.28-ps-JITTER 1-GHz DLL-BASED CLOCK GENERATOR 1417

Fig. 9. Waveforms during the locking process with the proposed PD with reset
circuitry.

Fig. 12. I/O signals of the clock generator.

Fig. 10. Block diagram of implemented DLL-based clock generator.

Fig. 13. Measured peak-to-peak cycle jitter histogram.

TABLE II
PERFORMANCE OF CLOCK GENERATOR

Fig. 11. Chip micrograph.

where and represent the reference signal pe-

riod and delay of the delay line, respectively. While the widths
of UP/DN pulses are proportional to the phase difference of the
inputs and (output of the VCDL), short UP/DN
pulses will be generated to prevent dead zone of the PD even of a four-stage VCDL, respectively. In Fig. 7(a), the phase dif-
after the DLL is locked. ference of each stage output signal is and the final stage
For correct locking, should be equal to . VCDL output is locked at 2 . In Fig. 7(b), the phase differ-
If the delay of the delay line deviates from the above locking ence of each stage output signal is and the final stage VCDL
range, the DLL may be stuck or locked to an incorrect harmonic output is locked at 4 . If the DLL is locked at 4 , the mul-
delay. Fig. 6(c) illustrates the locking range of the DLL. The top tiplied frequency of the DLL-based clock generator will be re-
signal represents the reference signal with a period of . The duced to half.
next three signals represent the delay line’s final stage outputs A conventional PD with new reset circuitry is proposed to
with a delay amount of , , and , respectively. overcome the limited locking range of the DLL, as shown in
Fig. 7(a) and (b) shows the examples of correct and false locking Fig. 8(a). and represent the logic levels to be initialized

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1418 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 11, NOVEMBER 2002

Fig. 14. Normalized jitter comparison of high-frequency clock multipliers.

at a certain node. Internal nodes ( , ), two input signals with a proposed reset circuitry is shown in Fig. 8(b). Hence,
( , ), and output signal UP are initialized to the low one of the boundaries of limited locking range in the DLL
logic level before DLL operation. Four NMOS transistors with is removed in our proposed technique. Furthermore, a control
control signal are used to reset the nodes , , , and voltage of the delay line should be initialized to make the
to a logic level “ .” Similarly, two PMOS transistors VCDL delay within the locking range. However, due to PVT
with control signal are used to reset the internal node variations, the actual initializing range of the conventional PD
and output signal DN to a logic level “ ,” respectively. For should be narrower compared to the ideal locking range. With
both NMOS and PMOS transistors, their drains are connected the proposed PD, the VCDL output can be initialized with a
to the node to be initialized. In order to maintain symmetry in broader range.
the PD design and to reduce the static phase offset, dummy
devices are inserted at the symmetric nodes of the initialized IV. IMPLEMENTATION OF DLL-BASED CLOCK GENERATOR
nodes. For example, dummy NMOS transistors are used with
at nodes , , and DN. Also, dummy PMOS A prototype of the proposed DLL-based clock generator
transistors are used with at the nodes and UP. was implemented in a 0.35- m single-poly four-metal CMOS
In addition, symmetric layout should be done to minimize the process with a 3.3-V supply. A block diagram of the im-
static phase offset. plemented DLL-based clock generator is shown in Fig. 10.
The operation of the proposed PD will now be explained. The frequency of the reference signal ( ) is 250 MHz and
The final-stage output of the VCDL ( ) always arrives after the multiplication factor is four, resulting in an output clock
the reference signal . The DN signal is precharged “ ” frequency of 1 GHz. The proposed PD with reset circuitry is
before reference signal is fed to the PD and VCDL. The rising used for increased locking range. A charge pump is designed
edge of the first pulse of the reference signal triggers the DN to avoid UP/DN current mismatches to achieve minimum
signal to go “ ,” as shown in Fig. 9. Thus, the PD can compare static phase error over the maximum VCDL control voltage
the phase difference between and the reference signal with range [11]. The loop filter filters the charge pump output,
the 2 phase offset once the phase of is within the 3 generating control voltage . drives a voltage regulator
range. This example is shown in Fig. 9. The DN signal goes that generates the regulated supply . In the regulator
“ ” when goes “ ,” while the UP signal goes “ ” design, the loop main pole(s) usually have to be set well
when goes “ .” After both UP/DN signals go “ ,” both below the regulator bandwidth to ensure stability. However,
UP/DN will stay “ ” for a short time and then both go “ .” we adopted a single-pole regulating amplifier to regulate the
UP signal boosts control voltage of the delay line and makes the supply without compromising either noise rejection or the
VCDL delay smaller. After certain periods, the DLL is locked overall loop bandwidth [12].
and only short pulses will be generated to prevent dead zone of The DLL generates evenly spaced clock phases at 250 MHz.
the PD, as shown in Fig. 9. The resulting gain curve of the PD A source-coupled differential pair with replica bias has been

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KIM et al.: LOW-POWER SMALL-AREA 7.28-ps-JITTER 1-GHz DLL-BASED CLOCK GENERATOR 1419

used popularly as a delay element due to its low supply sensi- a reference signal of 250 MHz and a multiplication factor of
tivity. However, it consumes more power than a CMOS inverter four, resulting in an output clock frequency of 1 GHz. The
delay line [11], [13]. Furthermore, it is more susceptible to sub- measured output cycle-to-cycle jitter with a quiet supply is
strate noise and transistor mismatches [13]. With the low cur- 7.28 ps at 1 GHz. The die area, peak-to-peak, and rms jitter
rent flowing in the analog part of the clock generator, a voltage are the smallest compared to reported high-frequency clock
drop across the resistance between the analog ground and dig- multipliers. The proposed clock generator can be used for
ital ground can be reduced; thus, the area of substrate plugs can either multiple integer or noninteger frequency multiplication.
be reduced. As shown in Fig. 10, our DLL uses a simple CMOS
inverter delay line with a regulated power supply. One delay cell ACKNOWLEDGMENT
consists of two cascaded CMOS inverters. Delay is adjusted by
controlling the supply voltage with a linear voltage regulator. The authors would like to thank Dr. A. Shakouri, University
The power consumptions in an -stage CMOS buffer (two cas- of California at Santa Cruz, and Dr. Y. Koh, National Semicon-
caded inverters) delay line consumes approximately times ductor, Santa Clara, CA, for their support for measurement and
less power than differential source-coupled delay line [13]. An- testing.
other power reduction comes from the lower operation frequen-
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1420 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 11, NOVEMBER 2002

Chulwoo Kim (S’98–M’02) received the B.S. and Sung-Mo (Steve) Kang (S’72–M’72–SM’80–F’90)
M.S. degrees in electronics engineering from the received the Ph.D. degree in electrical engineering
Korea University, Seoul, Korea, in 1994 and 1996, and computer science from the University of Cali-
respectively, and the Ph.D. degree in electrical and fornia at Berkeley, in 1975.
computer engineering from the University of Illinois He has been involved with CMOS very large scale
at Urbana-Champaign, in 2001. integration (VLSI) design with AT&T Bell Laborato-
From 1990 to 1991, he was with the Korea Military ries, Murray Hill, NJ, as a Supervisor and Member of
Academy, Seoul, Korea. From 1997 to 2000, he was Technical Staff of High-End CMOS VLSI Micropro-
a Research Assistant with the Coordinated Science cessor Design. He is currently a Professor and Dean
Laboratory, University of Illinois at Urbana-Cham- of the Baskin School of Engineering, University of
paign. In 1999, he was also a Summer Intern with California at Santa Cruz. From 1985 to 2000, he was
Design Technology, Intel Corporation, Santa Clara, CA. In May 2001, he joined a Professor of electrical and computer engineering, a Research Professor of
the Microelectronics Division, IBM, Austin, TX, where he was involved in the Beckman Institute for Advanced Science and Technology and the Coordi-
high-speed broadband engine design, which includes floating-point unit custom nated Science Laboratory at the University of Illinois at Urbana-Champaign.
design, latch design, and clock distribution. Prior to joining IBM, he was a Re- From 1995 to 2000, he was Head of the Electrical and Computer Engineering
search Staff Member with the University of California, Santa Cruz, CA, in 2001. Department. He was a Visiting Professor with the Swiss Federal Institute of
Since September 2002, he has been with the Department of Electronics and Technology, Lausanne, Switzerland, Technical University of München, Munich,
Computer Engineering, Korea University, where he is currently an Assistant Germany, University of Karlsruhe, Karlsruhe, Germany, Seoul National Uni-
Professor. His research interests are in the areas of broadband processor design, versity, Seoul, Korea, and a Distinguished Lecturer with the Taiwan Research
clocking and latching, low-power/high-performance circuits, and floating-point Council, Taiwan, R.O.C. He holds six patents. He has coauthored over 300 pa-
unit and high-speed I/O. He has authored over 20 papers and one book chapter. pers and eight books, including Design Automation For Timing-Driven Layout
Dr. Kim was the recipient of the 1996 HumanTech Thesis Contest Bronze Synthesis (Norwell, MA: Kluwer, 1993), Hot-Carrier Reliability of MOS VLSI
Award presented by the Samsung Electronics Corporation, the 2001 Interna- Circuits (Norwell, MA: Kluwer, 1993), Physical Design for Multichip Modules
tional Low-Power Design Contest Award presented at the IEEE International (Norwell, MA: Kluwer, 1994), Modeling of Electrical Overstress in Integrated
Symposium on Low-Power Electronics and Design, the 2002 Design Automa- Circuits and Electrothermal Analysis of VLSI Systems(Norwell, MA: Kluwer,
tion Conference (DAC) Student Design Contest Award, and the 2002 Semicon- 2000), two editions of CMOS Digital Integrated Circuits: Design and Anal-
ductor Research Corporation (SRC) Inventor Recognition Award. ysis (New York: McGraw-Hill, 2002), and Computer-Aided Design of Optoelec-
tronic Integrated Circuits and Systems (Upper Saddle River, NJ: Prentice-Hall,
1997). His research interests include computer-aided design of VLSI circuits
and systems, design optimization for performance, reliability, low power, and
manufacturability, modeling and simulation of semiconductor devices and cir-
cuits, opto-electronic integrated circuits, and fully optical networks. He has
served on the Editorial Boards of several international journals.
Dr. Kang is a Fellow of American Association for the Advancement of
In-Chul Hwang received the B.S., M.S., and Ph.D. Science (AAAS), Association for Computing Machinery (ACM). He is a
degrees in the electronics engineering from Korea foreign member of the National Academy of Engineering of Korea. He was the
University, Seoul, Korea, in 1993, 1995, and 2000, founding editor-in-chief of the IEEE TRANSACTIONS ON VERY LARGE SCALE
respectively. INTEGRATION (VLSI) SYSTEMS and has served on the Editorial Boards of the
From 2000 to 2001, he was a Post-Doctoral PROCEEDINGS OF THE IEEE and several IEEE journals. He was the recipient
Research Associate with the University of Illinois of the Distinguished Alumnus Award presented by the Electrical Engineering
at Urbana-Champaign, where he was involved with and Computer Science Department of the University of California at Berkeley,
advanced VCO structures and DLL-based clock the IEEE Third Millennium Medal, the Alexander von Humboldt Research
generators. Since joining the Samsung Electronics Award for the Senior U.S. Scientist, the IEEE Circuits and Systems Society
Corporation, Yongin, Korea, in November 2001, Golden Jubilee Medal, the Korean Broadcasting System (KBS) Korean Abroad
he has been a Senior Engineer involved with the Compatriot Award, the IEEE Graduate Teaching Technical Field Award,
design of sigma–delta fractional-N PLLs and frequency planning for WLAN, the IEEE Circuits and Systems Society Technical Achievement Award and
GSM, etc. His current research interests are integrated RF transceivers having Meritorious Service Award, the Semiconductor Research Corporation (SRC)
multiple standard options with special emphasis on CMOS RF circuit design. Technical Excellence Award, the SRC Inventor Recognition Awards, the IEEE
Dr. Hwang was the recipient of the 1999 First Prize of the Semiconductor Circuits and Systems Darlington Prize Paper Award, and other Best Paper
Design Contest presented by the LG Semiconductor Corporation. Awards.

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