10/20/2024

Lecture 8: 80x86 IO Interfacing

Seyed-Hosein Attarzadeh-Niaki

Based on the slides by Hongzi Zhu

Microprocessors and Interfacing 1

Review
• Memory and memory interfacing
– Memory chips
– Address decoding
– Data integrity
– 8086 memory interfacing

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Outline
• IO interfacing
– Basic IO interfacing
– 8255 programmable peripheral interface
– 8253 programmable interval timer

Microprocessors and Interfacing 3

I/O in x86 Family

• X86 microprocessors have an I/O
space in addition to memory space
• Use special I/O instructions accessing
I/O devices at ports (i.e., addresses
for I/O)
• Memory can contain machine codes
and data, I/O ports only contain data
• Also referred to as peripheral I/O or
isolated I/O
• I/O ports are 8 bits in width.
– a 16-bit port is actually two
consecutive 8-bit ports being
addressed
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I/O Instructions – 8-Bit Instance

• Direct I/O instructions

– port# ranges from 00h to 0ffh, 256 ports in total

• Indirect I/O instructions

– port# ranges from 0000h to 0ffffh, 65536 ports in all
– use a 16-bit address that resides in the DX register

• Note: no segment concept for port addresses

• Instructions are also provided to transfer strings of
data between memory and I/O.
– INS and OUTS, found except the 8086/8088
Microprocessors and Interfacing 5

I/O Example

‘Y’

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Personal Computer I/O Map

• The PC uses part of I/O map for
dedicated functions, as shown here
• I/O space between ports 0000H and
03FFH is normally reserved for the
system and ISA bus
• ports at 0400H–FFFFH are generally
available for user applications, main-
board functions, and the PCI bus
• 80287 coprocessor uses 00F8H–00FFH,
so Intel reserves I/O ports 00F0H–
00FFH
Microprocessors and Interfacing 7

Output Port Design:

Latches
• Latch the data coming from the CPU
• Address decoding
• TTL-compatible voltages: 0-> 0.0 V to 0.4 V , 1-> 2.4 V to 5.0 V
currents: 0-> 0.0 to 2.0 mA, 1-> 0.0 to 400 µA

What is the address of this port?

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Input Port Design:

Three-State Buffers
• Use tri-state buffer to connect to system data bus
• Address decoding
• A pull-up resistor ensures when the switch is open, the output signal is a logic 1.
• Mechanical switch contacts physically bounce when they are closed

What is the address of this port?

Microprocessors and Interfacing 9

I/O Instructions – 16-Bit Instance

• For 16-bit I/O modules
• Direct I/O instructions
– port# ranges from 00h to 0ffh, 256 ports in total
IN AX, port# OUT port#, AX
• Indirect I/O instructions
– port# ranges from 0000h to 0ffffh, 65536 ports in all
– use a 16-bit address that resides in the DX register
MOV DX, port# MOV DX, port#
IN AX, DX OUT DX, AX
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Interfacing 8-bit I/O Modules

To A 16-Bit Data Bus
• data for even-address
programmable-logic ports are carried on
device
data bus D0-D7
• data for odd-address
ports are carried on
data bus D8-D15

Microprocessors and Interfacing 11

Recall: I/O Module Structure

Interface to Interface to
System Bus External Device

Data
Data Registers External
Device
Data Status
Interface
Lines
Logic
Status/Control Registers Control

Address
Lines Data
External
I/O Device
Logic Status
Interface
Control Logic
Lines Control

Microprocessors and Interfacing 12

Figure 7.3 Block Diagram of an I/O Module

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8255 Package & Internal Structure

PA3 1 40 PA4
Internal Data Bus
PA2 2 39 PA5
PA1 3 38 PA6 Group A PA7~PA0
37 PA7
Group A
PA0 4 Control
RD 5 36 WR Port A
CS 6 35 RESET
D0～D7
GND 7 34 D0 Data Bus PC7~PC4(3)
Group A
A1 8 8255 33 D1
Buffer Port C
A0 9 32 D2 (upper bits)
PC7 10 31 D3
RD
11 30 D4
PC6 WR Read/ Group B PC3(2)~PC0
PC5 12 29 D5 A0 Port C
D6
Write
PC4 13 28 A1 (lower bits)
PC0 14 27 D7 CS
Logic
PC1 15 26 Vcc RESET
PB7~PB0
PC2 16 25 PB7
Group B Group B
PC3 17 24 PB6 Port B
23 PB5 Control
PB0 18
PB1 19 22 PB4
PB2 20 21 PB3
Microprocessors and Interfacing 13

Internal Structure and Pins

• Three data ports: A, B, and C PA3 1 40 PA4
• Port A (PA0~PA7): can be programmed all as PA2 2 39 PA5
PA1 3 38 PA6
input/output
PA0 4 37 PA7
• Port B (PB0~PB7): can be programmed all as RD 5 36 WR
input/output CS 6 35 RESET
• Port C (PC0~PC7): can be split into two separate GND 7 34 D0
parts PCU and PCL; any bit can be programmed A1 8 8255 33 D1
individually A0 9 32 D2
PC7 10 31 D3
PC6 11 30 D4
• Control register (CR) PC5 12 29 D5
13 28 D6
• Internal register: used to setup the chip PC4
27 D7
PC0 14
PC1 15 26 Vcc
• Group A, Group B and control logic PC2 16 25
24
PB7
PB6
PC3 17
• Group A (PA & PCU) PB0 18 23 PB5
• Group B (PB & PCL) PB1 19 22 PB4
PB2 20 21 PB3

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Internal Structure and Pins Internal Data Bus

Group A PA7~PA0
Group A
Control Port A

• Data bus buffer D0～D7

Data Bus Group A PC7~PC4(3)
Buffer Port C

• An interface between CPU RD

(upper bits)

and 8255 WR
A0
Read/
Write
Group B
Port C
PC3(2)~PC0

A1
• Bidirectional, tri-state, 8-bit
(lower bits)
CS
Logic
RESET
PB7~PB0
Group B Group B
Control Port B

• Read/Write control logic ~CS A1 A0 ~RD ~WR Function

• Internal and external control 0 0 0 0 1 PA->Data bus
signals 0 0 1 0 1 PB->Data bus
• RESET: high-active, clear the 0 1 0 0 1 PC->Data bus
control register, all ports are 0 0 0 1 0 Data bus->PA
set as input port 0 0 1 1 0 Data bus->PB
• ~CS, ~RD, ~WR 0 1 0 1 0 Data bus->PC
• A1, A0: port selection signals 0 1 1 1 0 Data bus->CR

1 × × 1 1 D0~D7 in float

Microprocessors and Interfacing 15

Operation Modes
• Input/output modes
– Mode 0, simple I/O mode:
• PA, PB, PC: PCU{PC4~PC7}, PCL{PC0~PC3}
• No Handshaking: negotiation between two entities before communication
• Each port can be programmed as input/output port
– Mode 1:
• PA, PB can be used as input/output ports with handshaking
• PCU{PC3~PC7}, PCL{PC0~PC2} are used as handshake lines for PA and PB, respectively
– Mode 2:
• Only PA can be used for bidirectional handshake data transfer
• PCU{PC3~PC7} are used as handshake lines for PA

• Bit set/reset (BSR) mode

– Only PC can be used as output port
– Each line of PC can be set/reset individually

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Control Register & Op. Modes

• An 8-bit internal register in 8255
• Selected when A1=1, A0=1
• Mode selection word
– Input/output modes

1 D6 D5 D4 D3 D2 D1 D0

– BSR mode
0 D6 D5 D4 D3 D2 D1 D0

Microprocessors and Interfacing 17

Mode Selection with Control Register

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Select Input/output
Mode Examples
1. Write ASM instructions for setting the 8255 in simple I/O mode with PA
and PB being output port and PC being input port.
MOV AL, 10001001B
MOV DX, ControlPort
OUT DX, AL

2. Assume that the address of the control register of the 8255 is 63H, give
out the instructions that set up the 8255 in mode 0 where PA, PB and PCU
are used as input ports and PCL is used as output port.
MOV AL, 10011010B
OUT 63H, AL

Microprocessors and Interfacing 19

Example: 8255 in figure below is configured as follows:

port A as input, B as output, and all the bits of port C as output.
a) Find the port addresses assigned to ports A, B, C, and the control register.

b) Find the control byte (word) for this configuration.

The control word is 90H, or 1001 0000
a) Program the ports to input data from port A and send it to both ports B
and C.
CNTLBYTE EQU 90H ;PA=in, PB=out, PC=out
PORTA EQU 310H
PORTB EQU 311H
PORTC EQU 312H
CNTLREG EQU 313H
…
MOV AL,CNTLBYTE ;control byte PA=in, PB=out, PC=out
MOV DX,CNTLREG ;load control reg address
OUT DX,AL ;send it to control register
MOV DX,PORTA ;load PA address
IN AL,DX ;get the data from PA
MOV DX, PORTB ;load PB address
OUT DX,AL ;send it to PB
MOV DX, PORTC ;load PC address
OUT DX,AL ;and to PC

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Next Lecture
• 8086 Interrupts

Microprocessors and Interfacing 21

SPARE SLIDES

Microprocessors and Interfacing 22

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Time in Embedded Real-time Systems

• Time is an inherent part of real-time systems
• Problem: Instruction-sets do not expose the
precise timing of the underlying hardware to
the programmer
• Solutions?
1. Number of executed instructions × cycle time
– Problems: imprecise timing (especially with
modern hardware), inflexible software
2. A dedicated hardware for timing
Microprocessors and Interfacing 23

Simplified Structure of a
Timer/Counter

Microprocessors and Interfacing 24

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The 8253/54 PIT

• The 8253/54
Programmable interval D0 1 24 Vcc
timer is used to generate a D1 2 23 WR
D2 3 22 RD
lower frequency for D3 4 21 CS
D4 5 20 A1
various uses e.g., D5 6 19 A0
8253
– Event counter D6 7 18 CLK2
D7 8 17 OUT2
– Accurate time delays CLK0 9 16 GATE2
OUT0 10 15 CLK1
• 8253 used in the first PC GATE0 11 14 GATE1
decoded at ports 40H–43H GND 12 13 OUT1

– Replaced with 8254 later

Microprocessors and Interfacing 25

Interface to the System

➢ There are three independent counters.
➢ The input frequency can be divided from 1
to 65536 (Binary), or from 1 to 10000 (BCD)
➢ Shape of the output frequency:
❖Square-wave
❖One-shot
❖Square-wave with various duty cycles.

➢ Gate is used to enable (High) or disable

(Low) the counter.
➢ Bidirectional bus D0-D7 is connected to
D0-D7 of the system bus (even addresses).

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Internal Structure

To operate a 16-bit down counter

❖ a 16-bit count is loaded in the counter
❖ begins to decrement the count until it
reaches 0
❖ generates a pulse that can be used to
interrupt the CPU
Microprocessors and Interfacing 27

Summary of the Features

• Three independent 16-bit down counters
• 8254 can handle inputs from DC to 10 MHz (5MHz 8254-5
8MHz 8254 10MHz 8254-2) whereas 8253 can operate up
to 2.6 MHz
• Three counters are identical and pre-settable, and can be
programmed for either binary or BCD count
• Counter can be programmed in six different modes
• Compatible with all Intel and most other microprocessors
• 8254 has a powerful command called READ BACK
command which allows the user to check the count value,
programmed mode and current mode and current status of
the counter

Microprocessors and Interfacing 28

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8253 Bus Access

Data bus buffer
How to
• interface the 8253/4 to the R/W 16-bit
system data bus counters
• Bi-directional, tri-state, 8-bit from a
single
address?
Read/Write control logic
• ~CS
– Tied to a decoded address /CS /RD /WR A1A0 FUNCTION
• ~RD, ~WR 0 1 0 00 Write counter0 (to CR0)
– In isolated I/O: ~IOR, ~IOW 0 1 0 01 Write counter1 (to CR1)
– Memory-mapped I/O: ~MEMR, 0 1 0 10 Write counter2 (to CR2)
~MEMW 0 1 0 11 Write control port

• A1, A0 0 0 1 00 Read counter0 (from OL0)

0 0 1 01 Read counter1 (from OL1)
– Select the control word register
0 0 1 10 Read counter2 (from OL2)
and counters
0 0 1 11 Read control port (for 8254)
– usually connected to address lines
A1, A0 1 X X XX Not available

Microprocessors and Interfacing 29

Write/Read Operations
• WRITE
– Write a control word into control register
– Load the low-order byte of a count in the counter register
– Load the high-order byte of a count in the counter register
• READ
– Simple Read: two I/O read operations, first one for low-order byte and
then one for the high order byte
– Counter Latch Command: one I/O write operation used to write a
control word to the control register to latch a count in the output
latch, then two I/O read operations are used to read the latched count
as in Simple Read.
➢ Read-Back Command: for 8254 only

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Operation of 8253
• 8253 takes one CLK pulse
to convey the count from
CR to CE
• CE will start to count only
when GATE = 1
– When to check the GATE?
On every CLK pulse’s rising
(0-to-1) edge
– When to count down?
On every CLK pulse’s falling
(1-to-0) edge

Microprocessors and Interfacing 31

Modes of Operation
• Mode 0: Interrupt
on Terminal Count
• Mode 1: Hardware
Retriggerable One-
shot
• Mode 2: Rate
Generator
• Mode 3: Square
Wave Rate
Generator
• Mode 4: Software
Triggered Strobe
• Mode 5: Hardware
Triggered Strobe
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8253/4 Gate Pin Operation

Modes 0 and 4
• Counting is suspended while GATE is low
• Resumed while GATE is high
Modes 1 and 5
• Rising edge of GATE starts counting
• GATE may go low without affecting counting
• Another rising edge will restart the count from
the beginning
Modes 2 and 3
• GATE low forces OUT high immediately
(without waiting for a clock pulse) and resets
the counter (on the next clock falling edge)
• When GATE goes high again, counting restarts
from the beginning

Microprocessors and Interfacing 33

Control Word Format

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Programming Example

Microprocessors and Interfacing 35

Example:
Setting Up a Counter

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Example
• The frequency of CLK is
2MHz, write initiation program D7~D0 D7~D0 OUT0
to let counter 0 generate an OUT1
IOR RD OUT2
interruption request after IOW WR GATE0
100μs, let counter 1 generate A1 A1
GATE1
A0 A0
50% duty cycle square wave GATE2
IOR &
with a period of 10μs, and let IOW
G 8253 CLK0
CLK1
counter 2 generate a negative A15 & CLK2
G2A

～
pulse every 1ms. A8 CS
A2 74LS138
A7 +
A6 G2B Y0
A5 A
A4 B
A3 C

Microprocessors and Interfacing 37

MOV DX, 0FF07H

MOV AL, 00010000B ;counter 0, write LSB only, mode 0, binary
OUT DX, AL
MOV AL, 01010110B ;counter 1, write LSB only, mode 3, binary
OUT DX, AL
MOV DX, 0FF04H
MOV AL, 200 ; initial count for counter 0
OUT DX, AL
MOV DX, 0FF05H
MOV AL, 20 ;initial count for counter 1
OUT DX, AL
MOV DX, 0FF07H
MOV AL, 10110100B ;counter 2, write LSB and MSB, mode 2
OUT DX, AL
MOV DX, 0FF06H
MOV AX, 2000 ; initial count for counter 2
OUT DX, AL
MOV AL, AH
OUT DX, AL

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Mode 0: Interrupt on Terminal Count I

• Normal Operation:
– The output will be initially low after CPU writes count
the mode set operation; into the CR
– After the count is loaded into the
First CLK Count is conveyed
selected CR the output will remain low to the CE
pulse
– When the terminal count is reached, Second CLK
the output will go high and remain pulse Counting down
high until the selected counter is
reloaded Output signal
when reaches 0
– Output: N clock pulses low and high
afterwards after writing a count

Microprocessors and Interfacing 39

Mode 0: Interrupt on Terminal Count II

• Gate disable:
– Gate = 1 enables counting
– Gate = 0 disables counting
• New count:
– If a new count is written to the counter, it will be
loaded on the next CLK pulse and counting will
continue from the new count
– In case of two byte count:
• Writing the first byte disables the current counting
• Writing the second byte loads the new count on the next CLK pulse and
counting will continue from the new count

Microprocessors and Interfacing 40

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Mode 0: Interrupt on Terminal Count III

When loading a new count N, the actual

number of CLK pulses in OUT is N+1

Does not automatically repeat

Microprocessors and Interfacing 41

Mode 1:
Hardware Retriggerable One-shot I
• Normal Operation:
– The output will be initially high after the mode set
operation;
– The output will go low on the CLK pulse following
the rising (0-to-1) edge of the gate input;
– The output will go high on the terminal count and
remain high until the next rising edge of the gate
input.
– Output: one-shot of N clock pulses on every
trigger

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Mode 1:
Hardware Retriggerable One-shot II
• Retriggering:
– retriggerable, hence the output will remain low for
the full count after any rising edge of the gate input
• New count:
– If the counter is loaded during one shot pulse, the
current one shot is not affected unless the counter is
retriggered
– If retriggered, the counter is loaded with the new
count and the one-shot pulse continues until the new
count expires
Microprocessors and Interfacing 43

Mode 1:
Hardware Retriggerable One-shot III

When loading a new count N, the current

counting will not be affected

Does not automatically repeat

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Mode 2: Rate Generator I

• Also called divide-by-N counter
• Normal Operation:
– The output will be initially high;
– The output will go low for one clock pulse before
the terminal count;
– The output then goes high, the counter reloads
the initial count and the process is repeated
– Output: periodical signal with a period of N-1
clock pulses high and 1 clock pulse low
Microprocessors and Interfacing 45

Mode 2: Rate Generator II

• Gate disable:
– If Gate=1 it enables a counting otherwise it disables counting (Gate=0)
– If Gate goes low during a low output pulse, output is set immediately
high
• New count:
– The current counting sequence is not affected when the new count is
written
– If a trigger (a rising edge of GATE) is received after writing a new count
but before the end of the current period, the new count will be loaded
with the new count on the next CLK pulse and counting will continue
from the new count
– Otherwise, the new count will be loaded at the end of the current
counting cycle
– Note : In mode 2, a count of 1 is illegal. Why?

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Mode 2: Rate Generator III

When loading a new count N, the current

counting will not be affected

Automatically repeat on terminal count

Microprocessors and Interfacing 47

Mode 3:
Square Wave Rate Generator I
• Normal Operation:
– The output will be initially high;
– For even count, counter is decremented by 2 on the falling edge of each clock
pulse; when reaches terminal count, the state of the output is changed and
the counter is reloaded with the full count and the whole process is repeated
– For odd count, the first clock pulse decrements the count by 1. Subsequent
clock pulses decrement the clock by 2. After timeout, the output goes low and
the full count is reloaded. The first clock pulse (following the reload)
decrements the count by 3 and subsequent clock pulse decrement the count
by two. Then the whole process is repeated.
– Output: if the count is odd, the output will be high for (n+1)/2
counts and low for (n-1)/2 counts.

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Mode 3:
Square Wave Rate Generator II
• Gate disable:
– If Gate is 1 counting is enabled otherwise it is disabled.
– If Gate goes low while output is low, output is set high immediately.
After this, When Gate goes high, the counter is loaded with the initial
count on the next clock pulse and the sequence is repeated.

Microprocessors and Interfacing 49

Mode 3:
Square Wave Rate Generator III
• New count:
– The current counting sequence is not affected when the new count is
written.
– If a trigger is received after writing a new count but before the end of
the current half-cycle of the square wave, the counter will be loaded
with the new count on the next CLK pulse and counting will continue
from the new count.
– Otherwise, the new count will be loaded at end of the current half-
cycle.

When loading a new count N, the current

half will not be affected

Automatically repeat on terminal count

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Mode 4:
Software Triggered Strobe I
• Similar to mode 2 except that the counter is not
auto-reloaded
• Normal Operation:
– The output will be initially high;
– The output will go low for one CLK pulse after the terminal count
• Gate disable:
– If Gate is one, the counting is enabled; otherwise, it is disabled
• New count:
– If a new count is written during counting, it will be loaded on the next CLK
pulse and counting will continue from the new count. If the count is two
byte then:
• Writing the first byte has no effect on counting
• Writing the second byte allows the new count to be loaded on the next CLK pulse

Microprocessors and Interfacing 51

Mode 4: Software Triggered Strobe II

When loading a new count N, the actual

number of CLK pulses in OUT is N+1

Automatically repeat

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Mode 5: Hardware Triggered Strobe

(Retriggerable) I
• Similar to mode 4 except that triggered by GATE.
• Normal Operation:
– The output will be initially high;
– The counting is triggered by the rising edge of the Gate
– The output will go low for one CLK pulse after the terminal count
• Retriggering:
– If the triggering occurs during the counting, the initial count is loaded on
the next CLK pulse and the counting will be continued until the terminal
count is reached
• New count:
– the current counting sequence will not be affected. If the trigger occurs
after the new count but before the terminal count, the counter will be
loaded with the new count on the next CLK pulse and counting will
continue from there

Microprocessors and Interfacing 53

Mode 5: Hardware Triggered Strobe

(Retriggerable) II

When loading a new count N, the current

counting will not be affected

Automatically repeat on terminal count

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